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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / x86 / include / asm / uv / uv_bau.h
blob57ab86d94d644e0881cb2397a50b57538a16ea84
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 128
37 #define MAX_CPUS_PER_SOCKET 64
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_GNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define cpubit_isset(cpu, bau_local_cpumask) \
59 test_bit((cpu), (bau_local_cpumask).bits)
60
61 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
62 /*
63 * UV2: Bit 19 selects between
64 * (0): 10 microsecond timebase and
65 * (1): 80 microseconds
66 * we're using 560us, similar to UV1: 65 units of 10us
67 */
68 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
69 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
70
71 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
72 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
73 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
74 /* assuming UV3 is the same */
75
76 #define BAU_MISC_CONTROL_MULT_MASK 3
77
78 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
79 /* [30:28] URGENCY_7 an index into a table of times */
80 #define BAU_URGENCY_7_SHIFT 28
81 #define BAU_URGENCY_7_MASK 7
82
83 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
84 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
85 #define BAU_TRANS_SHIFT 40
86 #define BAU_TRANS_MASK 0x3f
87
88 /*
89 * shorten some awkward names
90 */
91 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
92 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
93 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
94 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
95 #define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
96 #define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
97 #define write_gmmr uv_write_global_mmr64
98 #define write_lmmr uv_write_local_mmr
99 #define read_lmmr uv_read_local_mmr
100 #define read_gmmr uv_read_global_mmr64
101
102 /*
103 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
104 */
105 #define DS_IDLE 0
106 #define DS_ACTIVE 1
107 #define DS_DESTINATION_TIMEOUT 2
108 #define DS_SOURCE_TIMEOUT 3
109 /*
110 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
111 * values 1 and 3 will not occur
112 * Decoded meaning ERROR BUSY AUX ERR
113 * ------------------------------- ---- ----- -------
114 * IDLE 0 0 0
115 * BUSY (active) 0 1 0
116 * SW Ack Timeout (destination) 1 0 0
117 * SW Ack INTD rejected (strong NACK) 1 0 1
118 * Source Side Time Out Detected 1 1 0
119 * Destination Side PUT Failed 1 1 1
120 */
121 #define UV2H_DESC_IDLE 0
122 #define UV2H_DESC_BUSY 2
123 #define UV2H_DESC_DEST_TIMEOUT 4
124 #define UV2H_DESC_DEST_STRONG_NACK 5
125 #define UV2H_DESC_SOURCE_TIMEOUT 6
126 #define UV2H_DESC_DEST_PUT_ERR 7
127
128 /*
129 * delay for 'plugged' timeout retries, in microseconds
130 */
131 #define PLUGGED_DELAY 10
132
133 /*
134 * threshholds at which to use IPI to free resources
135 */
136 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
137 #define PLUGSB4RESET 100
138 /* after this many consecutive timeouts, use IPI to release resources */
139 #define TIMEOUTSB4RESET 1
140 /* at this number uses of IPI to release resources, giveup the request */
141 #define IPI_RESET_LIMIT 1
142 /* after this # consecutive successes, bump up the throttle if it was lowered */
143 #define COMPLETE_THRESHOLD 5
144 /* after this # of giveups (fall back to kernel IPI's) disable the use of
145 the BAU for a period of time */
146 #define GIVEUP_LIMIT 100
147
148 #define UV_LB_SUBNODEID 0x10
149
150 /* these two are the same for UV1 and UV2: */
151 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
152 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
153 /* 4 bits of software ack period */
154 #define UV2_ACK_MASK 0x7UL
155 #define UV2_ACK_UNITS_SHFT 3
156 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
157
158 /*
159 * number of entries in the destination side payload queue
160 */
161 #define DEST_Q_SIZE 20
162 /*
163 * number of destination side software ack resources
164 */
165 #define DEST_NUM_RESOURCES 8
166 /*
167 * completion statuses for sending a TLB flush message
168 */
169 #define FLUSH_RETRY_PLUGGED 1
170 #define FLUSH_RETRY_TIMEOUT 2
171 #define FLUSH_GIVEUP 3
172 #define FLUSH_COMPLETE 4
173
174 /*
175 * tuning the action when the numalink network is extremely delayed
176 */
177 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
178 microseconds */
179 #define CONGESTED_REPS 10 /* long delays averaged over
180 this many broadcasts */
181 #define DISABLED_PERIOD 10 /* time for the bau to be
182 disabled, in seconds */
183 /* see msg_type: */
184 #define MSG_NOOP 0
185 #define MSG_REGULAR 1
186 #define MSG_RETRY 2
187
188 /*
189 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
190 * If the 'multilevel' flag in the header portion of the descriptor
191 * has been set to 0, then endpoint multi-unicast mode is selected.
192 * The distribution specification (32 bytes) is interpreted as a 256-bit
193 * distribution vector. Adjacent bits correspond to consecutive even numbered
194 * nodeIDs. The result of adding the index of a given bit to the 15-bit
195 * 'base_dest_nasid' field of the header corresponds to the
196 * destination nodeID associated with that specified bit.
197 */
198 struct pnmask {
199 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
200 };
201
202 /*
203 * mask of cpu's on a uvhub
204 * (during initialization we need to check that unsigned long has
205 * enough bits for max. cpu's per uvhub)
206 */
207 struct bau_local_cpumask {
208 unsigned long bits;
209 };
210
211 /*
212 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
213 * only 12 bytes (96 bits) of the payload area are usable.
214 * An additional 3 bytes (bits 27:4) of the header address are carried
215 * to the next bytes of the destination payload queue.
216 * And an additional 2 bytes of the header Suppl_A field are also
217 * carried to the destination payload queue.
218 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
219 * of the destination payload queue, which is written by the hardware
220 * with the s/w ack resource bit vector.
221 * [ effective message contents (16 bytes (128 bits) maximum), not counting
222 * the s/w ack bit vector ]
223 */
224
225 /*
226 * The payload is software-defined for INTD transactions
227 */
228 struct bau_msg_payload {
229 unsigned long address; /* signifies a page or all
230 TLB's of the cpu */
231 /* 64 bits */
232 unsigned short sending_cpu; /* filled in by sender */
233 /* 16 bits */
234 unsigned short acknowledge_count; /* filled in by destination */
235 /* 16 bits */
236 unsigned int reserved1:32; /* not usable */
237 };
238
239
240 /*
241 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
242 * see table 4.2.3.0.1 in broacast_assist spec.
243 */
244 struct uv1_bau_msg_header {
245 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
246 /* bits 5:0 */
247 unsigned int base_dest_nasid:15; /* nasid of the first bit */
248 /* bits 20:6 */ /* in uvhub map */
249 unsigned int command:8; /* message type */
250 /* bits 28:21 */
251 /* 0x38: SN3net EndPoint Message */
252 unsigned int rsvd_1:3; /* must be zero */
253 /* bits 31:29 */
254 /* int will align on 32 bits */
255 unsigned int rsvd_2:9; /* must be zero */
256 /* bits 40:32 */
257 /* Suppl_A is 56-41 */
258 unsigned int sequence:16; /* message sequence number */
259 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
260 /* Address field (96:57) is
261 never used as an address
262 (these are address bits
263 42:3) */
264
265 unsigned int rsvd_3:1; /* must be zero */
266 /* bit 57 */
267 /* address bits 27:4 are payload */
268 /* these next 24 (58-81) bits become bytes 12-14 of msg */
269 /* bits 65:58 land in byte 12 */
270 unsigned int replied_to:1; /* sent as 0 by the source to
271 byte 12 */
272 /* bit 58 */
273 unsigned int msg_type:3; /* software type of the
274 message */
275 /* bits 61:59 */
276 unsigned int canceled:1; /* message canceled, resource
277 is to be freed*/
278 /* bit 62 */
279 unsigned int payload_1a:1; /* not currently used */
280 /* bit 63 */
281 unsigned int payload_1b:2; /* not currently used */
282 /* bits 65:64 */
283
284 /* bits 73:66 land in byte 13 */
285 unsigned int payload_1ca:6; /* not currently used */
286 /* bits 71:66 */
287 unsigned int payload_1c:2; /* not currently used */
288 /* bits 73:72 */
289
290 /* bits 81:74 land in byte 14 */
291 unsigned int payload_1d:6; /* not currently used */
292 /* bits 79:74 */
293 unsigned int payload_1e:2; /* not currently used */
294 /* bits 81:80 */
295
296 unsigned int rsvd_4:7; /* must be zero */
297 /* bits 88:82 */
298 unsigned int swack_flag:1; /* software acknowledge flag */
299 /* bit 89 */
300 /* INTD trasactions at
301 destination are to wait for
302 software acknowledge */
303 unsigned int rsvd_5:6; /* must be zero */
304 /* bits 95:90 */
305 unsigned int rsvd_6:5; /* must be zero */
306 /* bits 100:96 */
307 unsigned int int_both:1; /* if 1, interrupt both sockets
308 on the uvhub */
309 /* bit 101*/
310 unsigned int fairness:3; /* usually zero */
311 /* bits 104:102 */
312 unsigned int multilevel:1; /* multi-level multicast
313 format */
314 /* bit 105 */
315 /* 0 for TLB: endpoint multi-unicast messages */
316 unsigned int chaining:1; /* next descriptor is part of
317 this activation*/
318 /* bit 106 */
319 unsigned int rsvd_7:21; /* must be zero */
320 /* bits 127:107 */
321 };
322
323 /*
324 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
325 * see figure 9-2 of harp_sys.pdf
326 * assuming UV3 is the same
327 */
328 struct uv2_3_bau_msg_header {
329 unsigned int base_dest_nasid:15; /* nasid of the first bit */
330 /* bits 14:0 */ /* in uvhub map */
331 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
332 /* bits 19:15 */
333 unsigned int rsvd_1:1; /* must be zero */
334 /* bit 20 */
335 /* Address bits 59:21 */
336 /* bits 25:2 of address (44:21) are payload */
337 /* these next 24 bits become bytes 12-14 of msg */
338 /* bits 28:21 land in byte 12 */
339 unsigned int replied_to:1; /* sent as 0 by the source to
340 byte 12 */
341 /* bit 21 */
342 unsigned int msg_type:3; /* software type of the
343 message */
344 /* bits 24:22 */
345 unsigned int canceled:1; /* message canceled, resource
346 is to be freed*/
347 /* bit 25 */
348 unsigned int payload_1:3; /* not currently used */
349 /* bits 28:26 */
350
351 /* bits 36:29 land in byte 13 */
352 unsigned int payload_2a:3; /* not currently used */
353 unsigned int payload_2b:5; /* not currently used */
354 /* bits 36:29 */
355
356 /* bits 44:37 land in byte 14 */
357 unsigned int payload_3:8; /* not currently used */
358 /* bits 44:37 */
359
360 unsigned int rsvd_2:7; /* reserved */
361 /* bits 51:45 */
362 unsigned int swack_flag:1; /* software acknowledge flag */
363 /* bit 52 */
364 unsigned int rsvd_3a:3; /* must be zero */
365 unsigned int rsvd_3b:8; /* must be zero */
366 unsigned int rsvd_3c:8; /* must be zero */
367 unsigned int rsvd_3d:3; /* must be zero */
368 /* bits 74:53 */
369 unsigned int fairness:3; /* usually zero */
370 /* bits 77:75 */
371
372 unsigned int sequence:16; /* message sequence number */
373 /* bits 93:78 Suppl_A */
374 unsigned int chaining:1; /* next descriptor is part of
375 this activation*/
376 /* bit 94 */
377 unsigned int multilevel:1; /* multi-level multicast
378 format */
379 /* bit 95 */
380 unsigned int rsvd_4:24; /* ordered / source node /
381 source subnode / aging
382 must be zero */
383 /* bits 119:96 */
384 unsigned int command:8; /* message type */
385 /* bits 127:120 */
386 };
387
388 /* Abstracted BAU functions */
389 struct bau_operations {
390 unsigned long (*read_l_sw_ack)(void);
391 unsigned long (*read_g_sw_ack)(int pnode);
392 unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
393 void (*write_l_sw_ack)(unsigned long mmr);
394 void (*write_g_sw_ack)(int pnode, unsigned long mmr);
395 void (*write_payload_first)(int pnode, unsigned long mmr);
396 void (*write_payload_last)(int pnode, unsigned long mmr);
397 };
398
399 /*
400 * The activation descriptor:
401 * The format of the message to send, plus all accompanying control
402 * Should be 64 bytes
403 */
404 struct bau_desc {
405 struct pnmask distribution;
406 /*
407 * message template, consisting of header and payload:
408 */
409 union bau_msg_header {
410 struct uv1_bau_msg_header uv1_hdr;
411 struct uv2_3_bau_msg_header uv2_3_hdr;
412 } header;
413
414 struct bau_msg_payload payload;
415 };
416 /* UV1:
417 * -payload-- ---------header------
418 * bytes 0-11 bits 41-56 bits 58-81
419 * A B (2) C (3)
420 *
421 * A/B/C are moved to:
422 * A C B
423 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
424 * ------------payload queue-----------
425 */
426 /* UV2:
427 * -payload-- ---------header------
428 * bytes 0-11 bits 70-78 bits 21-44
429 * A B (2) C (3)
430 *
431 * A/B/C are moved to:
432 * A C B
433 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
434 * ------------payload queue-----------
435 */
436
437 /*
438 * The payload queue on the destination side is an array of these.
439 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
440 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
441 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
442 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
443 * swack_vec and payload_2)
444 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
445 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
446 * operation."
447 */
448 struct bau_pq_entry {
449 unsigned long address; /* signifies a page or all TLB's
450 of the cpu */
451 /* 64 bits, bytes 0-7 */
452 unsigned short sending_cpu; /* cpu that sent the message */
453 /* 16 bits, bytes 8-9 */
454 unsigned short acknowledge_count; /* filled in by destination */
455 /* 16 bits, bytes 10-11 */
456 /* these next 3 bytes come from bits 58-81 of the message header */
457 unsigned short replied_to:1; /* sent as 0 by the source */
458 unsigned short msg_type:3; /* software message type */
459 unsigned short canceled:1; /* sent as 0 by the source */
460 unsigned short unused1:3; /* not currently using */
461 /* byte 12 */
462 unsigned char unused2a; /* not currently using */
463 /* byte 13 */
464 unsigned char unused2; /* not currently using */
465 /* byte 14 */
466 unsigned char swack_vec; /* filled in by the hardware */
467 /* byte 15 (bits 127:120) */
468 unsigned short sequence; /* message sequence number */
469 /* bytes 16-17 */
470 unsigned char unused4[2]; /* not currently using bytes 18-19 */
471 /* bytes 18-19 */
472 int number_of_cpus; /* filled in at destination */
473 /* 32 bits, bytes 20-23 (aligned) */
474 unsigned char unused5[8]; /* not using */
475 /* bytes 24-31 */
476 };
477
478 struct msg_desc {
479 struct bau_pq_entry *msg;
480 int msg_slot;
481 struct bau_pq_entry *queue_first;
482 struct bau_pq_entry *queue_last;
483 };
484
485 struct reset_args {
486 int sender;
487 };
488
489 /*
490 * This structure is allocated per_cpu for UV TLB shootdown statistics.
491 */
492 struct ptc_stats {
493 /* sender statistics */
494 unsigned long s_giveup; /* number of fall backs to
495 IPI-style flushes */
496 unsigned long s_requestor; /* number of shootdown
497 requests */
498 unsigned long s_stimeout; /* source side timeouts */
499 unsigned long s_dtimeout; /* destination side timeouts */
500 unsigned long s_strongnacks; /* number of strong nack's */
501 unsigned long s_time; /* time spent in sending side */
502 unsigned long s_retriesok; /* successful retries */
503 unsigned long s_ntargcpu; /* total number of cpu's
504 targeted */
505 unsigned long s_ntargself; /* times the sending cpu was
506 targeted */
507 unsigned long s_ntarglocals; /* targets of cpus on the local
508 blade */
509 unsigned long s_ntargremotes; /* targets of cpus on remote
510 blades */
511 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
512 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
513 unsigned long s_ntarguvhub; /* total number of uvhubs
514 targeted */
515 unsigned long s_ntarguvhub16; /* number of times target
516 hubs >= 16*/
517 unsigned long s_ntarguvhub8; /* number of times target
518 hubs >= 8 */
519 unsigned long s_ntarguvhub4; /* number of times target
520 hubs >= 4 */
521 unsigned long s_ntarguvhub2; /* number of times target
522 hubs >= 2 */
523 unsigned long s_ntarguvhub1; /* number of times target
524 hubs == 1 */
525 unsigned long s_resets_plug; /* ipi-style resets from plug
526 state */
527 unsigned long s_resets_timeout; /* ipi-style resets from
528 timeouts */
529 unsigned long s_busy; /* status stayed busy past
530 s/w timer */
531 unsigned long s_throttles; /* waits in throttle */
532 unsigned long s_retry_messages; /* retry broadcasts */
533 unsigned long s_bau_reenabled; /* for bau enable/disable */
534 unsigned long s_bau_disabled; /* for bau enable/disable */
535 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
536 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
537 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
538 unsigned long s_overipilimit; /* over the ipi reset limit */
539 unsigned long s_giveuplimit; /* disables, over giveup limit*/
540 unsigned long s_enters; /* entries to the driver */
541 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */
542 unsigned long s_plugged; /* plugged by h/w bug*/
543 unsigned long s_congested; /* giveup on long wait */
544 /* destination statistics */
545 unsigned long d_alltlb; /* times all tlb's on this
546 cpu were flushed */
547 unsigned long d_onetlb; /* times just one tlb on this
548 cpu was flushed */
549 unsigned long d_multmsg; /* interrupts with multiple
550 messages */
551 unsigned long d_nomsg; /* interrupts with no message */
552 unsigned long d_time; /* time spent on destination
553 side */
554 unsigned long d_requestee; /* number of messages
555 processed */
556 unsigned long d_retries; /* number of retry messages
557 processed */
558 unsigned long d_canceled; /* number of messages canceled
559 by retries */
560 unsigned long d_nocanceled; /* retries that found nothing
561 to cancel */
562 unsigned long d_resets; /* number of ipi-style requests
563 processed */
564 unsigned long d_rcanceled; /* number of messages canceled
565 by resets */
566 };
567
568 struct tunables {
569 int *tunp;
570 int deflt;
571 };
572
573 struct hub_and_pnode {
574 short uvhub;
575 short pnode;
576 };
577
578 struct socket_desc {
579 short num_cpus;
580 short cpu_number[MAX_CPUS_PER_SOCKET];
581 };
582
583 struct uvhub_desc {
584 unsigned short socket_mask;
585 short num_cpus;
586 short uvhub;
587 short pnode;
588 struct socket_desc socket[2];
589 };
590
591 /*
592 * one per-cpu; to locate the software tables
593 */
594 struct bau_control {
595 struct bau_desc *descriptor_base;
596 struct bau_pq_entry *queue_first;
597 struct bau_pq_entry *queue_last;
598 struct bau_pq_entry *bau_msg_head;
599 struct bau_control *uvhub_master;
600 struct bau_control *socket_master;
601 struct ptc_stats *statp;
602 cpumask_t *cpumask;
603 unsigned long timeout_interval;
604 unsigned long set_bau_on_time;
605 atomic_t active_descriptor_count;
606 int plugged_tries;
607 int timeout_tries;
608 int ipi_attempts;
609 int conseccompletes;
610 bool nobau;
611 short baudisabled;
612 short cpu;
613 short osnode;
614 short uvhub_cpu;
615 short uvhub;
616 short uvhub_version;
617 short cpus_in_socket;
618 short cpus_in_uvhub;
619 short partition_base_pnode;
620 short busy; /* all were busy (war) */
621 unsigned short message_number;
622 unsigned short uvhub_quiesce;
623 short socket_acknowledge_count[DEST_Q_SIZE];
624 cycles_t send_message;
625 cycles_t period_end;
626 cycles_t period_time;
627 spinlock_t uvhub_lock;
628 spinlock_t queue_lock;
629 spinlock_t disable_lock;
630 /* tunables */
631 int max_concurr;
632 int max_concurr_const;
633 int plugged_delay;
634 int plugsb4reset;
635 int timeoutsb4reset;
636 int ipi_reset_limit;
637 int complete_threshold;
638 int cong_response_us;
639 int cong_reps;
640 cycles_t disabled_period;
641 int period_giveups;
642 int giveup_limit;
643 long period_requests;
644 struct hub_and_pnode *thp;
645 };
646
647 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
648 {
649 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
650 }
651
652 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
653 {
654 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
655 }
656
657 static inline void write_mmr_activation(unsigned long index)
658 {
659 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
660 }
661
662 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
663 {
664 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
665 }
666
667 static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
668 {
669 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
670 }
671
672 static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
673 {
674 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
675 }
676
677 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
678 {
679 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
680 }
681
682 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
683 {
684 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
685 }
686
687 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
688 {
689 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
690 }
691
692 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
693 {
694 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
695 }
696
697 static inline unsigned long read_mmr_misc_control(int pnode)
698 {
699 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
700 }
701
702 static inline void write_mmr_sw_ack(unsigned long mr)
703 {
704 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
705 }
706
707 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
708 {
709 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
710 }
711
712 static inline unsigned long read_mmr_sw_ack(void)
713 {
714 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
715 }
716
717 static inline unsigned long read_gmmr_sw_ack(int pnode)
718 {
719 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
720 }
721
722 static inline void write_mmr_proc_sw_ack(unsigned long mr)
723 {
724 uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
725 }
726
727 static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
728 {
729 write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
730 }
731
732 static inline unsigned long read_mmr_proc_sw_ack(void)
733 {
734 return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
735 }
736
737 static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
738 {
739 return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
740 }
741
742 static inline void write_mmr_data_config(int pnode, unsigned long mr)
743 {
744 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
745 }
746
747 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
748 {
749 return constant_test_bit(uvhub, &dstp->bits[0]);
750 }
751 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
752 {
753 __set_bit(pnode, &dstp->bits[0]);
754 }
755 static inline void bau_uvhubs_clear(struct pnmask *dstp,
756 int nbits)
757 {
758 bitmap_zero(&dstp->bits[0], nbits);
759 }
760 static inline int bau_uvhub_weight(struct pnmask *dstp)
761 {
762 return bitmap_weight((unsigned long *)&dstp->bits[0],
763 UV_DISTRIBUTION_SIZE);
764 }
765
766 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
767 {
768 bitmap_zero(&dstp->bits, nbits);
769 }
770
771 extern void uv_bau_message_intr1(void);
772 #ifdef CONFIG_TRACING
773 #define trace_uv_bau_message_intr1 uv_bau_message_intr1
774 #endif
775 extern void uv_bau_timeout_intr1(void);
776
777 struct atomic_short {
778 short counter;
779 };
780
781 /*
782 * atomic_read_short - read a short atomic variable
783 * @v: pointer of type atomic_short
784 *
785 * Atomically reads the value of @v.
786 */
787 static inline int atomic_read_short(const struct atomic_short *v)
788 {
789 return v->counter;
790 }
791
792 /*
793 * atom_asr - add and return a short int
794 * @i: short value to add
795 * @v: pointer of type atomic_short
796 *
797 * Atomically adds @i to @v and returns @i + @v
798 */
799 static inline int atom_asr(short i, struct atomic_short *v)
800 {
801 short __i = i;
802 asm volatile(LOCK_PREFIX "xaddw %0, %1"
803 : "+r" (i), "+m" (v->counter)
804 : : "memory");
805 return i + __i;
806 }
807
808 /*
809 * conditionally add 1 to *v, unless *v is >= u
810 * return 0 if we cannot add 1 to *v because it is >= u
811 * return 1 if we can add 1 to *v because it is < u
812 * the add is atomic
813 *
814 * This is close to atomic_add_unless(), but this allows the 'u' value
815 * to be lowered below the current 'v'. atomic_add_unless can only stop
816 * on equal.
817 */
818 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
819 {
820 spin_lock(lock);
821 if (atomic_read(v) >= u) {
822 spin_unlock(lock);
823 return 0;
824 }
825 atomic_inc(v);
826 spin_unlock(lock);
827 return 1;
828 }
829
830 #endif /* _ASM_X86_UV_UV_BAU_H */
Linux with added FPC-III support