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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / x86 / include / asm / vmx.h
blobcc54b70265674e8149239b667d63a42e3aa4b58d
1 /*
2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 * A few random additions are:
19 * Copyright (C) 2006 Qumranet
20 * Avi Kivity <avi@qumranet.com>
21 * Yaniv Kamay <yaniv@qumranet.com>
22 *
23 */
24 #ifndef VMX_H
25 #define VMX_H
26
27
28 #include <linux/bitops.h>
29 #include <linux/types.h>
30 #include <uapi/asm/vmx.h>
31
32 /*
33 * Definitions of Primary Processor-Based VM-Execution Controls.
34 */
35 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
36 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
37 #define CPU_BASED_HLT_EXITING 0x00000080
38 #define CPU_BASED_INVLPG_EXITING 0x00000200
39 #define CPU_BASED_MWAIT_EXITING 0x00000400
40 #define CPU_BASED_RDPMC_EXITING 0x00000800
41 #define CPU_BASED_RDTSC_EXITING 0x00001000
42 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000
43 #define CPU_BASED_CR3_STORE_EXITING 0x00010000
44 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
45 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
46 #define CPU_BASED_TPR_SHADOW 0x00200000
47 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
48 #define CPU_BASED_MOV_DR_EXITING 0x00800000
49 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
50 #define CPU_BASED_USE_IO_BITMAPS 0x02000000
51 #define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
52 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000
53 #define CPU_BASED_MONITOR_EXITING 0x20000000
54 #define CPU_BASED_PAUSE_EXITING 0x40000000
55 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
56
57 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
58
59 /*
60 * Definitions of Secondary Processor-Based VM-Execution Controls.
61 */
62 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
63 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002
64 #define SECONDARY_EXEC_DESC 0x00000004
65 #define SECONDARY_EXEC_RDTSCP 0x00000008
66 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
67 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
68 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
69 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
70 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
71 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
72 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
73 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
74 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
75 #define SECONDARY_EXEC_ENABLE_PML 0x00020000
76 #define SECONDARY_EXEC_XSAVES 0x00100000
77 #define SECONDARY_EXEC_TSC_SCALING 0x02000000
78
79 #define PIN_BASED_EXT_INTR_MASK 0x00000001
80 #define PIN_BASED_NMI_EXITING 0x00000008
81 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
82 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
83 #define PIN_BASED_POSTED_INTR 0x00000080
84
85 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
86
87 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
88 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
89 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
90 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
91 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
92 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
93 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
94 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
95 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
96 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
97
98 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
99
100 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
101 #define VM_ENTRY_IA32E_MODE 0x00000200
102 #define VM_ENTRY_SMM 0x00000400
103 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
104 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
105 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
106 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
107 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
108
109 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
110
111 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
112 #define VMX_MISC_SAVE_EFER_LMA 0x00000020
113 #define VMX_MISC_ACTIVITY_HLT 0x00000040
114
115 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
116 {
117 return vmx_basic & GENMASK_ULL(30, 0);
118 }
119
120 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
121 {
122 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
123 }
124
125 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
126 {
127 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
128 }
129
130 static inline int vmx_misc_cr3_count(u64 vmx_misc)
131 {
132 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
133 }
134
135 static inline int vmx_misc_max_msr(u64 vmx_misc)
136 {
137 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
138 }
139
140 static inline int vmx_misc_mseg_revid(u64 vmx_misc)
141 {
142 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
143 }
144
145 /* VMCS Encodings */
146 enum vmcs_field {
147 VIRTUAL_PROCESSOR_ID = 0x00000000,
148 POSTED_INTR_NV = 0x00000002,
149 GUEST_ES_SELECTOR = 0x00000800,
150 GUEST_CS_SELECTOR = 0x00000802,
151 GUEST_SS_SELECTOR = 0x00000804,
152 GUEST_DS_SELECTOR = 0x00000806,
153 GUEST_FS_SELECTOR = 0x00000808,
154 GUEST_GS_SELECTOR = 0x0000080a,
155 GUEST_LDTR_SELECTOR = 0x0000080c,
156 GUEST_TR_SELECTOR = 0x0000080e,
157 GUEST_INTR_STATUS = 0x00000810,
158 GUEST_PML_INDEX = 0x00000812,
159 HOST_ES_SELECTOR = 0x00000c00,
160 HOST_CS_SELECTOR = 0x00000c02,
161 HOST_SS_SELECTOR = 0x00000c04,
162 HOST_DS_SELECTOR = 0x00000c06,
163 HOST_FS_SELECTOR = 0x00000c08,
164 HOST_GS_SELECTOR = 0x00000c0a,
165 HOST_TR_SELECTOR = 0x00000c0c,
166 IO_BITMAP_A = 0x00002000,
167 IO_BITMAP_A_HIGH = 0x00002001,
168 IO_BITMAP_B = 0x00002002,
169 IO_BITMAP_B_HIGH = 0x00002003,
170 MSR_BITMAP = 0x00002004,
171 MSR_BITMAP_HIGH = 0x00002005,
172 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
173 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
174 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
175 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
176 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
177 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
178 PML_ADDRESS = 0x0000200e,
179 PML_ADDRESS_HIGH = 0x0000200f,
180 TSC_OFFSET = 0x00002010,
181 TSC_OFFSET_HIGH = 0x00002011,
182 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
183 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
184 APIC_ACCESS_ADDR = 0x00002014,
185 APIC_ACCESS_ADDR_HIGH = 0x00002015,
186 POSTED_INTR_DESC_ADDR = 0x00002016,
187 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
188 EPT_POINTER = 0x0000201a,
189 EPT_POINTER_HIGH = 0x0000201b,
190 EOI_EXIT_BITMAP0 = 0x0000201c,
191 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
192 EOI_EXIT_BITMAP1 = 0x0000201e,
193 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
194 EOI_EXIT_BITMAP2 = 0x00002020,
195 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
196 EOI_EXIT_BITMAP3 = 0x00002022,
197 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
198 VMREAD_BITMAP = 0x00002026,
199 VMWRITE_BITMAP = 0x00002028,
200 XSS_EXIT_BITMAP = 0x0000202C,
201 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
202 TSC_MULTIPLIER = 0x00002032,
203 TSC_MULTIPLIER_HIGH = 0x00002033,
204 GUEST_PHYSICAL_ADDRESS = 0x00002400,
205 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
206 VMCS_LINK_POINTER = 0x00002800,
207 VMCS_LINK_POINTER_HIGH = 0x00002801,
208 GUEST_IA32_DEBUGCTL = 0x00002802,
209 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
210 GUEST_IA32_PAT = 0x00002804,
211 GUEST_IA32_PAT_HIGH = 0x00002805,
212 GUEST_IA32_EFER = 0x00002806,
213 GUEST_IA32_EFER_HIGH = 0x00002807,
214 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
215 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
216 GUEST_PDPTR0 = 0x0000280a,
217 GUEST_PDPTR0_HIGH = 0x0000280b,
218 GUEST_PDPTR1 = 0x0000280c,
219 GUEST_PDPTR1_HIGH = 0x0000280d,
220 GUEST_PDPTR2 = 0x0000280e,
221 GUEST_PDPTR2_HIGH = 0x0000280f,
222 GUEST_PDPTR3 = 0x00002810,
223 GUEST_PDPTR3_HIGH = 0x00002811,
224 GUEST_BNDCFGS = 0x00002812,
225 GUEST_BNDCFGS_HIGH = 0x00002813,
226 HOST_IA32_PAT = 0x00002c00,
227 HOST_IA32_PAT_HIGH = 0x00002c01,
228 HOST_IA32_EFER = 0x00002c02,
229 HOST_IA32_EFER_HIGH = 0x00002c03,
230 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
231 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
232 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
233 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
234 EXCEPTION_BITMAP = 0x00004004,
235 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
236 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
237 CR3_TARGET_COUNT = 0x0000400a,
238 VM_EXIT_CONTROLS = 0x0000400c,
239 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
240 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
241 VM_ENTRY_CONTROLS = 0x00004012,
242 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
243 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
244 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
245 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
246 TPR_THRESHOLD = 0x0000401c,
247 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
248 PLE_GAP = 0x00004020,
249 PLE_WINDOW = 0x00004022,
250 VM_INSTRUCTION_ERROR = 0x00004400,
251 VM_EXIT_REASON = 0x00004402,
252 VM_EXIT_INTR_INFO = 0x00004404,
253 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
254 IDT_VECTORING_INFO_FIELD = 0x00004408,
255 IDT_VECTORING_ERROR_CODE = 0x0000440a,
256 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
257 VMX_INSTRUCTION_INFO = 0x0000440e,
258 GUEST_ES_LIMIT = 0x00004800,
259 GUEST_CS_LIMIT = 0x00004802,
260 GUEST_SS_LIMIT = 0x00004804,
261 GUEST_DS_LIMIT = 0x00004806,
262 GUEST_FS_LIMIT = 0x00004808,
263 GUEST_GS_LIMIT = 0x0000480a,
264 GUEST_LDTR_LIMIT = 0x0000480c,
265 GUEST_TR_LIMIT = 0x0000480e,
266 GUEST_GDTR_LIMIT = 0x00004810,
267 GUEST_IDTR_LIMIT = 0x00004812,
268 GUEST_ES_AR_BYTES = 0x00004814,
269 GUEST_CS_AR_BYTES = 0x00004816,
270 GUEST_SS_AR_BYTES = 0x00004818,
271 GUEST_DS_AR_BYTES = 0x0000481a,
272 GUEST_FS_AR_BYTES = 0x0000481c,
273 GUEST_GS_AR_BYTES = 0x0000481e,
274 GUEST_LDTR_AR_BYTES = 0x00004820,
275 GUEST_TR_AR_BYTES = 0x00004822,
276 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
277 GUEST_ACTIVITY_STATE = 0X00004826,
278 GUEST_SYSENTER_CS = 0x0000482A,
279 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
280 HOST_IA32_SYSENTER_CS = 0x00004c00,
281 CR0_GUEST_HOST_MASK = 0x00006000,
282 CR4_GUEST_HOST_MASK = 0x00006002,
283 CR0_READ_SHADOW = 0x00006004,
284 CR4_READ_SHADOW = 0x00006006,
285 CR3_TARGET_VALUE0 = 0x00006008,
286 CR3_TARGET_VALUE1 = 0x0000600a,
287 CR3_TARGET_VALUE2 = 0x0000600c,
288 CR3_TARGET_VALUE3 = 0x0000600e,
289 EXIT_QUALIFICATION = 0x00006400,
290 GUEST_LINEAR_ADDRESS = 0x0000640a,
291 GUEST_CR0 = 0x00006800,
292 GUEST_CR3 = 0x00006802,
293 GUEST_CR4 = 0x00006804,
294 GUEST_ES_BASE = 0x00006806,
295 GUEST_CS_BASE = 0x00006808,
296 GUEST_SS_BASE = 0x0000680a,
297 GUEST_DS_BASE = 0x0000680c,
298 GUEST_FS_BASE = 0x0000680e,
299 GUEST_GS_BASE = 0x00006810,
300 GUEST_LDTR_BASE = 0x00006812,
301 GUEST_TR_BASE = 0x00006814,
302 GUEST_GDTR_BASE = 0x00006816,
303 GUEST_IDTR_BASE = 0x00006818,
304 GUEST_DR7 = 0x0000681a,
305 GUEST_RSP = 0x0000681c,
306 GUEST_RIP = 0x0000681e,
307 GUEST_RFLAGS = 0x00006820,
308 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
309 GUEST_SYSENTER_ESP = 0x00006824,
310 GUEST_SYSENTER_EIP = 0x00006826,
311 HOST_CR0 = 0x00006c00,
312 HOST_CR3 = 0x00006c02,
313 HOST_CR4 = 0x00006c04,
314 HOST_FS_BASE = 0x00006c06,
315 HOST_GS_BASE = 0x00006c08,
316 HOST_TR_BASE = 0x00006c0a,
317 HOST_GDTR_BASE = 0x00006c0c,
318 HOST_IDTR_BASE = 0x00006c0e,
319 HOST_IA32_SYSENTER_ESP = 0x00006c10,
320 HOST_IA32_SYSENTER_EIP = 0x00006c12,
321 HOST_RSP = 0x00006c14,
322 HOST_RIP = 0x00006c16,
323 };
324
325 /*
326 * Interruption-information format
327 */
328 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
329 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
330 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
331 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
332 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
333 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
334
335 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
336 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
337 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
338 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
339
340 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
341 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
342 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
343 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
344 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
345
346 /* GUEST_INTERRUPTIBILITY_INFO flags. */
347 #define GUEST_INTR_STATE_STI 0x00000001
348 #define GUEST_INTR_STATE_MOV_SS 0x00000002
349 #define GUEST_INTR_STATE_SMI 0x00000004
350 #define GUEST_INTR_STATE_NMI 0x00000008
351
352 /* GUEST_ACTIVITY_STATE flags */
353 #define GUEST_ACTIVITY_ACTIVE 0
354 #define GUEST_ACTIVITY_HLT 1
355 #define GUEST_ACTIVITY_SHUTDOWN 2
356 #define GUEST_ACTIVITY_WAIT_SIPI 3
357
358 /*
359 * Exit Qualifications for MOV for Control Register Access
360 */
361 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
362 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
363 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
364 #define LMSW_SOURCE_DATA_SHIFT 16
365 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
366 #define REG_EAX (0 << 8)
367 #define REG_ECX (1 << 8)
368 #define REG_EDX (2 << 8)
369 #define REG_EBX (3 << 8)
370 #define REG_ESP (4 << 8)
371 #define REG_EBP (5 << 8)
372 #define REG_ESI (6 << 8)
373 #define REG_EDI (7 << 8)
374 #define REG_R8 (8 << 8)
375 #define REG_R9 (9 << 8)
376 #define REG_R10 (10 << 8)
377 #define REG_R11 (11 << 8)
378 #define REG_R12 (12 << 8)
379 #define REG_R13 (13 << 8)
380 #define REG_R14 (14 << 8)
381 #define REG_R15 (15 << 8)
382
383 /*
384 * Exit Qualifications for MOV for Debug Register Access
385 */
386 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
387 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
388 #define TYPE_MOV_TO_DR (0 << 4)
389 #define TYPE_MOV_FROM_DR (1 << 4)
390 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
391
392
393 /*
394 * Exit Qualifications for APIC-Access
395 */
396 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
397 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
398 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
399 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
400 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
401 #define TYPE_LINEAR_APIC_EVENT (3 << 12)
402 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
403 #define TYPE_PHYSICAL_APIC_INST (15 << 12)
404
405 /* segment AR in VMCS -- these are different from what LAR reports */
406 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
407
408 #define VMX_AR_TYPE_ACCESSES_MASK 1
409 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
410 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
411 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
412 #define VMX_AR_TYPE_MASK 0x0f
413 #define VMX_AR_TYPE_BUSY_64_TSS 11
414 #define VMX_AR_TYPE_BUSY_32_TSS 11
415 #define VMX_AR_TYPE_BUSY_16_TSS 3
416 #define VMX_AR_TYPE_LDT 2
417
418 #define VMX_AR_UNUSABLE_MASK (1 << 16)
419 #define VMX_AR_S_MASK (1 << 4)
420 #define VMX_AR_P_MASK (1 << 7)
421 #define VMX_AR_L_MASK (1 << 13)
422 #define VMX_AR_DB_MASK (1 << 14)
423 #define VMX_AR_G_MASK (1 << 15)
424 #define VMX_AR_DPL_SHIFT 5
425 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
426
427 #define VMX_AR_RESERVD_MASK 0xfffe0f00
428
429 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
430 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
431 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
432
433 #define VMX_NR_VPIDS (1 << 16)
434 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
435 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
436 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
437 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
438
439 #define VMX_EPT_EXTENT_CONTEXT 1
440 #define VMX_EPT_EXTENT_GLOBAL 2
441 #define VMX_EPT_EXTENT_SHIFT 24
442
443 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
444 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
445 #define VMX_EPTP_UC_BIT (1ull << 8)
446 #define VMX_EPTP_WB_BIT (1ull << 14)
447 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
448 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
449 #define VMX_EPT_INVEPT_BIT (1ull << 20)
450 #define VMX_EPT_AD_BIT (1ull << 21)
451 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
452 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
453
454 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
455 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
456 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
457 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
458 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
459
460 #define VMX_EPT_DEFAULT_GAW 3
461 #define VMX_EPT_MAX_GAW 0x4
462 #define VMX_EPT_MT_EPTE_SHIFT 3
463 #define VMX_EPT_GAW_EPTP_SHIFT 3
464 #define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
465 #define VMX_EPT_DEFAULT_MT 0x6ull
466 #define VMX_EPT_READABLE_MASK 0x1ull
467 #define VMX_EPT_WRITABLE_MASK 0x2ull
468 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
469 #define VMX_EPT_IPAT_BIT (1ull << 6)
470 #define VMX_EPT_ACCESS_BIT (1ull << 8)
471 #define VMX_EPT_DIRTY_BIT (1ull << 9)
472 #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
473 VMX_EPT_WRITABLE_MASK | \
474 VMX_EPT_EXECUTABLE_MASK)
475 #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
476
477 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
478 #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
479 VMX_EPT_EXECUTABLE_MASK)
480
481 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
482
483
484 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
485 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
486 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
487 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
488 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
489 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
490 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
491 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
492 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
493 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
494 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
495
496 struct vmx_msr_entry {
497 u32 index;
498 u32 reserved;
499 u64 value;
500 } __aligned(16);
501
502 /*
503 * Exit Qualifications for entry failure during or after loading guest state
504 */
505 #define ENTRY_FAIL_DEFAULT 0
506 #define ENTRY_FAIL_PDPTE 2
507 #define ENTRY_FAIL_NMI 3
508 #define ENTRY_FAIL_VMCS_LINK_PTR 4
509
510 /*
511 * Exit Qualifications for EPT Violations
512 */
513 #define EPT_VIOLATION_ACC_READ_BIT 0
514 #define EPT_VIOLATION_ACC_WRITE_BIT 1
515 #define EPT_VIOLATION_ACC_INSTR_BIT 2
516 #define EPT_VIOLATION_READABLE_BIT 3
517 #define EPT_VIOLATION_WRITABLE_BIT 4
518 #define EPT_VIOLATION_EXECUTABLE_BIT 5
519 #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
520 #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
521 #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
522 #define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
523 #define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
524 #define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
525
526 /*
527 * VM-instruction error numbers
528 */
529 enum vm_instruction_error_number {
530 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
531 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
532 VMXERR_VMCLEAR_VMXON_POINTER = 3,
533 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
534 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
535 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
536 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
537 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
538 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
539 VMXERR_VMPTRLD_VMXON_POINTER = 10,
540 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
541 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
542 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
543 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
544 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
545 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
546 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
547 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
548 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
549 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
550 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
551 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
552 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
553 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
554 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
555 };
556
557 #endif
Linux with added FPC-III support