x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / x86 / kvm / mmu.h
blobc92834c55c59ea43b0c34c57398ddb201b7d6281
1 #ifndef __KVM_X86_MMU_H
2 #define __KVM_X86_MMU_H
4 #include <linux/kvm_host.h>
5 #include "kvm_cache_regs.h"
7 #define PT64_PT_BITS 9
8 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9 #define PT32_PT_BITS 10
10 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
12 #define PT_WRITABLE_SHIFT 1
13 #define PT_USER_SHIFT 2
15 #define PT_PRESENT_MASK (1ULL << 0)
16 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
17 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
18 #define PT_PWT_MASK (1ULL << 3)
19 #define PT_PCD_MASK (1ULL << 4)
20 #define PT_ACCESSED_SHIFT 5
21 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
22 #define PT_DIRTY_SHIFT 6
23 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
24 #define PT_PAGE_SIZE_SHIFT 7
25 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
26 #define PT_PAT_MASK (1ULL << 7)
27 #define PT_GLOBAL_MASK (1ULL << 8)
28 #define PT64_NX_SHIFT 63
29 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
31 #define PT_PAT_SHIFT 7
32 #define PT_DIR_PAT_SHIFT 12
33 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
35 #define PT32_DIR_PSE36_SIZE 4
36 #define PT32_DIR_PSE36_SHIFT 13
37 #define PT32_DIR_PSE36_MASK \
38 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
40 #define PT64_ROOT_LEVEL 4
41 #define PT32_ROOT_LEVEL 2
42 #define PT32E_ROOT_LEVEL 3
44 #define PT_PDPE_LEVEL 3
45 #define PT_DIRECTORY_LEVEL 2
46 #define PT_PAGE_TABLE_LEVEL 1
47 #define PT_MAX_HUGEPAGE_LEVEL (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES - 1)
49 static inline u64 rsvd_bits(int s, int e)
51 return ((1ULL << (e - s + 1)) - 1) << s;
54 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
56 void
57 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
60 * Return values of handle_mmio_page_fault:
61 * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
62 * directly.
63 * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
64 * fault path update the mmio spte.
65 * RET_MMIO_PF_RETRY: let CPU fault again on the address.
66 * RET_MMIO_PF_BUG: a bug was detected (and a WARN was printed).
68 enum {
69 RET_MMIO_PF_EMULATE = 1,
70 RET_MMIO_PF_INVALID = 2,
71 RET_MMIO_PF_RETRY = 0,
72 RET_MMIO_PF_BUG = -1
75 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct);
76 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
77 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly);
78 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
80 static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
82 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
83 return kvm->arch.n_max_mmu_pages -
84 kvm->arch.n_used_mmu_pages;
86 return 0;
89 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
91 if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
92 return 0;
94 return kvm_mmu_load(vcpu);
98 * Currently, we have two sorts of write-protection, a) the first one
99 * write-protects guest page to sync the guest modification, b) another one is
100 * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
101 * between these two sorts are:
102 * 1) the first case clears SPTE_MMU_WRITEABLE bit.
103 * 2) the first case requires flushing tlb immediately avoiding corrupting
104 * shadow page table between all vcpus so it should be in the protection of
105 * mmu-lock. And the another case does not need to flush tlb until returning
106 * the dirty bitmap to userspace since it only write-protects the page
107 * logged in the bitmap, that means the page in the dirty bitmap is not
108 * missed, so it can flush tlb out of mmu-lock.
110 * So, there is the problem: the first case can meet the corrupted tlb caused
111 * by another case which write-protects pages but without flush tlb
112 * immediately. In order to making the first case be aware this problem we let
113 * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
114 * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
116 * Anyway, whenever a spte is updated (only permission and status bits are
117 * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
118 * readonly, if that happens, we need to flush tlb. Fortunately,
119 * mmu_spte_update() has already handled it perfectly.
121 * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
122 * - if we want to see if it has writable tlb entry or if the spte can be
123 * writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
124 * case, otherwise
125 * - if we fix page fault on the spte or do write-protection by dirty logging,
126 * check PT_WRITABLE_MASK.
128 * TODO: introduce APIs to split these two cases.
130 static inline int is_writable_pte(unsigned long pte)
132 return pte & PT_WRITABLE_MASK;
135 static inline bool is_write_protection(struct kvm_vcpu *vcpu)
137 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
141 * Check if a given access (described through the I/D, W/R and U/S bits of a
142 * page fault error code pfec) causes a permission fault with the given PTE
143 * access rights (in ACC_* format).
145 * Return zero if the access does not fault; return the page fault error code
146 * if the access faults.
148 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
149 unsigned pte_access, unsigned pte_pkey,
150 unsigned pfec)
152 int cpl = kvm_x86_ops->get_cpl(vcpu);
153 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
156 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
158 * If CPL = 3, SMAP applies to all supervisor-mode data accesses
159 * (these are implicit supervisor accesses) regardless of the value
160 * of EFLAGS.AC.
162 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
163 * the result in X86_EFLAGS_AC. We then insert it in place of
164 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
165 * but it will be one in index if SMAP checks are being overridden.
166 * It is important to keep this branchless.
168 unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
169 int index = (pfec >> 1) +
170 (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
171 bool fault = (mmu->permissions[index] >> pte_access) & 1;
172 u32 errcode = PFERR_PRESENT_MASK;
174 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
175 if (unlikely(mmu->pkru_mask)) {
176 u32 pkru_bits, offset;
179 * PKRU defines 32 bits, there are 16 domains and 2
180 * attribute bits per domain in pkru. pte_pkey is the
181 * index of the protection domain, so pte_pkey * 2 is
182 * is the index of the first bit for the domain.
184 pkru_bits = (kvm_read_pkru(vcpu) >> (pte_pkey * 2)) & 3;
186 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
187 offset = (pfec & ~1) +
188 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
190 pkru_bits &= mmu->pkru_mask >> offset;
191 errcode |= -pkru_bits & PFERR_PK_MASK;
192 fault |= (pkru_bits != 0);
195 return -(u32)fault & errcode;
198 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
199 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
201 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
202 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
203 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
204 struct kvm_memory_slot *slot, u64 gfn);
205 #endif