2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure
__using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn
[PT_MAX_FULL_LEVELS
];
98 pt_element_t ptes
[PT_MAX_FULL_LEVELS
];
99 pt_element_t prefetch_ptes
[PTE_PREFETCH_NUM
];
100 gpa_t pte_gpa
[PT_MAX_FULL_LEVELS
];
101 pt_element_t __user
*ptep_user
[PT_MAX_FULL_LEVELS
];
102 bool pte_writable
[PT_MAX_FULL_LEVELS
];
106 struct x86_exception fault
;
109 static gfn_t
gpte_to_gfn_lvl(pt_element_t gpte
, int lvl
)
111 return (gpte
& PT_LVL_ADDR_MASK(lvl
)) >> PAGE_SHIFT
;
114 static inline void FNAME(protect_clean_gpte
)(unsigned *access
, unsigned gpte
)
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK
)
122 BUILD_BUG_ON(PT_WRITABLE_MASK
!= ACC_WRITE_MASK
);
124 mask
= (unsigned)~ACC_WRITE_MASK
;
125 /* Allow write access to dirty gptes */
126 mask
|= (gpte
>> (PT_GUEST_DIRTY_SHIFT
- PT_WRITABLE_SHIFT
)) &
131 static inline int FNAME(is_present_gpte
)(unsigned long pte
)
133 #if PTTYPE != PTTYPE_EPT
134 return pte
& PT_PRESENT_MASK
;
140 static int FNAME(cmpxchg_gpte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
141 pt_element_t __user
*ptep_user
, unsigned index
,
142 pt_element_t orig_pte
, pt_element_t new_pte
)
149 npages
= get_user_pages_fast((unsigned long)ptep_user
, 1, 1, &page
);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages
!= 1))
154 table
= kmap_atomic(page
);
155 ret
= CMPXCHG(&table
[index
], orig_pte
, new_pte
);
156 kunmap_atomic(table
);
158 kvm_release_page_dirty(page
);
160 return (ret
!= orig_pte
);
163 static bool FNAME(prefetch_invalid_gpte
)(struct kvm_vcpu
*vcpu
,
164 struct kvm_mmu_page
*sp
, u64
*spte
,
167 if (is_rsvd_bits_set(&vcpu
->arch
.mmu
, gpte
, PT_PAGE_TABLE_LEVEL
))
170 if (!FNAME(is_present_gpte
)(gpte
))
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK
&& !(gpte
& PT_GUEST_ACCESSED_MASK
))
180 drop_spte(vcpu
->kvm
, spte
);
185 * For PTTYPE_EPT, a page table can be executable but not readable
186 * on supported processors. Therefore, set_spte does not automatically
187 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
188 * to signify readability since it isn't used in the EPT case
190 static inline unsigned FNAME(gpte_access
)(struct kvm_vcpu
*vcpu
, u64 gpte
)
193 #if PTTYPE == PTTYPE_EPT
194 access
= ((gpte
& VMX_EPT_WRITABLE_MASK
) ? ACC_WRITE_MASK
: 0) |
195 ((gpte
& VMX_EPT_EXECUTABLE_MASK
) ? ACC_EXEC_MASK
: 0) |
196 ((gpte
& VMX_EPT_READABLE_MASK
) ? ACC_USER_MASK
: 0);
198 BUILD_BUG_ON(ACC_EXEC_MASK
!= PT_PRESENT_MASK
);
199 BUILD_BUG_ON(ACC_EXEC_MASK
!= 1);
200 access
= gpte
& (PT_WRITABLE_MASK
| PT_USER_MASK
| PT_PRESENT_MASK
);
201 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
202 access
^= (gpte
>> PT64_NX_SHIFT
);
208 static int FNAME(update_accessed_dirty_bits
)(struct kvm_vcpu
*vcpu
,
210 struct guest_walker
*walker
,
213 unsigned level
, index
;
214 pt_element_t pte
, orig_pte
;
215 pt_element_t __user
*ptep_user
;
219 /* dirty/accessed bits are not supported, so no need to update them */
220 if (!PT_GUEST_DIRTY_MASK
)
223 for (level
= walker
->max_level
; level
>= walker
->level
; --level
) {
224 pte
= orig_pte
= walker
->ptes
[level
- 1];
225 table_gfn
= walker
->table_gfn
[level
- 1];
226 ptep_user
= walker
->ptep_user
[level
- 1];
227 index
= offset_in_page(ptep_user
) / sizeof(pt_element_t
);
228 if (!(pte
& PT_GUEST_ACCESSED_MASK
)) {
229 trace_kvm_mmu_set_accessed_bit(table_gfn
, index
, sizeof(pte
));
230 pte
|= PT_GUEST_ACCESSED_MASK
;
232 if (level
== walker
->level
&& write_fault
&&
233 !(pte
& PT_GUEST_DIRTY_MASK
)) {
234 trace_kvm_mmu_set_dirty_bit(table_gfn
, index
, sizeof(pte
));
235 pte
|= PT_GUEST_DIRTY_MASK
;
241 * If the slot is read-only, simply do not process the accessed
242 * and dirty bits. This is the correct thing to do if the slot
243 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
244 * are only supported if the accessed and dirty bits are already
245 * set in the ROM (so that MMIO writes are never needed).
247 * Note that NPT does not allow this at all and faults, since
248 * it always wants nested page table entries for the guest
249 * page tables to be writable. And EPT works but will simply
250 * overwrite the read-only memory to set the accessed and dirty
253 if (unlikely(!walker
->pte_writable
[level
- 1]))
256 ret
= FNAME(cmpxchg_gpte
)(vcpu
, mmu
, ptep_user
, index
, orig_pte
, pte
);
260 kvm_vcpu_mark_page_dirty(vcpu
, table_gfn
);
261 walker
->ptes
[level
- 1] = pte
;
266 static inline unsigned FNAME(gpte_pkeys
)(struct kvm_vcpu
*vcpu
, u64 gpte
)
270 pte_t pte
= {.pte
= gpte
};
272 pkeys
= pte_flags_pkey(pte_flags(pte
));
278 * Fetch a guest pte for a guest virtual address
280 static int FNAME(walk_addr_generic
)(struct guest_walker
*walker
,
281 struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
282 gva_t addr
, u32 access
)
286 pt_element_t __user
*uninitialized_var(ptep_user
);
288 unsigned index
, pt_access
, pte_access
, accessed_dirty
, pte_pkey
;
291 const int write_fault
= access
& PFERR_WRITE_MASK
;
292 const int user_fault
= access
& PFERR_USER_MASK
;
293 const int fetch_fault
= access
& PFERR_FETCH_MASK
;
298 trace_kvm_mmu_pagetable_walk(addr
, access
);
300 walker
->level
= mmu
->root_level
;
301 pte
= mmu
->get_cr3(vcpu
);
304 if (walker
->level
== PT32E_ROOT_LEVEL
) {
305 pte
= mmu
->get_pdptr(vcpu
, (addr
>> 30) & 3);
306 trace_kvm_mmu_paging_element(pte
, walker
->level
);
307 if (!FNAME(is_present_gpte
)(pte
))
312 walker
->max_level
= walker
->level
;
313 ASSERT(!(is_long_mode(vcpu
) && !is_pae(vcpu
)));
315 accessed_dirty
= PT_GUEST_ACCESSED_MASK
;
316 pt_access
= pte_access
= ACC_ALL
;
321 unsigned long host_addr
;
323 pt_access
&= pte_access
;
326 index
= PT_INDEX(addr
, walker
->level
);
328 table_gfn
= gpte_to_gfn(pte
);
329 offset
= index
* sizeof(pt_element_t
);
330 pte_gpa
= gfn_to_gpa(table_gfn
) + offset
;
331 walker
->table_gfn
[walker
->level
- 1] = table_gfn
;
332 walker
->pte_gpa
[walker
->level
- 1] = pte_gpa
;
334 real_gfn
= mmu
->translate_gpa(vcpu
, gfn_to_gpa(table_gfn
),
335 PFERR_USER_MASK
|PFERR_WRITE_MASK
,
339 * FIXME: This can happen if emulation (for of an INS/OUTS
340 * instruction) triggers a nested page fault. The exit
341 * qualification / exit info field will incorrectly have
342 * "guest page access" as the nested page fault's cause,
343 * instead of "guest page structure access". To fix this,
344 * the x86_exception struct should be augmented with enough
345 * information to fix the exit_qualification or exit_info_1
348 if (unlikely(real_gfn
== UNMAPPED_GVA
))
351 real_gfn
= gpa_to_gfn(real_gfn
);
353 host_addr
= kvm_vcpu_gfn_to_hva_prot(vcpu
, real_gfn
,
354 &walker
->pte_writable
[walker
->level
- 1]);
355 if (unlikely(kvm_is_error_hva(host_addr
)))
358 ptep_user
= (pt_element_t __user
*)((void *)host_addr
+ offset
);
359 if (unlikely(__copy_from_user(&pte
, ptep_user
, sizeof(pte
))))
361 walker
->ptep_user
[walker
->level
- 1] = ptep_user
;
363 trace_kvm_mmu_paging_element(pte
, walker
->level
);
365 if (unlikely(!FNAME(is_present_gpte
)(pte
)))
368 if (unlikely(is_rsvd_bits_set(mmu
, pte
, walker
->level
))) {
369 errcode
= PFERR_RSVD_MASK
| PFERR_PRESENT_MASK
;
373 accessed_dirty
&= pte
;
374 pte_access
= pt_access
& FNAME(gpte_access
)(vcpu
, pte
);
376 walker
->ptes
[walker
->level
- 1] = pte
;
377 } while (!is_last_gpte(mmu
, walker
->level
, pte
));
379 pte_pkey
= FNAME(gpte_pkeys
)(vcpu
, pte
);
380 errcode
= permission_fault(vcpu
, mmu
, pte_access
, pte_pkey
, access
);
381 if (unlikely(errcode
))
384 gfn
= gpte_to_gfn_lvl(pte
, walker
->level
);
385 gfn
+= (addr
& PT_LVL_OFFSET_MASK(walker
->level
)) >> PAGE_SHIFT
;
387 if (PTTYPE
== 32 && walker
->level
== PT_DIRECTORY_LEVEL
&& is_cpuid_PSE36())
388 gfn
+= pse36_gfn_delta(pte
);
390 real_gpa
= mmu
->translate_gpa(vcpu
, gfn_to_gpa(gfn
), access
, &walker
->fault
);
391 if (real_gpa
== UNMAPPED_GVA
)
394 walker
->gfn
= real_gpa
>> PAGE_SHIFT
;
397 FNAME(protect_clean_gpte
)(&pte_access
, pte
);
400 * On a write fault, fold the dirty bit into accessed_dirty.
401 * For modes without A/D bits support accessed_dirty will be
404 accessed_dirty
&= pte
>>
405 (PT_GUEST_DIRTY_SHIFT
- PT_GUEST_ACCESSED_SHIFT
);
407 if (unlikely(!accessed_dirty
)) {
408 ret
= FNAME(update_accessed_dirty_bits
)(vcpu
, mmu
, walker
, write_fault
);
409 if (unlikely(ret
< 0))
415 walker
->pt_access
= pt_access
;
416 walker
->pte_access
= pte_access
;
417 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
418 __func__
, (u64
)pte
, pte_access
, pt_access
);
422 errcode
|= write_fault
| user_fault
;
423 if (fetch_fault
&& (mmu
->nx
||
424 kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
)))
425 errcode
|= PFERR_FETCH_MASK
;
427 walker
->fault
.vector
= PF_VECTOR
;
428 walker
->fault
.error_code_valid
= true;
429 walker
->fault
.error_code
= errcode
;
431 #if PTTYPE == PTTYPE_EPT
433 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
434 * misconfiguration requires to be injected. The detection is
435 * done by is_rsvd_bits_set() above.
437 * We set up the value of exit_qualification to inject:
438 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
439 * [5:3] - Calculated by the page walk of the guest EPT page tables
440 * [7:8] - Derived from [7:8] of real exit_qualification
442 * The other bits are set to 0.
444 if (!(errcode
& PFERR_RSVD_MASK
)) {
445 vcpu
->arch
.exit_qualification
&= 0x187;
446 vcpu
->arch
.exit_qualification
|= ((pt_access
& pte
) & 0x7) << 3;
449 walker
->fault
.address
= addr
;
450 walker
->fault
.nested_page_fault
= mmu
!= vcpu
->arch
.walk_mmu
;
452 trace_kvm_mmu_walker_error(walker
->fault
.error_code
);
456 static int FNAME(walk_addr
)(struct guest_walker
*walker
,
457 struct kvm_vcpu
*vcpu
, gva_t addr
, u32 access
)
459 return FNAME(walk_addr_generic
)(walker
, vcpu
, &vcpu
->arch
.mmu
, addr
,
463 #if PTTYPE != PTTYPE_EPT
464 static int FNAME(walk_addr_nested
)(struct guest_walker
*walker
,
465 struct kvm_vcpu
*vcpu
, gva_t addr
,
468 return FNAME(walk_addr_generic
)(walker
, vcpu
, &vcpu
->arch
.nested_mmu
,
474 FNAME(prefetch_gpte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
475 u64
*spte
, pt_element_t gpte
, bool no_dirty_log
)
481 if (FNAME(prefetch_invalid_gpte
)(vcpu
, sp
, spte
, gpte
))
484 pgprintk("%s: gpte %llx spte %p\n", __func__
, (u64
)gpte
, spte
);
486 gfn
= gpte_to_gfn(gpte
);
487 pte_access
= sp
->role
.access
& FNAME(gpte_access
)(vcpu
, gpte
);
488 FNAME(protect_clean_gpte
)(&pte_access
, gpte
);
489 pfn
= pte_prefetch_gfn_to_pfn(vcpu
, gfn
,
490 no_dirty_log
&& (pte_access
& ACC_WRITE_MASK
));
491 if (is_error_pfn(pfn
))
495 * we call mmu_set_spte() with host_writable = true because
496 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
498 mmu_set_spte(vcpu
, spte
, pte_access
, 0, PT_PAGE_TABLE_LEVEL
, gfn
, pfn
,
504 static void FNAME(update_pte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
505 u64
*spte
, const void *pte
)
507 pt_element_t gpte
= *(const pt_element_t
*)pte
;
509 FNAME(prefetch_gpte
)(vcpu
, sp
, spte
, gpte
, false);
512 static bool FNAME(gpte_changed
)(struct kvm_vcpu
*vcpu
,
513 struct guest_walker
*gw
, int level
)
515 pt_element_t curr_pte
;
516 gpa_t base_gpa
, pte_gpa
= gw
->pte_gpa
[level
- 1];
520 if (level
== PT_PAGE_TABLE_LEVEL
) {
521 mask
= PTE_PREFETCH_NUM
* sizeof(pt_element_t
) - 1;
522 base_gpa
= pte_gpa
& ~mask
;
523 index
= (pte_gpa
- base_gpa
) / sizeof(pt_element_t
);
525 r
= kvm_vcpu_read_guest_atomic(vcpu
, base_gpa
,
526 gw
->prefetch_ptes
, sizeof(gw
->prefetch_ptes
));
527 curr_pte
= gw
->prefetch_ptes
[index
];
529 r
= kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
,
530 &curr_pte
, sizeof(curr_pte
));
532 return r
|| curr_pte
!= gw
->ptes
[level
- 1];
535 static void FNAME(pte_prefetch
)(struct kvm_vcpu
*vcpu
, struct guest_walker
*gw
,
538 struct kvm_mmu_page
*sp
;
539 pt_element_t
*gptep
= gw
->prefetch_ptes
;
543 sp
= page_header(__pa(sptep
));
545 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
549 return __direct_pte_prefetch(vcpu
, sp
, sptep
);
551 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
554 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
558 if (is_shadow_present_pte(*spte
))
561 if (!FNAME(prefetch_gpte
)(vcpu
, sp
, spte
, gptep
[i
], true))
567 * Fetch a shadow pte for a specific level in the paging hierarchy.
568 * If the guest tries to write a write-protected page, we need to
569 * emulate this operation, return 1 to indicate this case.
571 static int FNAME(fetch
)(struct kvm_vcpu
*vcpu
, gva_t addr
,
572 struct guest_walker
*gw
,
573 int write_fault
, int hlevel
,
574 kvm_pfn_t pfn
, bool map_writable
, bool prefault
)
576 struct kvm_mmu_page
*sp
= NULL
;
577 struct kvm_shadow_walk_iterator it
;
578 unsigned direct_access
, access
= gw
->pt_access
;
579 int top_level
, emulate
;
581 direct_access
= gw
->pte_access
;
583 top_level
= vcpu
->arch
.mmu
.root_level
;
584 if (top_level
== PT32E_ROOT_LEVEL
)
585 top_level
= PT32_ROOT_LEVEL
;
587 * Verify that the top-level gpte is still there. Since the page
588 * is a root page, it is either write protected (and cannot be
589 * changed from now on) or it is invalid (in which case, we don't
590 * really care if it changes underneath us after this point).
592 if (FNAME(gpte_changed
)(vcpu
, gw
, top_level
))
593 goto out_gpte_changed
;
595 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
596 goto out_gpte_changed
;
598 for (shadow_walk_init(&it
, vcpu
, addr
);
599 shadow_walk_okay(&it
) && it
.level
> gw
->level
;
600 shadow_walk_next(&it
)) {
603 clear_sp_write_flooding_count(it
.sptep
);
604 drop_large_spte(vcpu
, it
.sptep
);
607 if (!is_shadow_present_pte(*it
.sptep
)) {
608 table_gfn
= gw
->table_gfn
[it
.level
- 2];
609 sp
= kvm_mmu_get_page(vcpu
, table_gfn
, addr
, it
.level
-1,
614 * Verify that the gpte in the page we've just write
615 * protected is still there.
617 if (FNAME(gpte_changed
)(vcpu
, gw
, it
.level
- 1))
618 goto out_gpte_changed
;
621 link_shadow_page(vcpu
, it
.sptep
, sp
);
625 shadow_walk_okay(&it
) && it
.level
> hlevel
;
626 shadow_walk_next(&it
)) {
629 clear_sp_write_flooding_count(it
.sptep
);
630 validate_direct_spte(vcpu
, it
.sptep
, direct_access
);
632 drop_large_spte(vcpu
, it
.sptep
);
634 if (is_shadow_present_pte(*it
.sptep
))
637 direct_gfn
= gw
->gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
639 sp
= kvm_mmu_get_page(vcpu
, direct_gfn
, addr
, it
.level
-1,
640 true, direct_access
);
641 link_shadow_page(vcpu
, it
.sptep
, sp
);
644 clear_sp_write_flooding_count(it
.sptep
);
645 emulate
= mmu_set_spte(vcpu
, it
.sptep
, gw
->pte_access
, write_fault
,
646 it
.level
, gw
->gfn
, pfn
, prefault
, map_writable
);
647 FNAME(pte_prefetch
)(vcpu
, gw
, it
.sptep
);
652 kvm_release_pfn_clean(pfn
);
657 * To see whether the mapped gfn can write its page table in the current
660 * It is the helper function of FNAME(page_fault). When guest uses large page
661 * size to map the writable gfn which is used as current page table, we should
662 * force kvm to use small page size to map it because new shadow page will be
663 * created when kvm establishes shadow page table that stop kvm using large
664 * page size. Do it early can avoid unnecessary #PF and emulation.
666 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
667 * currently used as its page table.
669 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
670 * since the PDPT is always shadowed, that means, we can not use large page
671 * size to map the gfn which is used as PDPT.
674 FNAME(is_self_change_mapping
)(struct kvm_vcpu
*vcpu
,
675 struct guest_walker
*walker
, int user_fault
,
676 bool *write_fault_to_shadow_pgtable
)
679 gfn_t mask
= ~(KVM_PAGES_PER_HPAGE(walker
->level
) - 1);
680 bool self_changed
= false;
682 if (!(walker
->pte_access
& ACC_WRITE_MASK
||
683 (!is_write_protection(vcpu
) && !user_fault
)))
686 for (level
= walker
->level
; level
<= walker
->max_level
; level
++) {
687 gfn_t gfn
= walker
->gfn
^ walker
->table_gfn
[level
- 1];
689 self_changed
|= !(gfn
& mask
);
690 *write_fault_to_shadow_pgtable
|= !gfn
;
697 * Page fault handler. There are several causes for a page fault:
698 * - there is no shadow pte for the guest pte
699 * - write access through a shadow pte marked read only so that we can set
701 * - write access to a shadow pte marked read only so we can update the page
702 * dirty bitmap, when userspace requests it
703 * - mmio access; in this case we will never install a present shadow pte
704 * - normal guest page fault due to the guest pte marked not present, not
705 * writable, or not executable
707 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
708 * a negative value on error.
710 static int FNAME(page_fault
)(struct kvm_vcpu
*vcpu
, gva_t addr
, u32 error_code
,
713 int write_fault
= error_code
& PFERR_WRITE_MASK
;
714 int user_fault
= error_code
& PFERR_USER_MASK
;
715 struct guest_walker walker
;
718 int level
= PT_PAGE_TABLE_LEVEL
;
719 bool force_pt_level
= false;
720 unsigned long mmu_seq
;
721 bool map_writable
, is_self_change_mapping
;
723 pgprintk("%s: addr %lx err %x\n", __func__
, addr
, error_code
);
725 r
= mmu_topup_memory_caches(vcpu
);
730 * If PFEC.RSVD is set, this is a shadow page fault.
731 * The bit needs to be cleared before walking guest page tables.
733 error_code
&= ~PFERR_RSVD_MASK
;
736 * Look up the guest pte for the faulting address.
738 r
= FNAME(walk_addr
)(&walker
, vcpu
, addr
, error_code
);
741 * The page is not mapped by the guest. Let the guest handle it.
744 pgprintk("%s: guest page fault\n", __func__
);
746 inject_page_fault(vcpu
, &walker
.fault
);
751 if (page_fault_handle_page_track(vcpu
, error_code
, walker
.gfn
)) {
752 shadow_page_table_clear_flood(vcpu
, addr
);
756 vcpu
->arch
.write_fault_to_shadow_pgtable
= false;
758 is_self_change_mapping
= FNAME(is_self_change_mapping
)(vcpu
,
759 &walker
, user_fault
, &vcpu
->arch
.write_fault_to_shadow_pgtable
);
761 if (walker
.level
>= PT_DIRECTORY_LEVEL
&& !is_self_change_mapping
) {
762 level
= mapping_level(vcpu
, walker
.gfn
, &force_pt_level
);
763 if (likely(!force_pt_level
)) {
764 level
= min(walker
.level
, level
);
765 walker
.gfn
= walker
.gfn
& ~(KVM_PAGES_PER_HPAGE(level
) - 1);
768 force_pt_level
= true;
770 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
773 if (try_async_pf(vcpu
, prefault
, walker
.gfn
, addr
, &pfn
, write_fault
,
777 if (handle_abnormal_pfn(vcpu
, mmu_is_nested(vcpu
) ? 0 : addr
,
778 walker
.gfn
, pfn
, walker
.pte_access
, &r
))
782 * Do not change pte_access if the pfn is a mmio page, otherwise
783 * we will cache the incorrect access into mmio spte.
785 if (write_fault
&& !(walker
.pte_access
& ACC_WRITE_MASK
) &&
786 !is_write_protection(vcpu
) && !user_fault
&&
787 !is_noslot_pfn(pfn
)) {
788 walker
.pte_access
|= ACC_WRITE_MASK
;
789 walker
.pte_access
&= ~ACC_USER_MASK
;
792 * If we converted a user page to a kernel page,
793 * so that the kernel can write to it when cr0.wp=0,
794 * then we should prevent the kernel from executing it
795 * if SMEP is enabled.
797 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
798 walker
.pte_access
&= ~ACC_EXEC_MASK
;
801 spin_lock(&vcpu
->kvm
->mmu_lock
);
802 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
805 kvm_mmu_audit(vcpu
, AUDIT_PRE_PAGE_FAULT
);
806 make_mmu_pages_available(vcpu
);
808 transparent_hugepage_adjust(vcpu
, &walker
.gfn
, &pfn
, &level
);
809 r
= FNAME(fetch
)(vcpu
, addr
, &walker
, write_fault
,
810 level
, pfn
, map_writable
, prefault
);
811 ++vcpu
->stat
.pf_fixed
;
812 kvm_mmu_audit(vcpu
, AUDIT_POST_PAGE_FAULT
);
813 spin_unlock(&vcpu
->kvm
->mmu_lock
);
818 spin_unlock(&vcpu
->kvm
->mmu_lock
);
819 kvm_release_pfn_clean(pfn
);
823 static gpa_t
FNAME(get_level1_sp_gpa
)(struct kvm_mmu_page
*sp
)
827 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
830 offset
= sp
->role
.quadrant
<< PT64_LEVEL_BITS
;
832 return gfn_to_gpa(sp
->gfn
) + offset
* sizeof(pt_element_t
);
835 static void FNAME(invlpg
)(struct kvm_vcpu
*vcpu
, gva_t gva
)
837 struct kvm_shadow_walk_iterator iterator
;
838 struct kvm_mmu_page
*sp
;
842 vcpu_clear_mmio_info(vcpu
, gva
);
845 * No need to check return value here, rmap_can_add() can
846 * help us to skip pte prefetch later.
848 mmu_topup_memory_caches(vcpu
);
850 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
)) {
855 spin_lock(&vcpu
->kvm
->mmu_lock
);
856 for_each_shadow_entry(vcpu
, gva
, iterator
) {
857 level
= iterator
.level
;
858 sptep
= iterator
.sptep
;
860 sp
= page_header(__pa(sptep
));
861 if (is_last_spte(*sptep
, level
)) {
868 pte_gpa
= FNAME(get_level1_sp_gpa
)(sp
);
869 pte_gpa
+= (sptep
- sp
->spt
) * sizeof(pt_element_t
);
871 if (mmu_page_zap_pte(vcpu
->kvm
, sp
, sptep
))
872 kvm_flush_remote_tlbs(vcpu
->kvm
);
874 if (!rmap_can_add(vcpu
))
877 if (kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
, &gpte
,
878 sizeof(pt_element_t
)))
881 FNAME(update_pte
)(vcpu
, sp
, sptep
, &gpte
);
884 if (!is_shadow_present_pte(*sptep
) || !sp
->unsync_children
)
887 spin_unlock(&vcpu
->kvm
->mmu_lock
);
890 static gpa_t
FNAME(gva_to_gpa
)(struct kvm_vcpu
*vcpu
, gva_t vaddr
, u32 access
,
891 struct x86_exception
*exception
)
893 struct guest_walker walker
;
894 gpa_t gpa
= UNMAPPED_GVA
;
897 r
= FNAME(walk_addr
)(&walker
, vcpu
, vaddr
, access
);
900 gpa
= gfn_to_gpa(walker
.gfn
);
901 gpa
|= vaddr
& ~PAGE_MASK
;
902 } else if (exception
)
903 *exception
= walker
.fault
;
908 #if PTTYPE != PTTYPE_EPT
909 static gpa_t
FNAME(gva_to_gpa_nested
)(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
911 struct x86_exception
*exception
)
913 struct guest_walker walker
;
914 gpa_t gpa
= UNMAPPED_GVA
;
917 r
= FNAME(walk_addr_nested
)(&walker
, vcpu
, vaddr
, access
);
920 gpa
= gfn_to_gpa(walker
.gfn
);
921 gpa
|= vaddr
& ~PAGE_MASK
;
922 } else if (exception
)
923 *exception
= walker
.fault
;
930 * Using the cached information from sp->gfns is safe because:
931 * - The spte has a reference to the struct page, so the pfn for a given gfn
932 * can't change unless all sptes pointing to it are nuked first.
935 * We should flush all tlbs if spte is dropped even though guest is
936 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
937 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
938 * used by guest then tlbs are not flushed, so guest is allowed to access the
940 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
942 static int FNAME(sync_page
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
944 int i
, nr_present
= 0;
948 /* direct kvm_mmu_page can not be unsync. */
949 BUG_ON(sp
->role
.direct
);
951 first_pte_gpa
= FNAME(get_level1_sp_gpa
)(sp
);
953 for (i
= 0; i
< PT64_ENT_PER_PAGE
; i
++) {
962 pte_gpa
= first_pte_gpa
+ i
* sizeof(pt_element_t
);
964 if (kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
, &gpte
,
965 sizeof(pt_element_t
)))
968 if (FNAME(prefetch_invalid_gpte
)(vcpu
, sp
, &sp
->spt
[i
], gpte
)) {
970 * Update spte before increasing tlbs_dirty to make
971 * sure no tlb flush is lost after spte is zapped; see
972 * the comments in kvm_flush_remote_tlbs().
975 vcpu
->kvm
->tlbs_dirty
++;
979 gfn
= gpte_to_gfn(gpte
);
980 pte_access
= sp
->role
.access
;
981 pte_access
&= FNAME(gpte_access
)(vcpu
, gpte
);
982 FNAME(protect_clean_gpte
)(&pte_access
, gpte
);
984 if (sync_mmio_spte(vcpu
, &sp
->spt
[i
], gfn
, pte_access
,
988 if (gfn
!= sp
->gfns
[i
]) {
989 drop_spte(vcpu
->kvm
, &sp
->spt
[i
]);
991 * The same as above where we are doing
992 * prefetch_invalid_gpte().
995 vcpu
->kvm
->tlbs_dirty
++;
1001 host_writable
= sp
->spt
[i
] & SPTE_HOST_WRITEABLE
;
1003 set_spte(vcpu
, &sp
->spt
[i
], pte_access
,
1004 PT_PAGE_TABLE_LEVEL
, gfn
,
1005 spte_to_pfn(sp
->spt
[i
]), true, false,
1015 #undef PT_BASE_ADDR_MASK
1017 #undef PT_LVL_ADDR_MASK
1018 #undef PT_LVL_OFFSET_MASK
1019 #undef PT_LEVEL_BITS
1020 #undef PT_MAX_FULL_LEVELS
1022 #undef gpte_to_gfn_lvl
1024 #undef PT_GUEST_ACCESSED_MASK
1025 #undef PT_GUEST_DIRTY_MASK
1026 #undef PT_GUEST_DIRTY_SHIFT
1027 #undef PT_GUEST_ACCESSED_SHIFT