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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob4e957185d5b3f72cb65068c062a73f71937a2765
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define CREATE_TRACE_POINTS
72 #include "trace.h"
73
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
82 /* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86 #ifdef CONFIG_X86_64
87 static
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 #else
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
91 #endif
92
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109
110 unsigned int min_timer_period_us = 500;
111 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
113 static bool __read_mostly kvmclock_periodic_sync = true;
114 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
116 bool __read_mostly kvm_has_tsc_control;
117 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
118 u32 __read_mostly kvm_max_guest_tsc_khz;
119 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
120 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122 u64 __read_mostly kvm_max_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
124 u64 __read_mostly kvm_default_tsc_scaling_ratio;
125 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
126
127 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
128 static u32 __read_mostly tsc_tolerance_ppm = 250;
129 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
131 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
132 unsigned int __read_mostly lapic_timer_advance_ns = 0;
133 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
135 static bool __read_mostly vector_hashing = true;
136 module_param(vector_hashing, bool, S_IRUGO);
137
138 static bool __read_mostly backwards_tsc_observed = false;
139
140 #define KVM_NR_SHARED_MSRS 16
141
142 struct kvm_shared_msrs_global {
143 int nr;
144 u32 msrs[KVM_NR_SHARED_MSRS];
145 };
146
147 struct kvm_shared_msrs {
148 struct user_return_notifier urn;
149 bool registered;
150 struct kvm_shared_msr_values {
151 u64 host;
152 u64 curr;
153 } values[KVM_NR_SHARED_MSRS];
154 };
155
156 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
157 static struct kvm_shared_msrs __percpu *shared_msrs;
158
159 struct kvm_stats_debugfs_item debugfs_entries[] = {
160 { "pf_fixed", VCPU_STAT(pf_fixed) },
161 { "pf_guest", VCPU_STAT(pf_guest) },
162 { "tlb_flush", VCPU_STAT(tlb_flush) },
163 { "invlpg", VCPU_STAT(invlpg) },
164 { "exits", VCPU_STAT(exits) },
165 { "io_exits", VCPU_STAT(io_exits) },
166 { "mmio_exits", VCPU_STAT(mmio_exits) },
167 { "signal_exits", VCPU_STAT(signal_exits) },
168 { "irq_window", VCPU_STAT(irq_window_exits) },
169 { "nmi_window", VCPU_STAT(nmi_window_exits) },
170 { "halt_exits", VCPU_STAT(halt_exits) },
171 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
172 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
173 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
174 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
175 { "hypercalls", VCPU_STAT(hypercalls) },
176 { "request_irq", VCPU_STAT(request_irq_exits) },
177 { "irq_exits", VCPU_STAT(irq_exits) },
178 { "host_state_reload", VCPU_STAT(host_state_reload) },
179 { "efer_reload", VCPU_STAT(efer_reload) },
180 { "fpu_reload", VCPU_STAT(fpu_reload) },
181 { "insn_emulation", VCPU_STAT(insn_emulation) },
182 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
183 { "irq_injections", VCPU_STAT(irq_injections) },
184 { "nmi_injections", VCPU_STAT(nmi_injections) },
185 { "req_event", VCPU_STAT(req_event) },
186 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
187 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
188 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
189 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
190 { "mmu_flooded", VM_STAT(mmu_flooded) },
191 { "mmu_recycled", VM_STAT(mmu_recycled) },
192 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
193 { "mmu_unsync", VM_STAT(mmu_unsync) },
194 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
195 { "largepages", VM_STAT(lpages) },
196 { "max_mmu_page_hash_collisions",
197 VM_STAT(max_mmu_page_hash_collisions) },
198 { NULL }
199 };
200
201 u64 __read_mostly host_xcr0;
202
203 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
204
205 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
206 {
207 int i;
208 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
209 vcpu->arch.apf.gfns[i] = ~0;
210 }
211
212 static void kvm_on_user_return(struct user_return_notifier *urn)
213 {
214 unsigned slot;
215 struct kvm_shared_msrs *locals
216 = container_of(urn, struct kvm_shared_msrs, urn);
217 struct kvm_shared_msr_values *values;
218 unsigned long flags;
219
220 /*
221 * Disabling irqs at this point since the following code could be
222 * interrupted and executed through kvm_arch_hardware_disable()
223 */
224 local_irq_save(flags);
225 if (locals->registered) {
226 locals->registered = false;
227 user_return_notifier_unregister(urn);
228 }
229 local_irq_restore(flags);
230 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
231 values = &locals->values[slot];
232 if (values->host != values->curr) {
233 wrmsrl(shared_msrs_global.msrs[slot], values->host);
234 values->curr = values->host;
235 }
236 }
237 }
238
239 static void shared_msr_update(unsigned slot, u32 msr)
240 {
241 u64 value;
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244
245 /* only read, and nobody should modify it at this time,
246 * so don't need lock */
247 if (slot >= shared_msrs_global.nr) {
248 printk(KERN_ERR "kvm: invalid MSR slot!");
249 return;
250 }
251 rdmsrl_safe(msr, &value);
252 smsr->values[slot].host = value;
253 smsr->values[slot].curr = value;
254 }
255
256 void kvm_define_shared_msr(unsigned slot, u32 msr)
257 {
258 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
259 shared_msrs_global.msrs[slot] = msr;
260 if (slot >= shared_msrs_global.nr)
261 shared_msrs_global.nr = slot + 1;
262 }
263 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
264
265 static void kvm_shared_msr_cpu_online(void)
266 {
267 unsigned i;
268
269 for (i = 0; i < shared_msrs_global.nr; ++i)
270 shared_msr_update(i, shared_msrs_global.msrs[i]);
271 }
272
273 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
274 {
275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
277 int err;
278
279 if (((value ^ smsr->values[slot].curr) & mask) == 0)
280 return 0;
281 smsr->values[slot].curr = value;
282 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
283 if (err)
284 return 1;
285
286 if (!smsr->registered) {
287 smsr->urn.on_user_return = kvm_on_user_return;
288 user_return_notifier_register(&smsr->urn);
289 smsr->registered = true;
290 }
291 return 0;
292 }
293 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
294
295 static void drop_user_return_notifiers(void)
296 {
297 unsigned int cpu = smp_processor_id();
298 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
299
300 if (smsr->registered)
301 kvm_on_user_return(&smsr->urn);
302 }
303
304 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
305 {
306 return vcpu->arch.apic_base;
307 }
308 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
309
310 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
311 {
312 u64 old_state = vcpu->arch.apic_base &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
314 u64 new_state = msr_info->data &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
317 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
318
319 if (!msr_info->host_initiated &&
320 ((msr_info->data & reserved_bits) != 0 ||
321 new_state == X2APIC_ENABLE ||
322 (new_state == MSR_IA32_APICBASE_ENABLE &&
323 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
324 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
325 old_state == 0)))
326 return 1;
327
328 kvm_lapic_set_base(vcpu, msr_info->data);
329 return 0;
330 }
331 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
332
333 asmlinkage __visible void kvm_spurious_fault(void)
334 {
335 /* Fault while not rebooting. We want the trace. */
336 BUG();
337 }
338 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
339
340 #define EXCPT_BENIGN 0
341 #define EXCPT_CONTRIBUTORY 1
342 #define EXCPT_PF 2
343
344 static int exception_class(int vector)
345 {
346 switch (vector) {
347 case PF_VECTOR:
348 return EXCPT_PF;
349 case DE_VECTOR:
350 case TS_VECTOR:
351 case NP_VECTOR:
352 case SS_VECTOR:
353 case GP_VECTOR:
354 return EXCPT_CONTRIBUTORY;
355 default:
356 break;
357 }
358 return EXCPT_BENIGN;
359 }
360
361 #define EXCPT_FAULT 0
362 #define EXCPT_TRAP 1
363 #define EXCPT_ABORT 2
364 #define EXCPT_INTERRUPT 3
365
366 static int exception_type(int vector)
367 {
368 unsigned int mask;
369
370 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
371 return EXCPT_INTERRUPT;
372
373 mask = 1 << vector;
374
375 /* #DB is trap, as instruction watchpoints are handled elsewhere */
376 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
377 return EXCPT_TRAP;
378
379 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
380 return EXCPT_ABORT;
381
382 /* Reserved exceptions will result in fault */
383 return EXCPT_FAULT;
384 }
385
386 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
387 unsigned nr, bool has_error, u32 error_code,
388 bool reinject)
389 {
390 u32 prev_nr;
391 int class1, class2;
392
393 kvm_make_request(KVM_REQ_EVENT, vcpu);
394
395 if (!vcpu->arch.exception.pending) {
396 queue:
397 if (has_error && !is_protmode(vcpu))
398 has_error = false;
399 vcpu->arch.exception.pending = true;
400 vcpu->arch.exception.has_error_code = has_error;
401 vcpu->arch.exception.nr = nr;
402 vcpu->arch.exception.error_code = error_code;
403 vcpu->arch.exception.reinject = reinject;
404 return;
405 }
406
407 /* to check exception */
408 prev_nr = vcpu->arch.exception.nr;
409 if (prev_nr == DF_VECTOR) {
410 /* triple fault -> shutdown */
411 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
412 return;
413 }
414 class1 = exception_class(prev_nr);
415 class2 = exception_class(nr);
416 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
417 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
418 /* generate double fault per SDM Table 5-5 */
419 vcpu->arch.exception.pending = true;
420 vcpu->arch.exception.has_error_code = true;
421 vcpu->arch.exception.nr = DF_VECTOR;
422 vcpu->arch.exception.error_code = 0;
423 } else
424 /* replace previous exception with a new one in a hope
425 that instruction re-execution will regenerate lost
426 exception */
427 goto queue;
428 }
429
430 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
431 {
432 kvm_multiple_exception(vcpu, nr, false, 0, false);
433 }
434 EXPORT_SYMBOL_GPL(kvm_queue_exception);
435
436 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
437 {
438 kvm_multiple_exception(vcpu, nr, false, 0, true);
439 }
440 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
441
442 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
443 {
444 if (err)
445 kvm_inject_gp(vcpu, 0);
446 else
447 return kvm_skip_emulated_instruction(vcpu);
448
449 return 1;
450 }
451 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
452
453 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
454 {
455 ++vcpu->stat.pf_guest;
456 vcpu->arch.cr2 = fault->address;
457 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
458 }
459 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
460
461 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
462 {
463 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
464 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
465 else
466 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
467
468 return fault->nested_page_fault;
469 }
470
471 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
472 {
473 atomic_inc(&vcpu->arch.nmi_queued);
474 kvm_make_request(KVM_REQ_NMI, vcpu);
475 }
476 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
477
478 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
479 {
480 kvm_multiple_exception(vcpu, nr, true, error_code, false);
481 }
482 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
483
484 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
485 {
486 kvm_multiple_exception(vcpu, nr, true, error_code, true);
487 }
488 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
489
490 /*
491 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
492 * a #GP and return false.
493 */
494 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
495 {
496 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
497 return true;
498 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
499 return false;
500 }
501 EXPORT_SYMBOL_GPL(kvm_require_cpl);
502
503 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
504 {
505 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
506 return true;
507
508 kvm_queue_exception(vcpu, UD_VECTOR);
509 return false;
510 }
511 EXPORT_SYMBOL_GPL(kvm_require_dr);
512
513 /*
514 * This function will be used to read from the physical memory of the currently
515 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
516 * can read from guest physical or from the guest's guest physical memory.
517 */
518 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
519 gfn_t ngfn, void *data, int offset, int len,
520 u32 access)
521 {
522 struct x86_exception exception;
523 gfn_t real_gfn;
524 gpa_t ngpa;
525
526 ngpa = gfn_to_gpa(ngfn);
527 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
528 if (real_gfn == UNMAPPED_GVA)
529 return -EFAULT;
530
531 real_gfn = gpa_to_gfn(real_gfn);
532
533 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
534 }
535 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
536
537 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
538 void *data, int offset, int len, u32 access)
539 {
540 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
541 data, offset, len, access);
542 }
543
544 /*
545 * Load the pae pdptrs. Return true is they are all valid.
546 */
547 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
548 {
549 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
550 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
551 int i;
552 int ret;
553 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
554
555 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
556 offset * sizeof(u64), sizeof(pdpte),
557 PFERR_USER_MASK|PFERR_WRITE_MASK);
558 if (ret < 0) {
559 ret = 0;
560 goto out;
561 }
562 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
563 if ((pdpte[i] & PT_PRESENT_MASK) &&
564 (pdpte[i] &
565 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
566 ret = 0;
567 goto out;
568 }
569 }
570 ret = 1;
571
572 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
573 __set_bit(VCPU_EXREG_PDPTR,
574 (unsigned long *)&vcpu->arch.regs_avail);
575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_dirty);
577 out:
578
579 return ret;
580 }
581 EXPORT_SYMBOL_GPL(load_pdptrs);
582
583 bool pdptrs_changed(struct kvm_vcpu *vcpu)
584 {
585 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
586 bool changed = true;
587 int offset;
588 gfn_t gfn;
589 int r;
590
591 if (is_long_mode(vcpu) || !is_pae(vcpu))
592 return false;
593
594 if (!test_bit(VCPU_EXREG_PDPTR,
595 (unsigned long *)&vcpu->arch.regs_avail))
596 return true;
597
598 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
599 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
600 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
601 PFERR_USER_MASK | PFERR_WRITE_MASK);
602 if (r < 0)
603 goto out;
604 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
605 out:
606
607 return changed;
608 }
609 EXPORT_SYMBOL_GPL(pdptrs_changed);
610
611 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
612 {
613 unsigned long old_cr0 = kvm_read_cr0(vcpu);
614 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
615
616 cr0 |= X86_CR0_ET;
617
618 #ifdef CONFIG_X86_64
619 if (cr0 & 0xffffffff00000000UL)
620 return 1;
621 #endif
622
623 cr0 &= ~CR0_RESERVED_BITS;
624
625 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
626 return 1;
627
628 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
629 return 1;
630
631 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
632 #ifdef CONFIG_X86_64
633 if ((vcpu->arch.efer & EFER_LME)) {
634 int cs_db, cs_l;
635
636 if (!is_pae(vcpu))
637 return 1;
638 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
639 if (cs_l)
640 return 1;
641 } else
642 #endif
643 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
644 kvm_read_cr3(vcpu)))
645 return 1;
646 }
647
648 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
649 return 1;
650
651 kvm_x86_ops->set_cr0(vcpu, cr0);
652
653 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
654 kvm_clear_async_pf_completion_queue(vcpu);
655 kvm_async_pf_hash_reset(vcpu);
656 }
657
658 if ((cr0 ^ old_cr0) & update_bits)
659 kvm_mmu_reset_context(vcpu);
660
661 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
662 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
663 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
664 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
665
666 return 0;
667 }
668 EXPORT_SYMBOL_GPL(kvm_set_cr0);
669
670 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
671 {
672 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
673 }
674 EXPORT_SYMBOL_GPL(kvm_lmsw);
675
676 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
677 {
678 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
679 !vcpu->guest_xcr0_loaded) {
680 /* kvm_set_xcr() also depends on this */
681 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
682 vcpu->guest_xcr0_loaded = 1;
683 }
684 }
685
686 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
687 {
688 if (vcpu->guest_xcr0_loaded) {
689 if (vcpu->arch.xcr0 != host_xcr0)
690 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
691 vcpu->guest_xcr0_loaded = 0;
692 }
693 }
694
695 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
696 {
697 u64 xcr0 = xcr;
698 u64 old_xcr0 = vcpu->arch.xcr0;
699 u64 valid_bits;
700
701 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
702 if (index != XCR_XFEATURE_ENABLED_MASK)
703 return 1;
704 if (!(xcr0 & XFEATURE_MASK_FP))
705 return 1;
706 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
707 return 1;
708
709 /*
710 * Do not allow the guest to set bits that we do not support
711 * saving. However, xcr0 bit 0 is always set, even if the
712 * emulated CPU does not support XSAVE (see fx_init).
713 */
714 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
715 if (xcr0 & ~valid_bits)
716 return 1;
717
718 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
719 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
720 return 1;
721
722 if (xcr0 & XFEATURE_MASK_AVX512) {
723 if (!(xcr0 & XFEATURE_MASK_YMM))
724 return 1;
725 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
726 return 1;
727 }
728 vcpu->arch.xcr0 = xcr0;
729
730 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
731 kvm_update_cpuid(vcpu);
732 return 0;
733 }
734
735 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
736 {
737 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
738 __kvm_set_xcr(vcpu, index, xcr)) {
739 kvm_inject_gp(vcpu, 0);
740 return 1;
741 }
742 return 0;
743 }
744 EXPORT_SYMBOL_GPL(kvm_set_xcr);
745
746 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
747 {
748 unsigned long old_cr4 = kvm_read_cr4(vcpu);
749 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
750 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
751
752 if (cr4 & CR4_RESERVED_BITS)
753 return 1;
754
755 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
756 return 1;
757
758 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
759 return 1;
760
761 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
762 return 1;
763
764 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
765 return 1;
766
767 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
768 return 1;
769
770 if (is_long_mode(vcpu)) {
771 if (!(cr4 & X86_CR4_PAE))
772 return 1;
773 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
774 && ((cr4 ^ old_cr4) & pdptr_bits)
775 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
776 kvm_read_cr3(vcpu)))
777 return 1;
778
779 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
780 if (!guest_cpuid_has_pcid(vcpu))
781 return 1;
782
783 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
784 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
785 return 1;
786 }
787
788 if (kvm_x86_ops->set_cr4(vcpu, cr4))
789 return 1;
790
791 if (((cr4 ^ old_cr4) & pdptr_bits) ||
792 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
793 kvm_mmu_reset_context(vcpu);
794
795 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
796 kvm_update_cpuid(vcpu);
797
798 return 0;
799 }
800 EXPORT_SYMBOL_GPL(kvm_set_cr4);
801
802 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
803 {
804 #ifdef CONFIG_X86_64
805 cr3 &= ~CR3_PCID_INVD;
806 #endif
807
808 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
809 kvm_mmu_sync_roots(vcpu);
810 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
811 return 0;
812 }
813
814 if (is_long_mode(vcpu)) {
815 if (cr3 & CR3_L_MODE_RESERVED_BITS)
816 return 1;
817 } else if (is_pae(vcpu) && is_paging(vcpu) &&
818 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
819 return 1;
820
821 vcpu->arch.cr3 = cr3;
822 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
823 kvm_mmu_new_cr3(vcpu);
824 return 0;
825 }
826 EXPORT_SYMBOL_GPL(kvm_set_cr3);
827
828 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
829 {
830 if (cr8 & CR8_RESERVED_BITS)
831 return 1;
832 if (lapic_in_kernel(vcpu))
833 kvm_lapic_set_tpr(vcpu, cr8);
834 else
835 vcpu->arch.cr8 = cr8;
836 return 0;
837 }
838 EXPORT_SYMBOL_GPL(kvm_set_cr8);
839
840 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
841 {
842 if (lapic_in_kernel(vcpu))
843 return kvm_lapic_get_cr8(vcpu);
844 else
845 return vcpu->arch.cr8;
846 }
847 EXPORT_SYMBOL_GPL(kvm_get_cr8);
848
849 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
850 {
851 int i;
852
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
854 for (i = 0; i < KVM_NR_DB_REGS; i++)
855 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
856 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
857 }
858 }
859
860 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
861 {
862 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
863 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
864 }
865
866 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
867 {
868 unsigned long dr7;
869
870 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
871 dr7 = vcpu->arch.guest_debug_dr7;
872 else
873 dr7 = vcpu->arch.dr7;
874 kvm_x86_ops->set_dr7(vcpu, dr7);
875 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
876 if (dr7 & DR7_BP_EN_MASK)
877 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
878 }
879
880 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
881 {
882 u64 fixed = DR6_FIXED_1;
883
884 if (!guest_cpuid_has_rtm(vcpu))
885 fixed |= DR6_RTM;
886 return fixed;
887 }
888
889 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
890 {
891 switch (dr) {
892 case 0 ... 3:
893 vcpu->arch.db[dr] = val;
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
895 vcpu->arch.eff_db[dr] = val;
896 break;
897 case 4:
898 /* fall through */
899 case 6:
900 if (val & 0xffffffff00000000ULL)
901 return -1; /* #GP */
902 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
903 kvm_update_dr6(vcpu);
904 break;
905 case 5:
906 /* fall through */
907 default: /* 7 */
908 if (val & 0xffffffff00000000ULL)
909 return -1; /* #GP */
910 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
911 kvm_update_dr7(vcpu);
912 break;
913 }
914
915 return 0;
916 }
917
918 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
919 {
920 if (__kvm_set_dr(vcpu, dr, val)) {
921 kvm_inject_gp(vcpu, 0);
922 return 1;
923 }
924 return 0;
925 }
926 EXPORT_SYMBOL_GPL(kvm_set_dr);
927
928 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
929 {
930 switch (dr) {
931 case 0 ... 3:
932 *val = vcpu->arch.db[dr];
933 break;
934 case 4:
935 /* fall through */
936 case 6:
937 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
938 *val = vcpu->arch.dr6;
939 else
940 *val = kvm_x86_ops->get_dr6(vcpu);
941 break;
942 case 5:
943 /* fall through */
944 default: /* 7 */
945 *val = vcpu->arch.dr7;
946 break;
947 }
948 return 0;
949 }
950 EXPORT_SYMBOL_GPL(kvm_get_dr);
951
952 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
953 {
954 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
955 u64 data;
956 int err;
957
958 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
959 if (err)
960 return err;
961 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
962 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
963 return err;
964 }
965 EXPORT_SYMBOL_GPL(kvm_rdpmc);
966
967 /*
968 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
969 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
970 *
971 * This list is modified at module load time to reflect the
972 * capabilities of the host cpu. This capabilities test skips MSRs that are
973 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
974 * may depend on host virtualization features rather than host cpu features.
975 */
976
977 static u32 msrs_to_save[] = {
978 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
979 MSR_STAR,
980 #ifdef CONFIG_X86_64
981 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
982 #endif
983 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
984 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
985 };
986
987 static unsigned num_msrs_to_save;
988
989 static u32 emulated_msrs[] = {
990 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
991 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
992 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
993 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
994 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
995 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
996 HV_X64_MSR_RESET,
997 HV_X64_MSR_VP_INDEX,
998 HV_X64_MSR_VP_RUNTIME,
999 HV_X64_MSR_SCONTROL,
1000 HV_X64_MSR_STIMER0_CONFIG,
1001 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1002 MSR_KVM_PV_EOI_EN,
1003
1004 MSR_IA32_TSC_ADJUST,
1005 MSR_IA32_TSCDEADLINE,
1006 MSR_IA32_MISC_ENABLE,
1007 MSR_IA32_MCG_STATUS,
1008 MSR_IA32_MCG_CTL,
1009 MSR_IA32_MCG_EXT_CTL,
1010 MSR_IA32_SMBASE,
1011 };
1012
1013 static unsigned num_emulated_msrs;
1014
1015 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1016 {
1017 if (efer & efer_reserved_bits)
1018 return false;
1019
1020 if (efer & EFER_FFXSR) {
1021 struct kvm_cpuid_entry2 *feat;
1022
1023 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1024 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1025 return false;
1026 }
1027
1028 if (efer & EFER_SVME) {
1029 struct kvm_cpuid_entry2 *feat;
1030
1031 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1032 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1033 return false;
1034 }
1035
1036 return true;
1037 }
1038 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1039
1040 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1041 {
1042 u64 old_efer = vcpu->arch.efer;
1043
1044 if (!kvm_valid_efer(vcpu, efer))
1045 return 1;
1046
1047 if (is_paging(vcpu)
1048 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1049 return 1;
1050
1051 efer &= ~EFER_LMA;
1052 efer |= vcpu->arch.efer & EFER_LMA;
1053
1054 kvm_x86_ops->set_efer(vcpu, efer);
1055
1056 /* Update reserved bits */
1057 if ((efer ^ old_efer) & EFER_NX)
1058 kvm_mmu_reset_context(vcpu);
1059
1060 return 0;
1061 }
1062
1063 void kvm_enable_efer_bits(u64 mask)
1064 {
1065 efer_reserved_bits &= ~mask;
1066 }
1067 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1068
1069 /*
1070 * Writes msr value into into the appropriate "register".
1071 * Returns 0 on success, non-0 otherwise.
1072 * Assumes vcpu_load() was already called.
1073 */
1074 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1075 {
1076 switch (msr->index) {
1077 case MSR_FS_BASE:
1078 case MSR_GS_BASE:
1079 case MSR_KERNEL_GS_BASE:
1080 case MSR_CSTAR:
1081 case MSR_LSTAR:
1082 if (is_noncanonical_address(msr->data))
1083 return 1;
1084 break;
1085 case MSR_IA32_SYSENTER_EIP:
1086 case MSR_IA32_SYSENTER_ESP:
1087 /*
1088 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1089 * non-canonical address is written on Intel but not on
1090 * AMD (which ignores the top 32-bits, because it does
1091 * not implement 64-bit SYSENTER).
1092 *
1093 * 64-bit code should hence be able to write a non-canonical
1094 * value on AMD. Making the address canonical ensures that
1095 * vmentry does not fail on Intel after writing a non-canonical
1096 * value, and that something deterministic happens if the guest
1097 * invokes 64-bit SYSENTER.
1098 */
1099 msr->data = get_canonical(msr->data);
1100 }
1101 return kvm_x86_ops->set_msr(vcpu, msr);
1102 }
1103 EXPORT_SYMBOL_GPL(kvm_set_msr);
1104
1105 /*
1106 * Adapt set_msr() to msr_io()'s calling convention
1107 */
1108 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1109 {
1110 struct msr_data msr;
1111 int r;
1112
1113 msr.index = index;
1114 msr.host_initiated = true;
1115 r = kvm_get_msr(vcpu, &msr);
1116 if (r)
1117 return r;
1118
1119 *data = msr.data;
1120 return 0;
1121 }
1122
1123 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1124 {
1125 struct msr_data msr;
1126
1127 msr.data = *data;
1128 msr.index = index;
1129 msr.host_initiated = true;
1130 return kvm_set_msr(vcpu, &msr);
1131 }
1132
1133 #ifdef CONFIG_X86_64
1134 struct pvclock_gtod_data {
1135 seqcount_t seq;
1136
1137 struct { /* extract of a clocksource struct */
1138 int vclock_mode;
1139 u64 cycle_last;
1140 u64 mask;
1141 u32 mult;
1142 u32 shift;
1143 } clock;
1144
1145 u64 boot_ns;
1146 u64 nsec_base;
1147 u64 wall_time_sec;
1148 };
1149
1150 static struct pvclock_gtod_data pvclock_gtod_data;
1151
1152 static void update_pvclock_gtod(struct timekeeper *tk)
1153 {
1154 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1155 u64 boot_ns;
1156
1157 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1158
1159 write_seqcount_begin(&vdata->seq);
1160
1161 /* copy pvclock gtod data */
1162 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1163 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1164 vdata->clock.mask = tk->tkr_mono.mask;
1165 vdata->clock.mult = tk->tkr_mono.mult;
1166 vdata->clock.shift = tk->tkr_mono.shift;
1167
1168 vdata->boot_ns = boot_ns;
1169 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1170
1171 vdata->wall_time_sec = tk->xtime_sec;
1172
1173 write_seqcount_end(&vdata->seq);
1174 }
1175 #endif
1176
1177 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1178 {
1179 /*
1180 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1181 * vcpu_enter_guest. This function is only called from
1182 * the physical CPU that is running vcpu.
1183 */
1184 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1185 }
1186
1187 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1188 {
1189 int version;
1190 int r;
1191 struct pvclock_wall_clock wc;
1192 struct timespec64 boot;
1193
1194 if (!wall_clock)
1195 return;
1196
1197 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1198 if (r)
1199 return;
1200
1201 if (version & 1)
1202 ++version; /* first time write, random junk */
1203
1204 ++version;
1205
1206 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1207 return;
1208
1209 /*
1210 * The guest calculates current wall clock time by adding
1211 * system time (updated by kvm_guest_time_update below) to the
1212 * wall clock specified here. guest system time equals host
1213 * system time for us, thus we must fill in host boot time here.
1214 */
1215 getboottime64(&boot);
1216
1217 if (kvm->arch.kvmclock_offset) {
1218 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1219 boot = timespec64_sub(boot, ts);
1220 }
1221 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1222 wc.nsec = boot.tv_nsec;
1223 wc.version = version;
1224
1225 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1226
1227 version++;
1228 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1229 }
1230
1231 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1232 {
1233 do_shl32_div32(dividend, divisor);
1234 return dividend;
1235 }
1236
1237 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1238 s8 *pshift, u32 *pmultiplier)
1239 {
1240 uint64_t scaled64;
1241 int32_t shift = 0;
1242 uint64_t tps64;
1243 uint32_t tps32;
1244
1245 tps64 = base_hz;
1246 scaled64 = scaled_hz;
1247 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1248 tps64 >>= 1;
1249 shift--;
1250 }
1251
1252 tps32 = (uint32_t)tps64;
1253 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1254 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1255 scaled64 >>= 1;
1256 else
1257 tps32 <<= 1;
1258 shift++;
1259 }
1260
1261 *pshift = shift;
1262 *pmultiplier = div_frac(scaled64, tps32);
1263
1264 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1265 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1266 }
1267
1268 #ifdef CONFIG_X86_64
1269 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1270 #endif
1271
1272 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1273 static unsigned long max_tsc_khz;
1274
1275 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1276 {
1277 u64 v = (u64)khz * (1000000 + ppm);
1278 do_div(v, 1000000);
1279 return v;
1280 }
1281
1282 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1283 {
1284 u64 ratio;
1285
1286 /* Guest TSC same frequency as host TSC? */
1287 if (!scale) {
1288 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1289 return 0;
1290 }
1291
1292 /* TSC scaling supported? */
1293 if (!kvm_has_tsc_control) {
1294 if (user_tsc_khz > tsc_khz) {
1295 vcpu->arch.tsc_catchup = 1;
1296 vcpu->arch.tsc_always_catchup = 1;
1297 return 0;
1298 } else {
1299 WARN(1, "user requested TSC rate below hardware speed\n");
1300 return -1;
1301 }
1302 }
1303
1304 /* TSC scaling required - calculate ratio */
1305 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1306 user_tsc_khz, tsc_khz);
1307
1308 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1309 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1310 user_tsc_khz);
1311 return -1;
1312 }
1313
1314 vcpu->arch.tsc_scaling_ratio = ratio;
1315 return 0;
1316 }
1317
1318 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1319 {
1320 u32 thresh_lo, thresh_hi;
1321 int use_scaling = 0;
1322
1323 /* tsc_khz can be zero if TSC calibration fails */
1324 if (user_tsc_khz == 0) {
1325 /* set tsc_scaling_ratio to a safe value */
1326 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1327 return -1;
1328 }
1329
1330 /* Compute a scale to convert nanoseconds in TSC cycles */
1331 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1332 &vcpu->arch.virtual_tsc_shift,
1333 &vcpu->arch.virtual_tsc_mult);
1334 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1335
1336 /*
1337 * Compute the variation in TSC rate which is acceptable
1338 * within the range of tolerance and decide if the
1339 * rate being applied is within that bounds of the hardware
1340 * rate. If so, no scaling or compensation need be done.
1341 */
1342 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1343 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1344 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1345 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1346 use_scaling = 1;
1347 }
1348 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1349 }
1350
1351 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1352 {
1353 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1354 vcpu->arch.virtual_tsc_mult,
1355 vcpu->arch.virtual_tsc_shift);
1356 tsc += vcpu->arch.this_tsc_write;
1357 return tsc;
1358 }
1359
1360 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1361 {
1362 #ifdef CONFIG_X86_64
1363 bool vcpus_matched;
1364 struct kvm_arch *ka = &vcpu->kvm->arch;
1365 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1366
1367 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1368 atomic_read(&vcpu->kvm->online_vcpus));
1369
1370 /*
1371 * Once the masterclock is enabled, always perform request in
1372 * order to update it.
1373 *
1374 * In order to enable masterclock, the host clocksource must be TSC
1375 * and the vcpus need to have matched TSCs. When that happens,
1376 * perform request to enable masterclock.
1377 */
1378 if (ka->use_master_clock ||
1379 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1380 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1381
1382 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1383 atomic_read(&vcpu->kvm->online_vcpus),
1384 ka->use_master_clock, gtod->clock.vclock_mode);
1385 #endif
1386 }
1387
1388 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1389 {
1390 u64 curr_offset = vcpu->arch.tsc_offset;
1391 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1392 }
1393
1394 /*
1395 * Multiply tsc by a fixed point number represented by ratio.
1396 *
1397 * The most significant 64-N bits (mult) of ratio represent the
1398 * integral part of the fixed point number; the remaining N bits
1399 * (frac) represent the fractional part, ie. ratio represents a fixed
1400 * point number (mult + frac * 2^(-N)).
1401 *
1402 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1403 */
1404 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1405 {
1406 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1407 }
1408
1409 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1410 {
1411 u64 _tsc = tsc;
1412 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1413
1414 if (ratio != kvm_default_tsc_scaling_ratio)
1415 _tsc = __scale_tsc(ratio, tsc);
1416
1417 return _tsc;
1418 }
1419 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1420
1421 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1422 {
1423 u64 tsc;
1424
1425 tsc = kvm_scale_tsc(vcpu, rdtsc());
1426
1427 return target_tsc - tsc;
1428 }
1429
1430 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1431 {
1432 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1433 }
1434 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1435
1436 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1437 {
1438 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1439 vcpu->arch.tsc_offset = offset;
1440 }
1441
1442 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1443 {
1444 struct kvm *kvm = vcpu->kvm;
1445 u64 offset, ns, elapsed;
1446 unsigned long flags;
1447 s64 usdiff;
1448 bool matched;
1449 bool already_matched;
1450 u64 data = msr->data;
1451
1452 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1453 offset = kvm_compute_tsc_offset(vcpu, data);
1454 ns = ktime_get_boot_ns();
1455 elapsed = ns - kvm->arch.last_tsc_nsec;
1456
1457 if (vcpu->arch.virtual_tsc_khz) {
1458 int faulted = 0;
1459
1460 /* n.b - signed multiplication and division required */
1461 usdiff = data - kvm->arch.last_tsc_write;
1462 #ifdef CONFIG_X86_64
1463 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1464 #else
1465 /* do_div() only does unsigned */
1466 asm("1: idivl %[divisor]\n"
1467 "2: xor %%edx, %%edx\n"
1468 " movl $0, %[faulted]\n"
1469 "3:\n"
1470 ".section .fixup,\"ax\"\n"
1471 "4: movl $1, %[faulted]\n"
1472 " jmp 3b\n"
1473 ".previous\n"
1474
1475 _ASM_EXTABLE(1b, 4b)
1476
1477 : "=A"(usdiff), [faulted] "=r" (faulted)
1478 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1479
1480 #endif
1481 do_div(elapsed, 1000);
1482 usdiff -= elapsed;
1483 if (usdiff < 0)
1484 usdiff = -usdiff;
1485
1486 /* idivl overflow => difference is larger than USEC_PER_SEC */
1487 if (faulted)
1488 usdiff = USEC_PER_SEC;
1489 } else
1490 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1491
1492 /*
1493 * Special case: TSC write with a small delta (1 second) of virtual
1494 * cycle time against real time is interpreted as an attempt to
1495 * synchronize the CPU.
1496 *
1497 * For a reliable TSC, we can match TSC offsets, and for an unstable
1498 * TSC, we add elapsed time in this computation. We could let the
1499 * compensation code attempt to catch up if we fall behind, but
1500 * it's better to try to match offsets from the beginning.
1501 */
1502 if (usdiff < USEC_PER_SEC &&
1503 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1504 if (!check_tsc_unstable()) {
1505 offset = kvm->arch.cur_tsc_offset;
1506 pr_debug("kvm: matched tsc offset for %llu\n", data);
1507 } else {
1508 u64 delta = nsec_to_cycles(vcpu, elapsed);
1509 data += delta;
1510 offset = kvm_compute_tsc_offset(vcpu, data);
1511 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1512 }
1513 matched = true;
1514 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1515 } else {
1516 /*
1517 * We split periods of matched TSC writes into generations.
1518 * For each generation, we track the original measured
1519 * nanosecond time, offset, and write, so if TSCs are in
1520 * sync, we can match exact offset, and if not, we can match
1521 * exact software computation in compute_guest_tsc()
1522 *
1523 * These values are tracked in kvm->arch.cur_xxx variables.
1524 */
1525 kvm->arch.cur_tsc_generation++;
1526 kvm->arch.cur_tsc_nsec = ns;
1527 kvm->arch.cur_tsc_write = data;
1528 kvm->arch.cur_tsc_offset = offset;
1529 matched = false;
1530 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1531 kvm->arch.cur_tsc_generation, data);
1532 }
1533
1534 /*
1535 * We also track th most recent recorded KHZ, write and time to
1536 * allow the matching interval to be extended at each write.
1537 */
1538 kvm->arch.last_tsc_nsec = ns;
1539 kvm->arch.last_tsc_write = data;
1540 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1541
1542 vcpu->arch.last_guest_tsc = data;
1543
1544 /* Keep track of which generation this VCPU has synchronized to */
1545 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1546 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1547 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1548
1549 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1550 update_ia32_tsc_adjust_msr(vcpu, offset);
1551 kvm_vcpu_write_tsc_offset(vcpu, offset);
1552 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1553
1554 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1555 if (!matched) {
1556 kvm->arch.nr_vcpus_matched_tsc = 0;
1557 } else if (!already_matched) {
1558 kvm->arch.nr_vcpus_matched_tsc++;
1559 }
1560
1561 kvm_track_tsc_matching(vcpu);
1562 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1563 }
1564
1565 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1566
1567 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1568 s64 adjustment)
1569 {
1570 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1571 }
1572
1573 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1574 {
1575 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1576 WARN_ON(adjustment < 0);
1577 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1578 adjust_tsc_offset_guest(vcpu, adjustment);
1579 }
1580
1581 #ifdef CONFIG_X86_64
1582
1583 static u64 read_tsc(void)
1584 {
1585 u64 ret = (u64)rdtsc_ordered();
1586 u64 last = pvclock_gtod_data.clock.cycle_last;
1587
1588 if (likely(ret >= last))
1589 return ret;
1590
1591 /*
1592 * GCC likes to generate cmov here, but this branch is extremely
1593 * predictable (it's just a function of time and the likely is
1594 * very likely) and there's a data dependence, so force GCC
1595 * to generate a branch instead. I don't barrier() because
1596 * we don't actually need a barrier, and if this function
1597 * ever gets inlined it will generate worse code.
1598 */
1599 asm volatile ("");
1600 return last;
1601 }
1602
1603 static inline u64 vgettsc(u64 *cycle_now)
1604 {
1605 long v;
1606 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1607
1608 *cycle_now = read_tsc();
1609
1610 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1611 return v * gtod->clock.mult;
1612 }
1613
1614 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1615 {
1616 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1617 unsigned long seq;
1618 int mode;
1619 u64 ns;
1620
1621 do {
1622 seq = read_seqcount_begin(&gtod->seq);
1623 mode = gtod->clock.vclock_mode;
1624 ns = gtod->nsec_base;
1625 ns += vgettsc(cycle_now);
1626 ns >>= gtod->clock.shift;
1627 ns += gtod->boot_ns;
1628 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1629 *t = ns;
1630
1631 return mode;
1632 }
1633
1634 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1635 {
1636 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1637 unsigned long seq;
1638 int mode;
1639 u64 ns;
1640
1641 do {
1642 seq = read_seqcount_begin(&gtod->seq);
1643 mode = gtod->clock.vclock_mode;
1644 ts->tv_sec = gtod->wall_time_sec;
1645 ns = gtod->nsec_base;
1646 ns += vgettsc(cycle_now);
1647 ns >>= gtod->clock.shift;
1648 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1649
1650 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1651 ts->tv_nsec = ns;
1652
1653 return mode;
1654 }
1655
1656 /* returns true if host is using tsc clocksource */
1657 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1658 {
1659 /* checked again under seqlock below */
1660 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1661 return false;
1662
1663 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1664 }
1665
1666 /* returns true if host is using tsc clocksource */
1667 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1668 u64 *cycle_now)
1669 {
1670 /* checked again under seqlock below */
1671 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1672 return false;
1673
1674 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1675 }
1676 #endif
1677
1678 /*
1679 *
1680 * Assuming a stable TSC across physical CPUS, and a stable TSC
1681 * across virtual CPUs, the following condition is possible.
1682 * Each numbered line represents an event visible to both
1683 * CPUs at the next numbered event.
1684 *
1685 * "timespecX" represents host monotonic time. "tscX" represents
1686 * RDTSC value.
1687 *
1688 * VCPU0 on CPU0 | VCPU1 on CPU1
1689 *
1690 * 1. read timespec0,tsc0
1691 * 2. | timespec1 = timespec0 + N
1692 * | tsc1 = tsc0 + M
1693 * 3. transition to guest | transition to guest
1694 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1695 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1696 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1697 *
1698 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1699 *
1700 * - ret0 < ret1
1701 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1702 * ...
1703 * - 0 < N - M => M < N
1704 *
1705 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1706 * always the case (the difference between two distinct xtime instances
1707 * might be smaller then the difference between corresponding TSC reads,
1708 * when updating guest vcpus pvclock areas).
1709 *
1710 * To avoid that problem, do not allow visibility of distinct
1711 * system_timestamp/tsc_timestamp values simultaneously: use a master
1712 * copy of host monotonic time values. Update that master copy
1713 * in lockstep.
1714 *
1715 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1716 *
1717 */
1718
1719 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1720 {
1721 #ifdef CONFIG_X86_64
1722 struct kvm_arch *ka = &kvm->arch;
1723 int vclock_mode;
1724 bool host_tsc_clocksource, vcpus_matched;
1725
1726 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1727 atomic_read(&kvm->online_vcpus));
1728
1729 /*
1730 * If the host uses TSC clock, then passthrough TSC as stable
1731 * to the guest.
1732 */
1733 host_tsc_clocksource = kvm_get_time_and_clockread(
1734 &ka->master_kernel_ns,
1735 &ka->master_cycle_now);
1736
1737 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1738 && !backwards_tsc_observed
1739 && !ka->boot_vcpu_runs_old_kvmclock;
1740
1741 if (ka->use_master_clock)
1742 atomic_set(&kvm_guest_has_master_clock, 1);
1743
1744 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1745 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1746 vcpus_matched);
1747 #endif
1748 }
1749
1750 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1751 {
1752 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1753 }
1754
1755 static void kvm_gen_update_masterclock(struct kvm *kvm)
1756 {
1757 #ifdef CONFIG_X86_64
1758 int i;
1759 struct kvm_vcpu *vcpu;
1760 struct kvm_arch *ka = &kvm->arch;
1761
1762 spin_lock(&ka->pvclock_gtod_sync_lock);
1763 kvm_make_mclock_inprogress_request(kvm);
1764 /* no guest entries from this point */
1765 pvclock_update_vm_gtod_copy(kvm);
1766
1767 kvm_for_each_vcpu(i, vcpu, kvm)
1768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1769
1770 /* guest entries allowed */
1771 kvm_for_each_vcpu(i, vcpu, kvm)
1772 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1773
1774 spin_unlock(&ka->pvclock_gtod_sync_lock);
1775 #endif
1776 }
1777
1778 static u64 __get_kvmclock_ns(struct kvm *kvm)
1779 {
1780 struct kvm_arch *ka = &kvm->arch;
1781 struct pvclock_vcpu_time_info hv_clock;
1782 u64 ret;
1783
1784 spin_lock(&ka->pvclock_gtod_sync_lock);
1785 if (!ka->use_master_clock) {
1786 spin_unlock(&ka->pvclock_gtod_sync_lock);
1787 return ktime_get_boot_ns() + ka->kvmclock_offset;
1788 }
1789
1790 hv_clock.tsc_timestamp = ka->master_cycle_now;
1791 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1792 spin_unlock(&ka->pvclock_gtod_sync_lock);
1793
1794 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1795 get_cpu();
1796
1797 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1798 &hv_clock.tsc_shift,
1799 &hv_clock.tsc_to_system_mul);
1800 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1801
1802 put_cpu();
1803
1804 return ret;
1805 }
1806
1807 u64 get_kvmclock_ns(struct kvm *kvm)
1808 {
1809 unsigned long flags;
1810 s64 ns;
1811
1812 local_irq_save(flags);
1813 ns = __get_kvmclock_ns(kvm);
1814 local_irq_restore(flags);
1815
1816 return ns;
1817 }
1818
1819 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1820 {
1821 struct kvm_vcpu_arch *vcpu = &v->arch;
1822 struct pvclock_vcpu_time_info guest_hv_clock;
1823
1824 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1825 &guest_hv_clock, sizeof(guest_hv_clock))))
1826 return;
1827
1828 /* This VCPU is paused, but it's legal for a guest to read another
1829 * VCPU's kvmclock, so we really have to follow the specification where
1830 * it says that version is odd if data is being modified, and even after
1831 * it is consistent.
1832 *
1833 * Version field updates must be kept separate. This is because
1834 * kvm_write_guest_cached might use a "rep movs" instruction, and
1835 * writes within a string instruction are weakly ordered. So there
1836 * are three writes overall.
1837 *
1838 * As a small optimization, only write the version field in the first
1839 * and third write. The vcpu->pv_time cache is still valid, because the
1840 * version field is the first in the struct.
1841 */
1842 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1843
1844 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
1848
1849 smp_wmb();
1850
1851 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1852 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1853
1854 if (vcpu->pvclock_set_guest_stopped_request) {
1855 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1856 vcpu->pvclock_set_guest_stopped_request = false;
1857 }
1858
1859 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1860
1861 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1862 &vcpu->hv_clock,
1863 sizeof(vcpu->hv_clock));
1864
1865 smp_wmb();
1866
1867 vcpu->hv_clock.version++;
1868 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1869 &vcpu->hv_clock,
1870 sizeof(vcpu->hv_clock.version));
1871 }
1872
1873 static int kvm_guest_time_update(struct kvm_vcpu *v)
1874 {
1875 unsigned long flags, tgt_tsc_khz;
1876 struct kvm_vcpu_arch *vcpu = &v->arch;
1877 struct kvm_arch *ka = &v->kvm->arch;
1878 s64 kernel_ns;
1879 u64 tsc_timestamp, host_tsc;
1880 u8 pvclock_flags;
1881 bool use_master_clock;
1882
1883 kernel_ns = 0;
1884 host_tsc = 0;
1885
1886 /*
1887 * If the host uses TSC clock, then passthrough TSC as stable
1888 * to the guest.
1889 */
1890 spin_lock(&ka->pvclock_gtod_sync_lock);
1891 use_master_clock = ka->use_master_clock;
1892 if (use_master_clock) {
1893 host_tsc = ka->master_cycle_now;
1894 kernel_ns = ka->master_kernel_ns;
1895 }
1896 spin_unlock(&ka->pvclock_gtod_sync_lock);
1897
1898 /* Keep irq disabled to prevent changes to the clock */
1899 local_irq_save(flags);
1900 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1901 if (unlikely(tgt_tsc_khz == 0)) {
1902 local_irq_restore(flags);
1903 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1904 return 1;
1905 }
1906 if (!use_master_clock) {
1907 host_tsc = rdtsc();
1908 kernel_ns = ktime_get_boot_ns();
1909 }
1910
1911 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1912
1913 /*
1914 * We may have to catch up the TSC to match elapsed wall clock
1915 * time for two reasons, even if kvmclock is used.
1916 * 1) CPU could have been running below the maximum TSC rate
1917 * 2) Broken TSC compensation resets the base at each VCPU
1918 * entry to avoid unknown leaps of TSC even when running
1919 * again on the same CPU. This may cause apparent elapsed
1920 * time to disappear, and the guest to stand still or run
1921 * very slowly.
1922 */
1923 if (vcpu->tsc_catchup) {
1924 u64 tsc = compute_guest_tsc(v, kernel_ns);
1925 if (tsc > tsc_timestamp) {
1926 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1927 tsc_timestamp = tsc;
1928 }
1929 }
1930
1931 local_irq_restore(flags);
1932
1933 /* With all the info we got, fill in the values */
1934
1935 if (kvm_has_tsc_control)
1936 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1937
1938 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1939 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1940 &vcpu->hv_clock.tsc_shift,
1941 &vcpu->hv_clock.tsc_to_system_mul);
1942 vcpu->hw_tsc_khz = tgt_tsc_khz;
1943 }
1944
1945 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1946 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1947 vcpu->last_guest_tsc = tsc_timestamp;
1948
1949 /* If the host uses TSC clocksource, then it is stable */
1950 pvclock_flags = 0;
1951 if (use_master_clock)
1952 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1953
1954 vcpu->hv_clock.flags = pvclock_flags;
1955
1956 if (vcpu->pv_time_enabled)
1957 kvm_setup_pvclock_page(v);
1958 if (v == kvm_get_vcpu(v->kvm, 0))
1959 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1960 return 0;
1961 }
1962
1963 /*
1964 * kvmclock updates which are isolated to a given vcpu, such as
1965 * vcpu->cpu migration, should not allow system_timestamp from
1966 * the rest of the vcpus to remain static. Otherwise ntp frequency
1967 * correction applies to one vcpu's system_timestamp but not
1968 * the others.
1969 *
1970 * So in those cases, request a kvmclock update for all vcpus.
1971 * We need to rate-limit these requests though, as they can
1972 * considerably slow guests that have a large number of vcpus.
1973 * The time for a remote vcpu to update its kvmclock is bound
1974 * by the delay we use to rate-limit the updates.
1975 */
1976
1977 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1978
1979 static void kvmclock_update_fn(struct work_struct *work)
1980 {
1981 int i;
1982 struct delayed_work *dwork = to_delayed_work(work);
1983 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1984 kvmclock_update_work);
1985 struct kvm *kvm = container_of(ka, struct kvm, arch);
1986 struct kvm_vcpu *vcpu;
1987
1988 kvm_for_each_vcpu(i, vcpu, kvm) {
1989 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1990 kvm_vcpu_kick(vcpu);
1991 }
1992 }
1993
1994 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1995 {
1996 struct kvm *kvm = v->kvm;
1997
1998 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1999 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2000 KVMCLOCK_UPDATE_DELAY);
2001 }
2002
2003 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2004
2005 static void kvmclock_sync_fn(struct work_struct *work)
2006 {
2007 struct delayed_work *dwork = to_delayed_work(work);
2008 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2009 kvmclock_sync_work);
2010 struct kvm *kvm = container_of(ka, struct kvm, arch);
2011
2012 if (!kvmclock_periodic_sync)
2013 return;
2014
2015 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2016 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2017 KVMCLOCK_SYNC_PERIOD);
2018 }
2019
2020 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2021 {
2022 u64 mcg_cap = vcpu->arch.mcg_cap;
2023 unsigned bank_num = mcg_cap & 0xff;
2024
2025 switch (msr) {
2026 case MSR_IA32_MCG_STATUS:
2027 vcpu->arch.mcg_status = data;
2028 break;
2029 case MSR_IA32_MCG_CTL:
2030 if (!(mcg_cap & MCG_CTL_P))
2031 return 1;
2032 if (data != 0 && data != ~(u64)0)
2033 return -1;
2034 vcpu->arch.mcg_ctl = data;
2035 break;
2036 default:
2037 if (msr >= MSR_IA32_MC0_CTL &&
2038 msr < MSR_IA32_MCx_CTL(bank_num)) {
2039 u32 offset = msr - MSR_IA32_MC0_CTL;
2040 /* only 0 or all 1s can be written to IA32_MCi_CTL
2041 * some Linux kernels though clear bit 10 in bank 4 to
2042 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2043 * this to avoid an uncatched #GP in the guest
2044 */
2045 if ((offset & 0x3) == 0 &&
2046 data != 0 && (data | (1 << 10)) != ~(u64)0)
2047 return -1;
2048 vcpu->arch.mce_banks[offset] = data;
2049 break;
2050 }
2051 return 1;
2052 }
2053 return 0;
2054 }
2055
2056 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2057 {
2058 struct kvm *kvm = vcpu->kvm;
2059 int lm = is_long_mode(vcpu);
2060 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2061 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2062 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2063 : kvm->arch.xen_hvm_config.blob_size_32;
2064 u32 page_num = data & ~PAGE_MASK;
2065 u64 page_addr = data & PAGE_MASK;
2066 u8 *page;
2067 int r;
2068
2069 r = -E2BIG;
2070 if (page_num >= blob_size)
2071 goto out;
2072 r = -ENOMEM;
2073 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2074 if (IS_ERR(page)) {
2075 r = PTR_ERR(page);
2076 goto out;
2077 }
2078 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2079 goto out_free;
2080 r = 0;
2081 out_free:
2082 kfree(page);
2083 out:
2084 return r;
2085 }
2086
2087 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2088 {
2089 gpa_t gpa = data & ~0x3f;
2090
2091 /* Bits 2:5 are reserved, Should be zero */
2092 if (data & 0x3c)
2093 return 1;
2094
2095 vcpu->arch.apf.msr_val = data;
2096
2097 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2098 kvm_clear_async_pf_completion_queue(vcpu);
2099 kvm_async_pf_hash_reset(vcpu);
2100 return 0;
2101 }
2102
2103 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2104 sizeof(u32)))
2105 return 1;
2106
2107 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2108 kvm_async_pf_wakeup_all(vcpu);
2109 return 0;
2110 }
2111
2112 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2113 {
2114 vcpu->arch.pv_time_enabled = false;
2115 }
2116
2117 static void record_steal_time(struct kvm_vcpu *vcpu)
2118 {
2119 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2120 return;
2121
2122 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2123 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2124 return;
2125
2126 vcpu->arch.st.steal.preempted = 0;
2127
2128 if (vcpu->arch.st.steal.version & 1)
2129 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2130
2131 vcpu->arch.st.steal.version += 1;
2132
2133 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2134 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2135
2136 smp_wmb();
2137
2138 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2139 vcpu->arch.st.last_steal;
2140 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2141
2142 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2143 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2144
2145 smp_wmb();
2146
2147 vcpu->arch.st.steal.version += 1;
2148
2149 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2150 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2151 }
2152
2153 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2154 {
2155 bool pr = false;
2156 u32 msr = msr_info->index;
2157 u64 data = msr_info->data;
2158
2159 switch (msr) {
2160 case MSR_AMD64_NB_CFG:
2161 case MSR_IA32_UCODE_REV:
2162 case MSR_IA32_UCODE_WRITE:
2163 case MSR_VM_HSAVE_PA:
2164 case MSR_AMD64_PATCH_LOADER:
2165 case MSR_AMD64_BU_CFG2:
2166 break;
2167
2168 case MSR_EFER:
2169 return set_efer(vcpu, data);
2170 case MSR_K7_HWCR:
2171 data &= ~(u64)0x40; /* ignore flush filter disable */
2172 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2173 data &= ~(u64)0x8; /* ignore TLB cache disable */
2174 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2175 if (data != 0) {
2176 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2177 data);
2178 return 1;
2179 }
2180 break;
2181 case MSR_FAM10H_MMIO_CONF_BASE:
2182 if (data != 0) {
2183 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2184 "0x%llx\n", data);
2185 return 1;
2186 }
2187 break;
2188 case MSR_IA32_DEBUGCTLMSR:
2189 if (!data) {
2190 /* We support the non-activated case already */
2191 break;
2192 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2193 /* Values other than LBR and BTF are vendor-specific,
2194 thus reserved and should throw a #GP */
2195 return 1;
2196 }
2197 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2198 __func__, data);
2199 break;
2200 case 0x200 ... 0x2ff:
2201 return kvm_mtrr_set_msr(vcpu, msr, data);
2202 case MSR_IA32_APICBASE:
2203 return kvm_set_apic_base(vcpu, msr_info);
2204 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2205 return kvm_x2apic_msr_write(vcpu, msr, data);
2206 case MSR_IA32_TSCDEADLINE:
2207 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2208 break;
2209 case MSR_IA32_TSC_ADJUST:
2210 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2211 if (!msr_info->host_initiated) {
2212 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2213 adjust_tsc_offset_guest(vcpu, adj);
2214 }
2215 vcpu->arch.ia32_tsc_adjust_msr = data;
2216 }
2217 break;
2218 case MSR_IA32_MISC_ENABLE:
2219 vcpu->arch.ia32_misc_enable_msr = data;
2220 break;
2221 case MSR_IA32_SMBASE:
2222 if (!msr_info->host_initiated)
2223 return 1;
2224 vcpu->arch.smbase = data;
2225 break;
2226 case MSR_KVM_WALL_CLOCK_NEW:
2227 case MSR_KVM_WALL_CLOCK:
2228 vcpu->kvm->arch.wall_clock = data;
2229 kvm_write_wall_clock(vcpu->kvm, data);
2230 break;
2231 case MSR_KVM_SYSTEM_TIME_NEW:
2232 case MSR_KVM_SYSTEM_TIME: {
2233 struct kvm_arch *ka = &vcpu->kvm->arch;
2234
2235 kvmclock_reset(vcpu);
2236
2237 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2238 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2239
2240 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2241 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2242 &vcpu->requests);
2243
2244 ka->boot_vcpu_runs_old_kvmclock = tmp;
2245 }
2246
2247 vcpu->arch.time = data;
2248 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2249
2250 /* we verify if the enable bit is set... */
2251 if (!(data & 1))
2252 break;
2253
2254 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2255 &vcpu->arch.pv_time, data & ~1ULL,
2256 sizeof(struct pvclock_vcpu_time_info)))
2257 vcpu->arch.pv_time_enabled = false;
2258 else
2259 vcpu->arch.pv_time_enabled = true;
2260
2261 break;
2262 }
2263 case MSR_KVM_ASYNC_PF_EN:
2264 if (kvm_pv_enable_async_pf(vcpu, data))
2265 return 1;
2266 break;
2267 case MSR_KVM_STEAL_TIME:
2268
2269 if (unlikely(!sched_info_on()))
2270 return 1;
2271
2272 if (data & KVM_STEAL_RESERVED_MASK)
2273 return 1;
2274
2275 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2276 data & KVM_STEAL_VALID_BITS,
2277 sizeof(struct kvm_steal_time)))
2278 return 1;
2279
2280 vcpu->arch.st.msr_val = data;
2281
2282 if (!(data & KVM_MSR_ENABLED))
2283 break;
2284
2285 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2286
2287 break;
2288 case MSR_KVM_PV_EOI_EN:
2289 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2290 return 1;
2291 break;
2292
2293 case MSR_IA32_MCG_CTL:
2294 case MSR_IA32_MCG_STATUS:
2295 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2296 return set_msr_mce(vcpu, msr, data);
2297
2298 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2299 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2300 pr = true; /* fall through */
2301 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2302 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2303 if (kvm_pmu_is_valid_msr(vcpu, msr))
2304 return kvm_pmu_set_msr(vcpu, msr_info);
2305
2306 if (pr || data != 0)
2307 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2308 "0x%x data 0x%llx\n", msr, data);
2309 break;
2310 case MSR_K7_CLK_CTL:
2311 /*
2312 * Ignore all writes to this no longer documented MSR.
2313 * Writes are only relevant for old K7 processors,
2314 * all pre-dating SVM, but a recommended workaround from
2315 * AMD for these chips. It is possible to specify the
2316 * affected processor models on the command line, hence
2317 * the need to ignore the workaround.
2318 */
2319 break;
2320 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2321 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2322 case HV_X64_MSR_CRASH_CTL:
2323 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2324 return kvm_hv_set_msr_common(vcpu, msr, data,
2325 msr_info->host_initiated);
2326 case MSR_IA32_BBL_CR_CTL3:
2327 /* Drop writes to this legacy MSR -- see rdmsr
2328 * counterpart for further detail.
2329 */
2330 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2331 break;
2332 case MSR_AMD64_OSVW_ID_LENGTH:
2333 if (!guest_cpuid_has_osvw(vcpu))
2334 return 1;
2335 vcpu->arch.osvw.length = data;
2336 break;
2337 case MSR_AMD64_OSVW_STATUS:
2338 if (!guest_cpuid_has_osvw(vcpu))
2339 return 1;
2340 vcpu->arch.osvw.status = data;
2341 break;
2342 default:
2343 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2344 return xen_hvm_config(vcpu, data);
2345 if (kvm_pmu_is_valid_msr(vcpu, msr))
2346 return kvm_pmu_set_msr(vcpu, msr_info);
2347 if (!ignore_msrs) {
2348 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2349 msr, data);
2350 return 1;
2351 } else {
2352 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2353 msr, data);
2354 break;
2355 }
2356 }
2357 return 0;
2358 }
2359 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2360
2361
2362 /*
2363 * Reads an msr value (of 'msr_index') into 'pdata'.
2364 * Returns 0 on success, non-0 otherwise.
2365 * Assumes vcpu_load() was already called.
2366 */
2367 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2368 {
2369 return kvm_x86_ops->get_msr(vcpu, msr);
2370 }
2371 EXPORT_SYMBOL_GPL(kvm_get_msr);
2372
2373 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2374 {
2375 u64 data;
2376 u64 mcg_cap = vcpu->arch.mcg_cap;
2377 unsigned bank_num = mcg_cap & 0xff;
2378
2379 switch (msr) {
2380 case MSR_IA32_P5_MC_ADDR:
2381 case MSR_IA32_P5_MC_TYPE:
2382 data = 0;
2383 break;
2384 case MSR_IA32_MCG_CAP:
2385 data = vcpu->arch.mcg_cap;
2386 break;
2387 case MSR_IA32_MCG_CTL:
2388 if (!(mcg_cap & MCG_CTL_P))
2389 return 1;
2390 data = vcpu->arch.mcg_ctl;
2391 break;
2392 case MSR_IA32_MCG_STATUS:
2393 data = vcpu->arch.mcg_status;
2394 break;
2395 default:
2396 if (msr >= MSR_IA32_MC0_CTL &&
2397 msr < MSR_IA32_MCx_CTL(bank_num)) {
2398 u32 offset = msr - MSR_IA32_MC0_CTL;
2399 data = vcpu->arch.mce_banks[offset];
2400 break;
2401 }
2402 return 1;
2403 }
2404 *pdata = data;
2405 return 0;
2406 }
2407
2408 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2409 {
2410 switch (msr_info->index) {
2411 case MSR_IA32_PLATFORM_ID:
2412 case MSR_IA32_EBL_CR_POWERON:
2413 case MSR_IA32_DEBUGCTLMSR:
2414 case MSR_IA32_LASTBRANCHFROMIP:
2415 case MSR_IA32_LASTBRANCHTOIP:
2416 case MSR_IA32_LASTINTFROMIP:
2417 case MSR_IA32_LASTINTTOIP:
2418 case MSR_K8_SYSCFG:
2419 case MSR_K8_TSEG_ADDR:
2420 case MSR_K8_TSEG_MASK:
2421 case MSR_K7_HWCR:
2422 case MSR_VM_HSAVE_PA:
2423 case MSR_K8_INT_PENDING_MSG:
2424 case MSR_AMD64_NB_CFG:
2425 case MSR_FAM10H_MMIO_CONF_BASE:
2426 case MSR_AMD64_BU_CFG2:
2427 case MSR_IA32_PERF_CTL:
2428 msr_info->data = 0;
2429 break;
2430 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2431 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2432 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2433 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2434 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2435 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2436 msr_info->data = 0;
2437 break;
2438 case MSR_IA32_UCODE_REV:
2439 msr_info->data = 0x100000000ULL;
2440 break;
2441 case MSR_MTRRcap:
2442 case 0x200 ... 0x2ff:
2443 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2444 case 0xcd: /* fsb frequency */
2445 msr_info->data = 3;
2446 break;
2447 /*
2448 * MSR_EBC_FREQUENCY_ID
2449 * Conservative value valid for even the basic CPU models.
2450 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2451 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2452 * and 266MHz for model 3, or 4. Set Core Clock
2453 * Frequency to System Bus Frequency Ratio to 1 (bits
2454 * 31:24) even though these are only valid for CPU
2455 * models > 2, however guests may end up dividing or
2456 * multiplying by zero otherwise.
2457 */
2458 case MSR_EBC_FREQUENCY_ID:
2459 msr_info->data = 1 << 24;
2460 break;
2461 case MSR_IA32_APICBASE:
2462 msr_info->data = kvm_get_apic_base(vcpu);
2463 break;
2464 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2465 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2466 break;
2467 case MSR_IA32_TSCDEADLINE:
2468 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2469 break;
2470 case MSR_IA32_TSC_ADJUST:
2471 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2472 break;
2473 case MSR_IA32_MISC_ENABLE:
2474 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2475 break;
2476 case MSR_IA32_SMBASE:
2477 if (!msr_info->host_initiated)
2478 return 1;
2479 msr_info->data = vcpu->arch.smbase;
2480 break;
2481 case MSR_IA32_PERF_STATUS:
2482 /* TSC increment by tick */
2483 msr_info->data = 1000ULL;
2484 /* CPU multiplier */
2485 msr_info->data |= (((uint64_t)4ULL) << 40);
2486 break;
2487 case MSR_EFER:
2488 msr_info->data = vcpu->arch.efer;
2489 break;
2490 case MSR_KVM_WALL_CLOCK:
2491 case MSR_KVM_WALL_CLOCK_NEW:
2492 msr_info->data = vcpu->kvm->arch.wall_clock;
2493 break;
2494 case MSR_KVM_SYSTEM_TIME:
2495 case MSR_KVM_SYSTEM_TIME_NEW:
2496 msr_info->data = vcpu->arch.time;
2497 break;
2498 case MSR_KVM_ASYNC_PF_EN:
2499 msr_info->data = vcpu->arch.apf.msr_val;
2500 break;
2501 case MSR_KVM_STEAL_TIME:
2502 msr_info->data = vcpu->arch.st.msr_val;
2503 break;
2504 case MSR_KVM_PV_EOI_EN:
2505 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2506 break;
2507 case MSR_IA32_P5_MC_ADDR:
2508 case MSR_IA32_P5_MC_TYPE:
2509 case MSR_IA32_MCG_CAP:
2510 case MSR_IA32_MCG_CTL:
2511 case MSR_IA32_MCG_STATUS:
2512 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2513 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2514 case MSR_K7_CLK_CTL:
2515 /*
2516 * Provide expected ramp-up count for K7. All other
2517 * are set to zero, indicating minimum divisors for
2518 * every field.
2519 *
2520 * This prevents guest kernels on AMD host with CPU
2521 * type 6, model 8 and higher from exploding due to
2522 * the rdmsr failing.
2523 */
2524 msr_info->data = 0x20000000;
2525 break;
2526 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2527 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2528 case HV_X64_MSR_CRASH_CTL:
2529 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2530 return kvm_hv_get_msr_common(vcpu,
2531 msr_info->index, &msr_info->data);
2532 break;
2533 case MSR_IA32_BBL_CR_CTL3:
2534 /* This legacy MSR exists but isn't fully documented in current
2535 * silicon. It is however accessed by winxp in very narrow
2536 * scenarios where it sets bit #19, itself documented as
2537 * a "reserved" bit. Best effort attempt to source coherent
2538 * read data here should the balance of the register be
2539 * interpreted by the guest:
2540 *
2541 * L2 cache control register 3: 64GB range, 256KB size,
2542 * enabled, latency 0x1, configured
2543 */
2544 msr_info->data = 0xbe702111;
2545 break;
2546 case MSR_AMD64_OSVW_ID_LENGTH:
2547 if (!guest_cpuid_has_osvw(vcpu))
2548 return 1;
2549 msr_info->data = vcpu->arch.osvw.length;
2550 break;
2551 case MSR_AMD64_OSVW_STATUS:
2552 if (!guest_cpuid_has_osvw(vcpu))
2553 return 1;
2554 msr_info->data = vcpu->arch.osvw.status;
2555 break;
2556 default:
2557 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2558 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2559 if (!ignore_msrs) {
2560 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2561 msr_info->index);
2562 return 1;
2563 } else {
2564 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2565 msr_info->data = 0;
2566 }
2567 break;
2568 }
2569 return 0;
2570 }
2571 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2572
2573 /*
2574 * Read or write a bunch of msrs. All parameters are kernel addresses.
2575 *
2576 * @return number of msrs set successfully.
2577 */
2578 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2579 struct kvm_msr_entry *entries,
2580 int (*do_msr)(struct kvm_vcpu *vcpu,
2581 unsigned index, u64 *data))
2582 {
2583 int i, idx;
2584
2585 idx = srcu_read_lock(&vcpu->kvm->srcu);
2586 for (i = 0; i < msrs->nmsrs; ++i)
2587 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2588 break;
2589 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2590
2591 return i;
2592 }
2593
2594 /*
2595 * Read or write a bunch of msrs. Parameters are user addresses.
2596 *
2597 * @return number of msrs set successfully.
2598 */
2599 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2600 int (*do_msr)(struct kvm_vcpu *vcpu,
2601 unsigned index, u64 *data),
2602 int writeback)
2603 {
2604 struct kvm_msrs msrs;
2605 struct kvm_msr_entry *entries;
2606 int r, n;
2607 unsigned size;
2608
2609 r = -EFAULT;
2610 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2611 goto out;
2612
2613 r = -E2BIG;
2614 if (msrs.nmsrs >= MAX_IO_MSRS)
2615 goto out;
2616
2617 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2618 entries = memdup_user(user_msrs->entries, size);
2619 if (IS_ERR(entries)) {
2620 r = PTR_ERR(entries);
2621 goto out;
2622 }
2623
2624 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2625 if (r < 0)
2626 goto out_free;
2627
2628 r = -EFAULT;
2629 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2630 goto out_free;
2631
2632 r = n;
2633
2634 out_free:
2635 kfree(entries);
2636 out:
2637 return r;
2638 }
2639
2640 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2641 {
2642 int r;
2643
2644 switch (ext) {
2645 case KVM_CAP_IRQCHIP:
2646 case KVM_CAP_HLT:
2647 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2648 case KVM_CAP_SET_TSS_ADDR:
2649 case KVM_CAP_EXT_CPUID:
2650 case KVM_CAP_EXT_EMUL_CPUID:
2651 case KVM_CAP_CLOCKSOURCE:
2652 case KVM_CAP_PIT:
2653 case KVM_CAP_NOP_IO_DELAY:
2654 case KVM_CAP_MP_STATE:
2655 case KVM_CAP_SYNC_MMU:
2656 case KVM_CAP_USER_NMI:
2657 case KVM_CAP_REINJECT_CONTROL:
2658 case KVM_CAP_IRQ_INJECT_STATUS:
2659 case KVM_CAP_IOEVENTFD:
2660 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2661 case KVM_CAP_PIT2:
2662 case KVM_CAP_PIT_STATE2:
2663 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2664 case KVM_CAP_XEN_HVM:
2665 case KVM_CAP_VCPU_EVENTS:
2666 case KVM_CAP_HYPERV:
2667 case KVM_CAP_HYPERV_VAPIC:
2668 case KVM_CAP_HYPERV_SPIN:
2669 case KVM_CAP_HYPERV_SYNIC:
2670 case KVM_CAP_PCI_SEGMENT:
2671 case KVM_CAP_DEBUGREGS:
2672 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2673 case KVM_CAP_XSAVE:
2674 case KVM_CAP_ASYNC_PF:
2675 case KVM_CAP_GET_TSC_KHZ:
2676 case KVM_CAP_KVMCLOCK_CTRL:
2677 case KVM_CAP_READONLY_MEM:
2678 case KVM_CAP_HYPERV_TIME:
2679 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2680 case KVM_CAP_TSC_DEADLINE_TIMER:
2681 case KVM_CAP_ENABLE_CAP_VM:
2682 case KVM_CAP_DISABLE_QUIRKS:
2683 case KVM_CAP_SET_BOOT_CPU_ID:
2684 case KVM_CAP_SPLIT_IRQCHIP:
2685 case KVM_CAP_IMMEDIATE_EXIT:
2686 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2687 case KVM_CAP_ASSIGN_DEV_IRQ:
2688 case KVM_CAP_PCI_2_3:
2689 #endif
2690 r = 1;
2691 break;
2692 case KVM_CAP_ADJUST_CLOCK:
2693 r = KVM_CLOCK_TSC_STABLE;
2694 break;
2695 case KVM_CAP_X86_SMM:
2696 /* SMBASE is usually relocated above 1M on modern chipsets,
2697 * and SMM handlers might indeed rely on 4G segment limits,
2698 * so do not report SMM to be available if real mode is
2699 * emulated via vm86 mode. Still, do not go to great lengths
2700 * to avoid userspace's usage of the feature, because it is a
2701 * fringe case that is not enabled except via specific settings
2702 * of the module parameters.
2703 */
2704 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2705 break;
2706 case KVM_CAP_COALESCED_MMIO:
2707 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2708 break;
2709 case KVM_CAP_VAPIC:
2710 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2711 break;
2712 case KVM_CAP_NR_VCPUS:
2713 r = KVM_SOFT_MAX_VCPUS;
2714 break;
2715 case KVM_CAP_MAX_VCPUS:
2716 r = KVM_MAX_VCPUS;
2717 break;
2718 case KVM_CAP_NR_MEMSLOTS:
2719 r = KVM_USER_MEM_SLOTS;
2720 break;
2721 case KVM_CAP_PV_MMU: /* obsolete */
2722 r = 0;
2723 break;
2724 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2725 case KVM_CAP_IOMMU:
2726 r = iommu_present(&pci_bus_type);
2727 break;
2728 #endif
2729 case KVM_CAP_MCE:
2730 r = KVM_MAX_MCE_BANKS;
2731 break;
2732 case KVM_CAP_XCRS:
2733 r = boot_cpu_has(X86_FEATURE_XSAVE);
2734 break;
2735 case KVM_CAP_TSC_CONTROL:
2736 r = kvm_has_tsc_control;
2737 break;
2738 case KVM_CAP_X2APIC_API:
2739 r = KVM_X2APIC_API_VALID_FLAGS;
2740 break;
2741 default:
2742 r = 0;
2743 break;
2744 }
2745 return r;
2746
2747 }
2748
2749 long kvm_arch_dev_ioctl(struct file *filp,
2750 unsigned int ioctl, unsigned long arg)
2751 {
2752 void __user *argp = (void __user *)arg;
2753 long r;
2754
2755 switch (ioctl) {
2756 case KVM_GET_MSR_INDEX_LIST: {
2757 struct kvm_msr_list __user *user_msr_list = argp;
2758 struct kvm_msr_list msr_list;
2759 unsigned n;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2763 goto out;
2764 n = msr_list.nmsrs;
2765 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2766 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2767 goto out;
2768 r = -E2BIG;
2769 if (n < msr_list.nmsrs)
2770 goto out;
2771 r = -EFAULT;
2772 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2773 num_msrs_to_save * sizeof(u32)))
2774 goto out;
2775 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2776 &emulated_msrs,
2777 num_emulated_msrs * sizeof(u32)))
2778 goto out;
2779 r = 0;
2780 break;
2781 }
2782 case KVM_GET_SUPPORTED_CPUID:
2783 case KVM_GET_EMULATED_CPUID: {
2784 struct kvm_cpuid2 __user *cpuid_arg = argp;
2785 struct kvm_cpuid2 cpuid;
2786
2787 r = -EFAULT;
2788 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2789 goto out;
2790
2791 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2792 ioctl);
2793 if (r)
2794 goto out;
2795
2796 r = -EFAULT;
2797 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2798 goto out;
2799 r = 0;
2800 break;
2801 }
2802 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2803 r = -EFAULT;
2804 if (copy_to_user(argp, &kvm_mce_cap_supported,
2805 sizeof(kvm_mce_cap_supported)))
2806 goto out;
2807 r = 0;
2808 break;
2809 }
2810 default:
2811 r = -EINVAL;
2812 }
2813 out:
2814 return r;
2815 }
2816
2817 static void wbinvd_ipi(void *garbage)
2818 {
2819 wbinvd();
2820 }
2821
2822 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2823 {
2824 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2825 }
2826
2827 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2828 {
2829 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2830 }
2831
2832 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2833 {
2834 /* Address WBINVD may be executed by guest */
2835 if (need_emulate_wbinvd(vcpu)) {
2836 if (kvm_x86_ops->has_wbinvd_exit())
2837 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2838 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2839 smp_call_function_single(vcpu->cpu,
2840 wbinvd_ipi, NULL, 1);
2841 }
2842
2843 kvm_x86_ops->vcpu_load(vcpu, cpu);
2844
2845 /* Apply any externally detected TSC adjustments (due to suspend) */
2846 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2847 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2848 vcpu->arch.tsc_offset_adjustment = 0;
2849 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2850 }
2851
2852 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2853 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2854 rdtsc() - vcpu->arch.last_host_tsc;
2855 if (tsc_delta < 0)
2856 mark_tsc_unstable("KVM discovered backwards TSC");
2857
2858 if (check_tsc_unstable()) {
2859 u64 offset = kvm_compute_tsc_offset(vcpu,
2860 vcpu->arch.last_guest_tsc);
2861 kvm_vcpu_write_tsc_offset(vcpu, offset);
2862 vcpu->arch.tsc_catchup = 1;
2863 }
2864 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2865 kvm_x86_ops->set_hv_timer(vcpu,
2866 kvm_get_lapic_target_expiration_tsc(vcpu)))
2867 kvm_lapic_switch_to_sw_timer(vcpu);
2868 /*
2869 * On a host with synchronized TSC, there is no need to update
2870 * kvmclock on vcpu->cpu migration
2871 */
2872 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2873 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2874 if (vcpu->cpu != cpu)
2875 kvm_migrate_timers(vcpu);
2876 vcpu->cpu = cpu;
2877 }
2878
2879 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2880 }
2881
2882 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2883 {
2884 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2885 return;
2886
2887 vcpu->arch.st.steal.preempted = 1;
2888
2889 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2890 &vcpu->arch.st.steal.preempted,
2891 offsetof(struct kvm_steal_time, preempted),
2892 sizeof(vcpu->arch.st.steal.preempted));
2893 }
2894
2895 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2896 {
2897 int idx;
2898 /*
2899 * Disable page faults because we're in atomic context here.
2900 * kvm_write_guest_offset_cached() would call might_fault()
2901 * that relies on pagefault_disable() to tell if there's a
2902 * bug. NOTE: the write to guest memory may not go through if
2903 * during postcopy live migration or if there's heavy guest
2904 * paging.
2905 */
2906 pagefault_disable();
2907 /*
2908 * kvm_memslots() will be called by
2909 * kvm_write_guest_offset_cached() so take the srcu lock.
2910 */
2911 idx = srcu_read_lock(&vcpu->kvm->srcu);
2912 kvm_steal_time_set_preempted(vcpu);
2913 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2914 pagefault_enable();
2915 kvm_x86_ops->vcpu_put(vcpu);
2916 kvm_put_guest_fpu(vcpu);
2917 vcpu->arch.last_host_tsc = rdtsc();
2918 }
2919
2920 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2921 struct kvm_lapic_state *s)
2922 {
2923 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2924 kvm_x86_ops->sync_pir_to_irr(vcpu);
2925
2926 return kvm_apic_get_state(vcpu, s);
2927 }
2928
2929 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2930 struct kvm_lapic_state *s)
2931 {
2932 int r;
2933
2934 r = kvm_apic_set_state(vcpu, s);
2935 if (r)
2936 return r;
2937 update_cr8_intercept(vcpu);
2938
2939 return 0;
2940 }
2941
2942 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2943 {
2944 return (!lapic_in_kernel(vcpu) ||
2945 kvm_apic_accept_pic_intr(vcpu));
2946 }
2947
2948 /*
2949 * if userspace requested an interrupt window, check that the
2950 * interrupt window is open.
2951 *
2952 * No need to exit to userspace if we already have an interrupt queued.
2953 */
2954 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2955 {
2956 return kvm_arch_interrupt_allowed(vcpu) &&
2957 !kvm_cpu_has_interrupt(vcpu) &&
2958 !kvm_event_needs_reinjection(vcpu) &&
2959 kvm_cpu_accept_dm_intr(vcpu);
2960 }
2961
2962 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2963 struct kvm_interrupt *irq)
2964 {
2965 if (irq->irq >= KVM_NR_INTERRUPTS)
2966 return -EINVAL;
2967
2968 if (!irqchip_in_kernel(vcpu->kvm)) {
2969 kvm_queue_interrupt(vcpu, irq->irq, false);
2970 kvm_make_request(KVM_REQ_EVENT, vcpu);
2971 return 0;
2972 }
2973
2974 /*
2975 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2976 * fail for in-kernel 8259.
2977 */
2978 if (pic_in_kernel(vcpu->kvm))
2979 return -ENXIO;
2980
2981 if (vcpu->arch.pending_external_vector != -1)
2982 return -EEXIST;
2983
2984 vcpu->arch.pending_external_vector = irq->irq;
2985 kvm_make_request(KVM_REQ_EVENT, vcpu);
2986 return 0;
2987 }
2988
2989 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2990 {
2991 kvm_inject_nmi(vcpu);
2992
2993 return 0;
2994 }
2995
2996 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2997 {
2998 kvm_make_request(KVM_REQ_SMI, vcpu);
2999
3000 return 0;
3001 }
3002
3003 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3004 struct kvm_tpr_access_ctl *tac)
3005 {
3006 if (tac->flags)
3007 return -EINVAL;
3008 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3009 return 0;
3010 }
3011
3012 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3013 u64 mcg_cap)
3014 {
3015 int r;
3016 unsigned bank_num = mcg_cap & 0xff, bank;
3017
3018 r = -EINVAL;
3019 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3020 goto out;
3021 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3022 goto out;
3023 r = 0;
3024 vcpu->arch.mcg_cap = mcg_cap;
3025 /* Init IA32_MCG_CTL to all 1s */
3026 if (mcg_cap & MCG_CTL_P)
3027 vcpu->arch.mcg_ctl = ~(u64)0;
3028 /* Init IA32_MCi_CTL to all 1s */
3029 for (bank = 0; bank < bank_num; bank++)
3030 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3031
3032 if (kvm_x86_ops->setup_mce)
3033 kvm_x86_ops->setup_mce(vcpu);
3034 out:
3035 return r;
3036 }
3037
3038 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3039 struct kvm_x86_mce *mce)
3040 {
3041 u64 mcg_cap = vcpu->arch.mcg_cap;
3042 unsigned bank_num = mcg_cap & 0xff;
3043 u64 *banks = vcpu->arch.mce_banks;
3044
3045 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3046 return -EINVAL;
3047 /*
3048 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3049 * reporting is disabled
3050 */
3051 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3052 vcpu->arch.mcg_ctl != ~(u64)0)
3053 return 0;
3054 banks += 4 * mce->bank;
3055 /*
3056 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3057 * reporting is disabled for the bank
3058 */
3059 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3060 return 0;
3061 if (mce->status & MCI_STATUS_UC) {
3062 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3063 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3064 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3065 return 0;
3066 }
3067 if (banks[1] & MCI_STATUS_VAL)
3068 mce->status |= MCI_STATUS_OVER;
3069 banks[2] = mce->addr;
3070 banks[3] = mce->misc;
3071 vcpu->arch.mcg_status = mce->mcg_status;
3072 banks[1] = mce->status;
3073 kvm_queue_exception(vcpu, MC_VECTOR);
3074 } else if (!(banks[1] & MCI_STATUS_VAL)
3075 || !(banks[1] & MCI_STATUS_UC)) {
3076 if (banks[1] & MCI_STATUS_VAL)
3077 mce->status |= MCI_STATUS_OVER;
3078 banks[2] = mce->addr;
3079 banks[3] = mce->misc;
3080 banks[1] = mce->status;
3081 } else
3082 banks[1] |= MCI_STATUS_OVER;
3083 return 0;
3084 }
3085
3086 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3087 struct kvm_vcpu_events *events)
3088 {
3089 process_nmi(vcpu);
3090 events->exception.injected =
3091 vcpu->arch.exception.pending &&
3092 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3093 events->exception.nr = vcpu->arch.exception.nr;
3094 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3095 events->exception.pad = 0;
3096 events->exception.error_code = vcpu->arch.exception.error_code;
3097
3098 events->interrupt.injected =
3099 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3100 events->interrupt.nr = vcpu->arch.interrupt.nr;
3101 events->interrupt.soft = 0;
3102 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3103
3104 events->nmi.injected = vcpu->arch.nmi_injected;
3105 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3106 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3107 events->nmi.pad = 0;
3108
3109 events->sipi_vector = 0; /* never valid when reporting to user space */
3110
3111 events->smi.smm = is_smm(vcpu);
3112 events->smi.pending = vcpu->arch.smi_pending;
3113 events->smi.smm_inside_nmi =
3114 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3115 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3116
3117 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3118 | KVM_VCPUEVENT_VALID_SHADOW
3119 | KVM_VCPUEVENT_VALID_SMM);
3120 memset(&events->reserved, 0, sizeof(events->reserved));
3121 }
3122
3123 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3124
3125 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3126 struct kvm_vcpu_events *events)
3127 {
3128 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3129 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3130 | KVM_VCPUEVENT_VALID_SHADOW
3131 | KVM_VCPUEVENT_VALID_SMM))
3132 return -EINVAL;
3133
3134 if (events->exception.injected &&
3135 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3136 return -EINVAL;
3137
3138 /* INITs are latched while in SMM */
3139 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3140 (events->smi.smm || events->smi.pending) &&
3141 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3142 return -EINVAL;
3143
3144 process_nmi(vcpu);
3145 vcpu->arch.exception.pending = events->exception.injected;
3146 vcpu->arch.exception.nr = events->exception.nr;
3147 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3148 vcpu->arch.exception.error_code = events->exception.error_code;
3149
3150 vcpu->arch.interrupt.pending = events->interrupt.injected;
3151 vcpu->arch.interrupt.nr = events->interrupt.nr;
3152 vcpu->arch.interrupt.soft = events->interrupt.soft;
3153 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3154 kvm_x86_ops->set_interrupt_shadow(vcpu,
3155 events->interrupt.shadow);
3156
3157 vcpu->arch.nmi_injected = events->nmi.injected;
3158 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3159 vcpu->arch.nmi_pending = events->nmi.pending;
3160 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3161
3162 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3163 lapic_in_kernel(vcpu))
3164 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3165
3166 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3167 u32 hflags = vcpu->arch.hflags;
3168 if (events->smi.smm)
3169 hflags |= HF_SMM_MASK;
3170 else
3171 hflags &= ~HF_SMM_MASK;
3172 kvm_set_hflags(vcpu, hflags);
3173
3174 vcpu->arch.smi_pending = events->smi.pending;
3175 if (events->smi.smm_inside_nmi)
3176 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3177 else
3178 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3179 if (lapic_in_kernel(vcpu)) {
3180 if (events->smi.latched_init)
3181 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3182 else
3183 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3184 }
3185 }
3186
3187 kvm_make_request(KVM_REQ_EVENT, vcpu);
3188
3189 return 0;
3190 }
3191
3192 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3193 struct kvm_debugregs *dbgregs)
3194 {
3195 unsigned long val;
3196
3197 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3198 kvm_get_dr(vcpu, 6, &val);
3199 dbgregs->dr6 = val;
3200 dbgregs->dr7 = vcpu->arch.dr7;
3201 dbgregs->flags = 0;
3202 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3203 }
3204
3205 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3206 struct kvm_debugregs *dbgregs)
3207 {
3208 if (dbgregs->flags)
3209 return -EINVAL;
3210
3211 if (dbgregs->dr6 & ~0xffffffffull)
3212 return -EINVAL;
3213 if (dbgregs->dr7 & ~0xffffffffull)
3214 return -EINVAL;
3215
3216 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3217 kvm_update_dr0123(vcpu);
3218 vcpu->arch.dr6 = dbgregs->dr6;
3219 kvm_update_dr6(vcpu);
3220 vcpu->arch.dr7 = dbgregs->dr7;
3221 kvm_update_dr7(vcpu);
3222
3223 return 0;
3224 }
3225
3226 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3227
3228 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3229 {
3230 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3231 u64 xstate_bv = xsave->header.xfeatures;
3232 u64 valid;
3233
3234 /*
3235 * Copy legacy XSAVE area, to avoid complications with CPUID
3236 * leaves 0 and 1 in the loop below.
3237 */
3238 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3239
3240 /* Set XSTATE_BV */
3241 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3242 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3243
3244 /*
3245 * Copy each region from the possibly compacted offset to the
3246 * non-compacted offset.
3247 */
3248 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3249 while (valid) {
3250 u64 feature = valid & -valid;
3251 int index = fls64(feature) - 1;
3252 void *src = get_xsave_addr(xsave, feature);
3253
3254 if (src) {
3255 u32 size, offset, ecx, edx;
3256 cpuid_count(XSTATE_CPUID, index,
3257 &size, &offset, &ecx, &edx);
3258 memcpy(dest + offset, src, size);
3259 }
3260
3261 valid -= feature;
3262 }
3263 }
3264
3265 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3266 {
3267 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3268 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3269 u64 valid;
3270
3271 /*
3272 * Copy legacy XSAVE area, to avoid complications with CPUID
3273 * leaves 0 and 1 in the loop below.
3274 */
3275 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3276
3277 /* Set XSTATE_BV and possibly XCOMP_BV. */
3278 xsave->header.xfeatures = xstate_bv;
3279 if (boot_cpu_has(X86_FEATURE_XSAVES))
3280 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3281
3282 /*
3283 * Copy each region from the non-compacted offset to the
3284 * possibly compacted offset.
3285 */
3286 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3287 while (valid) {
3288 u64 feature = valid & -valid;
3289 int index = fls64(feature) - 1;
3290 void *dest = get_xsave_addr(xsave, feature);
3291
3292 if (dest) {
3293 u32 size, offset, ecx, edx;
3294 cpuid_count(XSTATE_CPUID, index,
3295 &size, &offset, &ecx, &edx);
3296 memcpy(dest, src + offset, size);
3297 }
3298
3299 valid -= feature;
3300 }
3301 }
3302
3303 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3304 struct kvm_xsave *guest_xsave)
3305 {
3306 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3307 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3308 fill_xsave((u8 *) guest_xsave->region, vcpu);
3309 } else {
3310 memcpy(guest_xsave->region,
3311 &vcpu->arch.guest_fpu.state.fxsave,
3312 sizeof(struct fxregs_state));
3313 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3314 XFEATURE_MASK_FPSSE;
3315 }
3316 }
3317
3318 #define XSAVE_MXCSR_OFFSET 24
3319
3320 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3321 struct kvm_xsave *guest_xsave)
3322 {
3323 u64 xstate_bv =
3324 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3325 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3326
3327 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3328 /*
3329 * Here we allow setting states that are not present in
3330 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3331 * with old userspace.
3332 */
3333 if (xstate_bv & ~kvm_supported_xcr0() ||
3334 mxcsr & ~mxcsr_feature_mask)
3335 return -EINVAL;
3336 load_xsave(vcpu, (u8 *)guest_xsave->region);
3337 } else {
3338 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3339 mxcsr & ~mxcsr_feature_mask)
3340 return -EINVAL;
3341 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3342 guest_xsave->region, sizeof(struct fxregs_state));
3343 }
3344 return 0;
3345 }
3346
3347 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3348 struct kvm_xcrs *guest_xcrs)
3349 {
3350 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3351 guest_xcrs->nr_xcrs = 0;
3352 return;
3353 }
3354
3355 guest_xcrs->nr_xcrs = 1;
3356 guest_xcrs->flags = 0;
3357 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3358 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3359 }
3360
3361 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3362 struct kvm_xcrs *guest_xcrs)
3363 {
3364 int i, r = 0;
3365
3366 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3367 return -EINVAL;
3368
3369 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3370 return -EINVAL;
3371
3372 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3373 /* Only support XCR0 currently */
3374 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3375 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3376 guest_xcrs->xcrs[i].value);
3377 break;
3378 }
3379 if (r)
3380 r = -EINVAL;
3381 return r;
3382 }
3383
3384 /*
3385 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3386 * stopped by the hypervisor. This function will be called from the host only.
3387 * EINVAL is returned when the host attempts to set the flag for a guest that
3388 * does not support pv clocks.
3389 */
3390 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3391 {
3392 if (!vcpu->arch.pv_time_enabled)
3393 return -EINVAL;
3394 vcpu->arch.pvclock_set_guest_stopped_request = true;
3395 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3396 return 0;
3397 }
3398
3399 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3400 struct kvm_enable_cap *cap)
3401 {
3402 if (cap->flags)
3403 return -EINVAL;
3404
3405 switch (cap->cap) {
3406 case KVM_CAP_HYPERV_SYNIC:
3407 if (!irqchip_in_kernel(vcpu->kvm))
3408 return -EINVAL;
3409 return kvm_hv_activate_synic(vcpu);
3410 default:
3411 return -EINVAL;
3412 }
3413 }
3414
3415 long kvm_arch_vcpu_ioctl(struct file *filp,
3416 unsigned int ioctl, unsigned long arg)
3417 {
3418 struct kvm_vcpu *vcpu = filp->private_data;
3419 void __user *argp = (void __user *)arg;
3420 int r;
3421 union {
3422 struct kvm_lapic_state *lapic;
3423 struct kvm_xsave *xsave;
3424 struct kvm_xcrs *xcrs;
3425 void *buffer;
3426 } u;
3427
3428 u.buffer = NULL;
3429 switch (ioctl) {
3430 case KVM_GET_LAPIC: {
3431 r = -EINVAL;
3432 if (!lapic_in_kernel(vcpu))
3433 goto out;
3434 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3435
3436 r = -ENOMEM;
3437 if (!u.lapic)
3438 goto out;
3439 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3440 if (r)
3441 goto out;
3442 r = -EFAULT;
3443 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3444 goto out;
3445 r = 0;
3446 break;
3447 }
3448 case KVM_SET_LAPIC: {
3449 r = -EINVAL;
3450 if (!lapic_in_kernel(vcpu))
3451 goto out;
3452 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3453 if (IS_ERR(u.lapic))
3454 return PTR_ERR(u.lapic);
3455
3456 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3457 break;
3458 }
3459 case KVM_INTERRUPT: {
3460 struct kvm_interrupt irq;
3461
3462 r = -EFAULT;
3463 if (copy_from_user(&irq, argp, sizeof irq))
3464 goto out;
3465 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3466 break;
3467 }
3468 case KVM_NMI: {
3469 r = kvm_vcpu_ioctl_nmi(vcpu);
3470 break;
3471 }
3472 case KVM_SMI: {
3473 r = kvm_vcpu_ioctl_smi(vcpu);
3474 break;
3475 }
3476 case KVM_SET_CPUID: {
3477 struct kvm_cpuid __user *cpuid_arg = argp;
3478 struct kvm_cpuid cpuid;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3482 goto out;
3483 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3484 break;
3485 }
3486 case KVM_SET_CPUID2: {
3487 struct kvm_cpuid2 __user *cpuid_arg = argp;
3488 struct kvm_cpuid2 cpuid;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3492 goto out;
3493 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3494 cpuid_arg->entries);
3495 break;
3496 }
3497 case KVM_GET_CPUID2: {
3498 struct kvm_cpuid2 __user *cpuid_arg = argp;
3499 struct kvm_cpuid2 cpuid;
3500
3501 r = -EFAULT;
3502 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3503 goto out;
3504 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3505 cpuid_arg->entries);
3506 if (r)
3507 goto out;
3508 r = -EFAULT;
3509 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3510 goto out;
3511 r = 0;
3512 break;
3513 }
3514 case KVM_GET_MSRS:
3515 r = msr_io(vcpu, argp, do_get_msr, 1);
3516 break;
3517 case KVM_SET_MSRS:
3518 r = msr_io(vcpu, argp, do_set_msr, 0);
3519 break;
3520 case KVM_TPR_ACCESS_REPORTING: {
3521 struct kvm_tpr_access_ctl tac;
3522
3523 r = -EFAULT;
3524 if (copy_from_user(&tac, argp, sizeof tac))
3525 goto out;
3526 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3527 if (r)
3528 goto out;
3529 r = -EFAULT;
3530 if (copy_to_user(argp, &tac, sizeof tac))
3531 goto out;
3532 r = 0;
3533 break;
3534 };
3535 case KVM_SET_VAPIC_ADDR: {
3536 struct kvm_vapic_addr va;
3537 int idx;
3538
3539 r = -EINVAL;
3540 if (!lapic_in_kernel(vcpu))
3541 goto out;
3542 r = -EFAULT;
3543 if (copy_from_user(&va, argp, sizeof va))
3544 goto out;
3545 idx = srcu_read_lock(&vcpu->kvm->srcu);
3546 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3547 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3548 break;
3549 }
3550 case KVM_X86_SETUP_MCE: {
3551 u64 mcg_cap;
3552
3553 r = -EFAULT;
3554 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3555 goto out;
3556 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3557 break;
3558 }
3559 case KVM_X86_SET_MCE: {
3560 struct kvm_x86_mce mce;
3561
3562 r = -EFAULT;
3563 if (copy_from_user(&mce, argp, sizeof mce))
3564 goto out;
3565 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3566 break;
3567 }
3568 case KVM_GET_VCPU_EVENTS: {
3569 struct kvm_vcpu_events events;
3570
3571 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3572
3573 r = -EFAULT;
3574 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3575 break;
3576 r = 0;
3577 break;
3578 }
3579 case KVM_SET_VCPU_EVENTS: {
3580 struct kvm_vcpu_events events;
3581
3582 r = -EFAULT;
3583 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3584 break;
3585
3586 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3587 break;
3588 }
3589 case KVM_GET_DEBUGREGS: {
3590 struct kvm_debugregs dbgregs;
3591
3592 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3593
3594 r = -EFAULT;
3595 if (copy_to_user(argp, &dbgregs,
3596 sizeof(struct kvm_debugregs)))
3597 break;
3598 r = 0;
3599 break;
3600 }
3601 case KVM_SET_DEBUGREGS: {
3602 struct kvm_debugregs dbgregs;
3603
3604 r = -EFAULT;
3605 if (copy_from_user(&dbgregs, argp,
3606 sizeof(struct kvm_debugregs)))
3607 break;
3608
3609 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3610 break;
3611 }
3612 case KVM_GET_XSAVE: {
3613 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3614 r = -ENOMEM;
3615 if (!u.xsave)
3616 break;
3617
3618 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3619
3620 r = -EFAULT;
3621 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3622 break;
3623 r = 0;
3624 break;
3625 }
3626 case KVM_SET_XSAVE: {
3627 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3628 if (IS_ERR(u.xsave))
3629 return PTR_ERR(u.xsave);
3630
3631 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3632 break;
3633 }
3634 case KVM_GET_XCRS: {
3635 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3636 r = -ENOMEM;
3637 if (!u.xcrs)
3638 break;
3639
3640 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3641
3642 r = -EFAULT;
3643 if (copy_to_user(argp, u.xcrs,
3644 sizeof(struct kvm_xcrs)))
3645 break;
3646 r = 0;
3647 break;
3648 }
3649 case KVM_SET_XCRS: {
3650 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3651 if (IS_ERR(u.xcrs))
3652 return PTR_ERR(u.xcrs);
3653
3654 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3655 break;
3656 }
3657 case KVM_SET_TSC_KHZ: {
3658 u32 user_tsc_khz;
3659
3660 r = -EINVAL;
3661 user_tsc_khz = (u32)arg;
3662
3663 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3664 goto out;
3665
3666 if (user_tsc_khz == 0)
3667 user_tsc_khz = tsc_khz;
3668
3669 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3670 r = 0;
3671
3672 goto out;
3673 }
3674 case KVM_GET_TSC_KHZ: {
3675 r = vcpu->arch.virtual_tsc_khz;
3676 goto out;
3677 }
3678 case KVM_KVMCLOCK_CTRL: {
3679 r = kvm_set_guest_paused(vcpu);
3680 goto out;
3681 }
3682 case KVM_ENABLE_CAP: {
3683 struct kvm_enable_cap cap;
3684
3685 r = -EFAULT;
3686 if (copy_from_user(&cap, argp, sizeof(cap)))
3687 goto out;
3688 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3689 break;
3690 }
3691 default:
3692 r = -EINVAL;
3693 }
3694 out:
3695 kfree(u.buffer);
3696 return r;
3697 }
3698
3699 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3700 {
3701 return VM_FAULT_SIGBUS;
3702 }
3703
3704 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3705 {
3706 int ret;
3707
3708 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3709 return -EINVAL;
3710 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3711 return ret;
3712 }
3713
3714 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3715 u64 ident_addr)
3716 {
3717 kvm->arch.ept_identity_map_addr = ident_addr;
3718 return 0;
3719 }
3720
3721 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3722 u32 kvm_nr_mmu_pages)
3723 {
3724 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3725 return -EINVAL;
3726
3727 mutex_lock(&kvm->slots_lock);
3728
3729 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3730 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3731
3732 mutex_unlock(&kvm->slots_lock);
3733 return 0;
3734 }
3735
3736 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3737 {
3738 return kvm->arch.n_max_mmu_pages;
3739 }
3740
3741 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3742 {
3743 int r;
3744
3745 r = 0;
3746 switch (chip->chip_id) {
3747 case KVM_IRQCHIP_PIC_MASTER:
3748 memcpy(&chip->chip.pic,
3749 &pic_irqchip(kvm)->pics[0],
3750 sizeof(struct kvm_pic_state));
3751 break;
3752 case KVM_IRQCHIP_PIC_SLAVE:
3753 memcpy(&chip->chip.pic,
3754 &pic_irqchip(kvm)->pics[1],
3755 sizeof(struct kvm_pic_state));
3756 break;
3757 case KVM_IRQCHIP_IOAPIC:
3758 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3759 break;
3760 default:
3761 r = -EINVAL;
3762 break;
3763 }
3764 return r;
3765 }
3766
3767 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3768 {
3769 int r;
3770
3771 r = 0;
3772 switch (chip->chip_id) {
3773 case KVM_IRQCHIP_PIC_MASTER:
3774 spin_lock(&pic_irqchip(kvm)->lock);
3775 memcpy(&pic_irqchip(kvm)->pics[0],
3776 &chip->chip.pic,
3777 sizeof(struct kvm_pic_state));
3778 spin_unlock(&pic_irqchip(kvm)->lock);
3779 break;
3780 case KVM_IRQCHIP_PIC_SLAVE:
3781 spin_lock(&pic_irqchip(kvm)->lock);
3782 memcpy(&pic_irqchip(kvm)->pics[1],
3783 &chip->chip.pic,
3784 sizeof(struct kvm_pic_state));
3785 spin_unlock(&pic_irqchip(kvm)->lock);
3786 break;
3787 case KVM_IRQCHIP_IOAPIC:
3788 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3789 break;
3790 default:
3791 r = -EINVAL;
3792 break;
3793 }
3794 kvm_pic_update_irq(pic_irqchip(kvm));
3795 return r;
3796 }
3797
3798 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3799 {
3800 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3801
3802 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3803
3804 mutex_lock(&kps->lock);
3805 memcpy(ps, &kps->channels, sizeof(*ps));
3806 mutex_unlock(&kps->lock);
3807 return 0;
3808 }
3809
3810 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3811 {
3812 int i;
3813 struct kvm_pit *pit = kvm->arch.vpit;
3814
3815 mutex_lock(&pit->pit_state.lock);
3816 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3817 for (i = 0; i < 3; i++)
3818 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3819 mutex_unlock(&pit->pit_state.lock);
3820 return 0;
3821 }
3822
3823 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3824 {
3825 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3826 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3827 sizeof(ps->channels));
3828 ps->flags = kvm->arch.vpit->pit_state.flags;
3829 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3830 memset(&ps->reserved, 0, sizeof(ps->reserved));
3831 return 0;
3832 }
3833
3834 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3835 {
3836 int start = 0;
3837 int i;
3838 u32 prev_legacy, cur_legacy;
3839 struct kvm_pit *pit = kvm->arch.vpit;
3840
3841 mutex_lock(&pit->pit_state.lock);
3842 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3843 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3844 if (!prev_legacy && cur_legacy)
3845 start = 1;
3846 memcpy(&pit->pit_state.channels, &ps->channels,
3847 sizeof(pit->pit_state.channels));
3848 pit->pit_state.flags = ps->flags;
3849 for (i = 0; i < 3; i++)
3850 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3851 start && i == 0);
3852 mutex_unlock(&pit->pit_state.lock);
3853 return 0;
3854 }
3855
3856 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3857 struct kvm_reinject_control *control)
3858 {
3859 struct kvm_pit *pit = kvm->arch.vpit;
3860
3861 if (!pit)
3862 return -ENXIO;
3863
3864 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3865 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3866 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3867 */
3868 mutex_lock(&pit->pit_state.lock);
3869 kvm_pit_set_reinject(pit, control->pit_reinject);
3870 mutex_unlock(&pit->pit_state.lock);
3871
3872 return 0;
3873 }
3874
3875 /**
3876 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3877 * @kvm: kvm instance
3878 * @log: slot id and address to which we copy the log
3879 *
3880 * Steps 1-4 below provide general overview of dirty page logging. See
3881 * kvm_get_dirty_log_protect() function description for additional details.
3882 *
3883 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3884 * always flush the TLB (step 4) even if previous step failed and the dirty
3885 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3886 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3887 * writes will be marked dirty for next log read.
3888 *
3889 * 1. Take a snapshot of the bit and clear it if needed.
3890 * 2. Write protect the corresponding page.
3891 * 3. Copy the snapshot to the userspace.
3892 * 4. Flush TLB's if needed.
3893 */
3894 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3895 {
3896 bool is_dirty = false;
3897 int r;
3898
3899 mutex_lock(&kvm->slots_lock);
3900
3901 /*
3902 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3903 */
3904 if (kvm_x86_ops->flush_log_dirty)
3905 kvm_x86_ops->flush_log_dirty(kvm);
3906
3907 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3908
3909 /*
3910 * All the TLBs can be flushed out of mmu lock, see the comments in
3911 * kvm_mmu_slot_remove_write_access().
3912 */
3913 lockdep_assert_held(&kvm->slots_lock);
3914 if (is_dirty)
3915 kvm_flush_remote_tlbs(kvm);
3916
3917 mutex_unlock(&kvm->slots_lock);
3918 return r;
3919 }
3920
3921 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3922 bool line_status)
3923 {
3924 if (!irqchip_in_kernel(kvm))
3925 return -ENXIO;
3926
3927 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3928 irq_event->irq, irq_event->level,
3929 line_status);
3930 return 0;
3931 }
3932
3933 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3934 struct kvm_enable_cap *cap)
3935 {
3936 int r;
3937
3938 if (cap->flags)
3939 return -EINVAL;
3940
3941 switch (cap->cap) {
3942 case KVM_CAP_DISABLE_QUIRKS:
3943 kvm->arch.disabled_quirks = cap->args[0];
3944 r = 0;
3945 break;
3946 case KVM_CAP_SPLIT_IRQCHIP: {
3947 mutex_lock(&kvm->lock);
3948 r = -EINVAL;
3949 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3950 goto split_irqchip_unlock;
3951 r = -EEXIST;
3952 if (irqchip_in_kernel(kvm))
3953 goto split_irqchip_unlock;
3954 if (kvm->created_vcpus)
3955 goto split_irqchip_unlock;
3956 r = kvm_setup_empty_irq_routing(kvm);
3957 if (r)
3958 goto split_irqchip_unlock;
3959 /* Pairs with irqchip_in_kernel. */
3960 smp_wmb();
3961 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3962 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3963 r = 0;
3964 split_irqchip_unlock:
3965 mutex_unlock(&kvm->lock);
3966 break;
3967 }
3968 case KVM_CAP_X2APIC_API:
3969 r = -EINVAL;
3970 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3971 break;
3972
3973 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3974 kvm->arch.x2apic_format = true;
3975 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3976 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3977
3978 r = 0;
3979 break;
3980 default:
3981 r = -EINVAL;
3982 break;
3983 }
3984 return r;
3985 }
3986
3987 long kvm_arch_vm_ioctl(struct file *filp,
3988 unsigned int ioctl, unsigned long arg)
3989 {
3990 struct kvm *kvm = filp->private_data;
3991 void __user *argp = (void __user *)arg;
3992 int r = -ENOTTY;
3993 /*
3994 * This union makes it completely explicit to gcc-3.x
3995 * that these two variables' stack usage should be
3996 * combined, not added together.
3997 */
3998 union {
3999 struct kvm_pit_state ps;
4000 struct kvm_pit_state2 ps2;
4001 struct kvm_pit_config pit_config;
4002 } u;
4003
4004 switch (ioctl) {
4005 case KVM_SET_TSS_ADDR:
4006 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4007 break;
4008 case KVM_SET_IDENTITY_MAP_ADDR: {
4009 u64 ident_addr;
4010
4011 r = -EFAULT;
4012 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4013 goto out;
4014 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4015 break;
4016 }
4017 case KVM_SET_NR_MMU_PAGES:
4018 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4019 break;
4020 case KVM_GET_NR_MMU_PAGES:
4021 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4022 break;
4023 case KVM_CREATE_IRQCHIP: {
4024 mutex_lock(&kvm->lock);
4025
4026 r = -EEXIST;
4027 if (irqchip_in_kernel(kvm))
4028 goto create_irqchip_unlock;
4029
4030 r = -EINVAL;
4031 if (kvm->created_vcpus)
4032 goto create_irqchip_unlock;
4033
4034 r = kvm_pic_init(kvm);
4035 if (r)
4036 goto create_irqchip_unlock;
4037
4038 r = kvm_ioapic_init(kvm);
4039 if (r) {
4040 mutex_lock(&kvm->slots_lock);
4041 kvm_pic_destroy(kvm);
4042 mutex_unlock(&kvm->slots_lock);
4043 goto create_irqchip_unlock;
4044 }
4045
4046 r = kvm_setup_default_irq_routing(kvm);
4047 if (r) {
4048 mutex_lock(&kvm->slots_lock);
4049 mutex_lock(&kvm->irq_lock);
4050 kvm_ioapic_destroy(kvm);
4051 kvm_pic_destroy(kvm);
4052 mutex_unlock(&kvm->irq_lock);
4053 mutex_unlock(&kvm->slots_lock);
4054 goto create_irqchip_unlock;
4055 }
4056 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4057 smp_wmb();
4058 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4059 create_irqchip_unlock:
4060 mutex_unlock(&kvm->lock);
4061 break;
4062 }
4063 case KVM_CREATE_PIT:
4064 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4065 goto create_pit;
4066 case KVM_CREATE_PIT2:
4067 r = -EFAULT;
4068 if (copy_from_user(&u.pit_config, argp,
4069 sizeof(struct kvm_pit_config)))
4070 goto out;
4071 create_pit:
4072 mutex_lock(&kvm->lock);
4073 r = -EEXIST;
4074 if (kvm->arch.vpit)
4075 goto create_pit_unlock;
4076 r = -ENOMEM;
4077 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4078 if (kvm->arch.vpit)
4079 r = 0;
4080 create_pit_unlock:
4081 mutex_unlock(&kvm->lock);
4082 break;
4083 case KVM_GET_IRQCHIP: {
4084 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4085 struct kvm_irqchip *chip;
4086
4087 chip = memdup_user(argp, sizeof(*chip));
4088 if (IS_ERR(chip)) {
4089 r = PTR_ERR(chip);
4090 goto out;
4091 }
4092
4093 r = -ENXIO;
4094 if (!irqchip_kernel(kvm))
4095 goto get_irqchip_out;
4096 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4097 if (r)
4098 goto get_irqchip_out;
4099 r = -EFAULT;
4100 if (copy_to_user(argp, chip, sizeof *chip))
4101 goto get_irqchip_out;
4102 r = 0;
4103 get_irqchip_out:
4104 kfree(chip);
4105 break;
4106 }
4107 case KVM_SET_IRQCHIP: {
4108 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4109 struct kvm_irqchip *chip;
4110
4111 chip = memdup_user(argp, sizeof(*chip));
4112 if (IS_ERR(chip)) {
4113 r = PTR_ERR(chip);
4114 goto out;
4115 }
4116
4117 r = -ENXIO;
4118 if (!irqchip_kernel(kvm))
4119 goto set_irqchip_out;
4120 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4121 if (r)
4122 goto set_irqchip_out;
4123 r = 0;
4124 set_irqchip_out:
4125 kfree(chip);
4126 break;
4127 }
4128 case KVM_GET_PIT: {
4129 r = -EFAULT;
4130 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4131 goto out;
4132 r = -ENXIO;
4133 if (!kvm->arch.vpit)
4134 goto out;
4135 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4136 if (r)
4137 goto out;
4138 r = -EFAULT;
4139 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4140 goto out;
4141 r = 0;
4142 break;
4143 }
4144 case KVM_SET_PIT: {
4145 r = -EFAULT;
4146 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4147 goto out;
4148 r = -ENXIO;
4149 if (!kvm->arch.vpit)
4150 goto out;
4151 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4152 break;
4153 }
4154 case KVM_GET_PIT2: {
4155 r = -ENXIO;
4156 if (!kvm->arch.vpit)
4157 goto out;
4158 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4159 if (r)
4160 goto out;
4161 r = -EFAULT;
4162 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4163 goto out;
4164 r = 0;
4165 break;
4166 }
4167 case KVM_SET_PIT2: {
4168 r = -EFAULT;
4169 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4170 goto out;
4171 r = -ENXIO;
4172 if (!kvm->arch.vpit)
4173 goto out;
4174 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4175 break;
4176 }
4177 case KVM_REINJECT_CONTROL: {
4178 struct kvm_reinject_control control;
4179 r = -EFAULT;
4180 if (copy_from_user(&control, argp, sizeof(control)))
4181 goto out;
4182 r = kvm_vm_ioctl_reinject(kvm, &control);
4183 break;
4184 }
4185 case KVM_SET_BOOT_CPU_ID:
4186 r = 0;
4187 mutex_lock(&kvm->lock);
4188 if (kvm->created_vcpus)
4189 r = -EBUSY;
4190 else
4191 kvm->arch.bsp_vcpu_id = arg;
4192 mutex_unlock(&kvm->lock);
4193 break;
4194 case KVM_XEN_HVM_CONFIG: {
4195 r = -EFAULT;
4196 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4197 sizeof(struct kvm_xen_hvm_config)))
4198 goto out;
4199 r = -EINVAL;
4200 if (kvm->arch.xen_hvm_config.flags)
4201 goto out;
4202 r = 0;
4203 break;
4204 }
4205 case KVM_SET_CLOCK: {
4206 struct kvm_clock_data user_ns;
4207 u64 now_ns;
4208
4209 r = -EFAULT;
4210 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4211 goto out;
4212
4213 r = -EINVAL;
4214 if (user_ns.flags)
4215 goto out;
4216
4217 r = 0;
4218 local_irq_disable();
4219 now_ns = __get_kvmclock_ns(kvm);
4220 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4221 local_irq_enable();
4222 kvm_gen_update_masterclock(kvm);
4223 break;
4224 }
4225 case KVM_GET_CLOCK: {
4226 struct kvm_clock_data user_ns;
4227 u64 now_ns;
4228
4229 local_irq_disable();
4230 now_ns = __get_kvmclock_ns(kvm);
4231 user_ns.clock = now_ns;
4232 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4233 local_irq_enable();
4234 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4235
4236 r = -EFAULT;
4237 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4238 goto out;
4239 r = 0;
4240 break;
4241 }
4242 case KVM_ENABLE_CAP: {
4243 struct kvm_enable_cap cap;
4244
4245 r = -EFAULT;
4246 if (copy_from_user(&cap, argp, sizeof(cap)))
4247 goto out;
4248 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4249 break;
4250 }
4251 default:
4252 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4253 }
4254 out:
4255 return r;
4256 }
4257
4258 static void kvm_init_msr_list(void)
4259 {
4260 u32 dummy[2];
4261 unsigned i, j;
4262
4263 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4264 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4265 continue;
4266
4267 /*
4268 * Even MSRs that are valid in the host may not be exposed
4269 * to the guests in some cases.
4270 */
4271 switch (msrs_to_save[i]) {
4272 case MSR_IA32_BNDCFGS:
4273 if (!kvm_x86_ops->mpx_supported())
4274 continue;
4275 break;
4276 case MSR_TSC_AUX:
4277 if (!kvm_x86_ops->rdtscp_supported())
4278 continue;
4279 break;
4280 default:
4281 break;
4282 }
4283
4284 if (j < i)
4285 msrs_to_save[j] = msrs_to_save[i];
4286 j++;
4287 }
4288 num_msrs_to_save = j;
4289
4290 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4291 switch (emulated_msrs[i]) {
4292 case MSR_IA32_SMBASE:
4293 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4294 continue;
4295 break;
4296 default:
4297 break;
4298 }
4299
4300 if (j < i)
4301 emulated_msrs[j] = emulated_msrs[i];
4302 j++;
4303 }
4304 num_emulated_msrs = j;
4305 }
4306
4307 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4308 const void *v)
4309 {
4310 int handled = 0;
4311 int n;
4312
4313 do {
4314 n = min(len, 8);
4315 if (!(lapic_in_kernel(vcpu) &&
4316 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4317 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4318 break;
4319 handled += n;
4320 addr += n;
4321 len -= n;
4322 v += n;
4323 } while (len);
4324
4325 return handled;
4326 }
4327
4328 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4329 {
4330 int handled = 0;
4331 int n;
4332
4333 do {
4334 n = min(len, 8);
4335 if (!(lapic_in_kernel(vcpu) &&
4336 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4337 addr, n, v))
4338 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4339 break;
4340 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4341 handled += n;
4342 addr += n;
4343 len -= n;
4344 v += n;
4345 } while (len);
4346
4347 return handled;
4348 }
4349
4350 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4351 struct kvm_segment *var, int seg)
4352 {
4353 kvm_x86_ops->set_segment(vcpu, var, seg);
4354 }
4355
4356 void kvm_get_segment(struct kvm_vcpu *vcpu,
4357 struct kvm_segment *var, int seg)
4358 {
4359 kvm_x86_ops->get_segment(vcpu, var, seg);
4360 }
4361
4362 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4363 struct x86_exception *exception)
4364 {
4365 gpa_t t_gpa;
4366
4367 BUG_ON(!mmu_is_nested(vcpu));
4368
4369 /* NPT walks are always user-walks */
4370 access |= PFERR_USER_MASK;
4371 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4372
4373 return t_gpa;
4374 }
4375
4376 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4377 struct x86_exception *exception)
4378 {
4379 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4381 }
4382
4383 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4384 struct x86_exception *exception)
4385 {
4386 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4387 access |= PFERR_FETCH_MASK;
4388 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4389 }
4390
4391 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4392 struct x86_exception *exception)
4393 {
4394 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4395 access |= PFERR_WRITE_MASK;
4396 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4397 }
4398
4399 /* uses this to access any guest's mapped memory without checking CPL */
4400 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4401 struct x86_exception *exception)
4402 {
4403 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4404 }
4405
4406 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4407 struct kvm_vcpu *vcpu, u32 access,
4408 struct x86_exception *exception)
4409 {
4410 void *data = val;
4411 int r = X86EMUL_CONTINUE;
4412
4413 while (bytes) {
4414 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4415 exception);
4416 unsigned offset = addr & (PAGE_SIZE-1);
4417 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4418 int ret;
4419
4420 if (gpa == UNMAPPED_GVA)
4421 return X86EMUL_PROPAGATE_FAULT;
4422 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4423 offset, toread);
4424 if (ret < 0) {
4425 r = X86EMUL_IO_NEEDED;
4426 goto out;
4427 }
4428
4429 bytes -= toread;
4430 data += toread;
4431 addr += toread;
4432 }
4433 out:
4434 return r;
4435 }
4436
4437 /* used for instruction fetching */
4438 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4439 gva_t addr, void *val, unsigned int bytes,
4440 struct x86_exception *exception)
4441 {
4442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4443 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4444 unsigned offset;
4445 int ret;
4446
4447 /* Inline kvm_read_guest_virt_helper for speed. */
4448 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4449 exception);
4450 if (unlikely(gpa == UNMAPPED_GVA))
4451 return X86EMUL_PROPAGATE_FAULT;
4452
4453 offset = addr & (PAGE_SIZE-1);
4454 if (WARN_ON(offset + bytes > PAGE_SIZE))
4455 bytes = (unsigned)PAGE_SIZE - offset;
4456 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4457 offset, bytes);
4458 if (unlikely(ret < 0))
4459 return X86EMUL_IO_NEEDED;
4460
4461 return X86EMUL_CONTINUE;
4462 }
4463
4464 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4465 gva_t addr, void *val, unsigned int bytes,
4466 struct x86_exception *exception)
4467 {
4468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4469 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4470
4471 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4472 exception);
4473 }
4474 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4475
4476 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4477 gva_t addr, void *val, unsigned int bytes,
4478 struct x86_exception *exception)
4479 {
4480 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4481 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4482 }
4483
4484 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4485 unsigned long addr, void *val, unsigned int bytes)
4486 {
4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4488 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4489
4490 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4491 }
4492
4493 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4494 gva_t addr, void *val,
4495 unsigned int bytes,
4496 struct x86_exception *exception)
4497 {
4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4499 void *data = val;
4500 int r = X86EMUL_CONTINUE;
4501
4502 while (bytes) {
4503 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4504 PFERR_WRITE_MASK,
4505 exception);
4506 unsigned offset = addr & (PAGE_SIZE-1);
4507 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4508 int ret;
4509
4510 if (gpa == UNMAPPED_GVA)
4511 return X86EMUL_PROPAGATE_FAULT;
4512 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4513 if (ret < 0) {
4514 r = X86EMUL_IO_NEEDED;
4515 goto out;
4516 }
4517
4518 bytes -= towrite;
4519 data += towrite;
4520 addr += towrite;
4521 }
4522 out:
4523 return r;
4524 }
4525 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4526
4527 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4528 gpa_t gpa, bool write)
4529 {
4530 /* For APIC access vmexit */
4531 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4532 return 1;
4533
4534 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4535 trace_vcpu_match_mmio(gva, gpa, write, true);
4536 return 1;
4537 }
4538
4539 return 0;
4540 }
4541
4542 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4543 gpa_t *gpa, struct x86_exception *exception,
4544 bool write)
4545 {
4546 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4547 | (write ? PFERR_WRITE_MASK : 0);
4548
4549 /*
4550 * currently PKRU is only applied to ept enabled guest so
4551 * there is no pkey in EPT page table for L1 guest or EPT
4552 * shadow page table for L2 guest.
4553 */
4554 if (vcpu_match_mmio_gva(vcpu, gva)
4555 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4556 vcpu->arch.access, 0, access)) {
4557 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4558 (gva & (PAGE_SIZE - 1));
4559 trace_vcpu_match_mmio(gva, *gpa, write, false);
4560 return 1;
4561 }
4562
4563 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4564
4565 if (*gpa == UNMAPPED_GVA)
4566 return -1;
4567
4568 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4569 }
4570
4571 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4572 const void *val, int bytes)
4573 {
4574 int ret;
4575
4576 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4577 if (ret < 0)
4578 return 0;
4579 kvm_page_track_write(vcpu, gpa, val, bytes);
4580 return 1;
4581 }
4582
4583 struct read_write_emulator_ops {
4584 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4585 int bytes);
4586 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4587 void *val, int bytes);
4588 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4589 int bytes, void *val);
4590 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4591 void *val, int bytes);
4592 bool write;
4593 };
4594
4595 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4596 {
4597 if (vcpu->mmio_read_completed) {
4598 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4599 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4600 vcpu->mmio_read_completed = 0;
4601 return 1;
4602 }
4603
4604 return 0;
4605 }
4606
4607 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4608 void *val, int bytes)
4609 {
4610 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4611 }
4612
4613 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4614 void *val, int bytes)
4615 {
4616 return emulator_write_phys(vcpu, gpa, val, bytes);
4617 }
4618
4619 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4620 {
4621 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4622 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4623 }
4624
4625 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4626 void *val, int bytes)
4627 {
4628 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4629 return X86EMUL_IO_NEEDED;
4630 }
4631
4632 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4633 void *val, int bytes)
4634 {
4635 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4636
4637 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4638 return X86EMUL_CONTINUE;
4639 }
4640
4641 static const struct read_write_emulator_ops read_emultor = {
4642 .read_write_prepare = read_prepare,
4643 .read_write_emulate = read_emulate,
4644 .read_write_mmio = vcpu_mmio_read,
4645 .read_write_exit_mmio = read_exit_mmio,
4646 };
4647
4648 static const struct read_write_emulator_ops write_emultor = {
4649 .read_write_emulate = write_emulate,
4650 .read_write_mmio = write_mmio,
4651 .read_write_exit_mmio = write_exit_mmio,
4652 .write = true,
4653 };
4654
4655 static int emulator_read_write_onepage(unsigned long addr, void *val,
4656 unsigned int bytes,
4657 struct x86_exception *exception,
4658 struct kvm_vcpu *vcpu,
4659 const struct read_write_emulator_ops *ops)
4660 {
4661 gpa_t gpa;
4662 int handled, ret;
4663 bool write = ops->write;
4664 struct kvm_mmio_fragment *frag;
4665 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4666
4667 /*
4668 * If the exit was due to a NPF we may already have a GPA.
4669 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4670 * Note, this cannot be used on string operations since string
4671 * operation using rep will only have the initial GPA from the NPF
4672 * occurred.
4673 */
4674 if (vcpu->arch.gpa_available &&
4675 emulator_can_use_gpa(ctxt) &&
4676 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4677 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4678 gpa = exception->address;
4679 goto mmio;
4680 }
4681
4682 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4683
4684 if (ret < 0)
4685 return X86EMUL_PROPAGATE_FAULT;
4686
4687 /* For APIC access vmexit */
4688 if (ret)
4689 goto mmio;
4690
4691 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4692 return X86EMUL_CONTINUE;
4693
4694 mmio:
4695 /*
4696 * Is this MMIO handled locally?
4697 */
4698 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4699 if (handled == bytes)
4700 return X86EMUL_CONTINUE;
4701
4702 gpa += handled;
4703 bytes -= handled;
4704 val += handled;
4705
4706 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4707 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4708 frag->gpa = gpa;
4709 frag->data = val;
4710 frag->len = bytes;
4711 return X86EMUL_CONTINUE;
4712 }
4713
4714 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4715 unsigned long addr,
4716 void *val, unsigned int bytes,
4717 struct x86_exception *exception,
4718 const struct read_write_emulator_ops *ops)
4719 {
4720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4721 gpa_t gpa;
4722 int rc;
4723
4724 if (ops->read_write_prepare &&
4725 ops->read_write_prepare(vcpu, val, bytes))
4726 return X86EMUL_CONTINUE;
4727
4728 vcpu->mmio_nr_fragments = 0;
4729
4730 /* Crossing a page boundary? */
4731 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4732 int now;
4733
4734 now = -addr & ~PAGE_MASK;
4735 rc = emulator_read_write_onepage(addr, val, now, exception,
4736 vcpu, ops);
4737
4738 if (rc != X86EMUL_CONTINUE)
4739 return rc;
4740 addr += now;
4741 if (ctxt->mode != X86EMUL_MODE_PROT64)
4742 addr = (u32)addr;
4743 val += now;
4744 bytes -= now;
4745 }
4746
4747 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4748 vcpu, ops);
4749 if (rc != X86EMUL_CONTINUE)
4750 return rc;
4751
4752 if (!vcpu->mmio_nr_fragments)
4753 return rc;
4754
4755 gpa = vcpu->mmio_fragments[0].gpa;
4756
4757 vcpu->mmio_needed = 1;
4758 vcpu->mmio_cur_fragment = 0;
4759
4760 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4761 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4762 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4763 vcpu->run->mmio.phys_addr = gpa;
4764
4765 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4766 }
4767
4768 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4769 unsigned long addr,
4770 void *val,
4771 unsigned int bytes,
4772 struct x86_exception *exception)
4773 {
4774 return emulator_read_write(ctxt, addr, val, bytes,
4775 exception, &read_emultor);
4776 }
4777
4778 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4779 unsigned long addr,
4780 const void *val,
4781 unsigned int bytes,
4782 struct x86_exception *exception)
4783 {
4784 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4785 exception, &write_emultor);
4786 }
4787
4788 #define CMPXCHG_TYPE(t, ptr, old, new) \
4789 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4790
4791 #ifdef CONFIG_X86_64
4792 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4793 #else
4794 # define CMPXCHG64(ptr, old, new) \
4795 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4796 #endif
4797
4798 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4799 unsigned long addr,
4800 const void *old,
4801 const void *new,
4802 unsigned int bytes,
4803 struct x86_exception *exception)
4804 {
4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4806 gpa_t gpa;
4807 struct page *page;
4808 char *kaddr;
4809 bool exchanged;
4810
4811 /* guests cmpxchg8b have to be emulated atomically */
4812 if (bytes > 8 || (bytes & (bytes - 1)))
4813 goto emul_write;
4814
4815 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4816
4817 if (gpa == UNMAPPED_GVA ||
4818 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4819 goto emul_write;
4820
4821 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4822 goto emul_write;
4823
4824 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4825 if (is_error_page(page))
4826 goto emul_write;
4827
4828 kaddr = kmap_atomic(page);
4829 kaddr += offset_in_page(gpa);
4830 switch (bytes) {
4831 case 1:
4832 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4833 break;
4834 case 2:
4835 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4836 break;
4837 case 4:
4838 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4839 break;
4840 case 8:
4841 exchanged = CMPXCHG64(kaddr, old, new);
4842 break;
4843 default:
4844 BUG();
4845 }
4846 kunmap_atomic(kaddr);
4847 kvm_release_page_dirty(page);
4848
4849 if (!exchanged)
4850 return X86EMUL_CMPXCHG_FAILED;
4851
4852 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4853 kvm_page_track_write(vcpu, gpa, new, bytes);
4854
4855 return X86EMUL_CONTINUE;
4856
4857 emul_write:
4858 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4859
4860 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4861 }
4862
4863 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4864 {
4865 int r = 0, i;
4866
4867 for (i = 0; i < vcpu->arch.pio.count; i++) {
4868 if (vcpu->arch.pio.in)
4869 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4870 vcpu->arch.pio.size, pd);
4871 else
4872 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4873 vcpu->arch.pio.port, vcpu->arch.pio.size,
4874 pd);
4875 if (r)
4876 break;
4877 pd += vcpu->arch.pio.size;
4878 }
4879 return r;
4880 }
4881
4882 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4883 unsigned short port, void *val,
4884 unsigned int count, bool in)
4885 {
4886 vcpu->arch.pio.port = port;
4887 vcpu->arch.pio.in = in;
4888 vcpu->arch.pio.count = count;
4889 vcpu->arch.pio.size = size;
4890
4891 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4892 vcpu->arch.pio.count = 0;
4893 return 1;
4894 }
4895
4896 vcpu->run->exit_reason = KVM_EXIT_IO;
4897 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4898 vcpu->run->io.size = size;
4899 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4900 vcpu->run->io.count = count;
4901 vcpu->run->io.port = port;
4902
4903 return 0;
4904 }
4905
4906 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4907 int size, unsigned short port, void *val,
4908 unsigned int count)
4909 {
4910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4911 int ret;
4912
4913 if (vcpu->arch.pio.count)
4914 goto data_avail;
4915
4916 memset(vcpu->arch.pio_data, 0, size * count);
4917
4918 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4919 if (ret) {
4920 data_avail:
4921 memcpy(val, vcpu->arch.pio_data, size * count);
4922 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4923 vcpu->arch.pio.count = 0;
4924 return 1;
4925 }
4926
4927 return 0;
4928 }
4929
4930 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4931 int size, unsigned short port,
4932 const void *val, unsigned int count)
4933 {
4934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4935
4936 memcpy(vcpu->arch.pio_data, val, size * count);
4937 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4938 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4939 }
4940
4941 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4942 {
4943 return kvm_x86_ops->get_segment_base(vcpu, seg);
4944 }
4945
4946 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4947 {
4948 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4949 }
4950
4951 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4952 {
4953 if (!need_emulate_wbinvd(vcpu))
4954 return X86EMUL_CONTINUE;
4955
4956 if (kvm_x86_ops->has_wbinvd_exit()) {
4957 int cpu = get_cpu();
4958
4959 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4960 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4961 wbinvd_ipi, NULL, 1);
4962 put_cpu();
4963 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4964 } else
4965 wbinvd();
4966 return X86EMUL_CONTINUE;
4967 }
4968
4969 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4970 {
4971 kvm_emulate_wbinvd_noskip(vcpu);
4972 return kvm_skip_emulated_instruction(vcpu);
4973 }
4974 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4975
4976
4977
4978 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4979 {
4980 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4981 }
4982
4983 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4984 unsigned long *dest)
4985 {
4986 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4987 }
4988
4989 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4990 unsigned long value)
4991 {
4992
4993 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4994 }
4995
4996 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4997 {
4998 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4999 }
5000
5001 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5002 {
5003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5004 unsigned long value;
5005
5006 switch (cr) {
5007 case 0:
5008 value = kvm_read_cr0(vcpu);
5009 break;
5010 case 2:
5011 value = vcpu->arch.cr2;
5012 break;
5013 case 3:
5014 value = kvm_read_cr3(vcpu);
5015 break;
5016 case 4:
5017 value = kvm_read_cr4(vcpu);
5018 break;
5019 case 8:
5020 value = kvm_get_cr8(vcpu);
5021 break;
5022 default:
5023 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5024 return 0;
5025 }
5026
5027 return value;
5028 }
5029
5030 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5031 {
5032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5033 int res = 0;
5034
5035 switch (cr) {
5036 case 0:
5037 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5038 break;
5039 case 2:
5040 vcpu->arch.cr2 = val;
5041 break;
5042 case 3:
5043 res = kvm_set_cr3(vcpu, val);
5044 break;
5045 case 4:
5046 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5047 break;
5048 case 8:
5049 res = kvm_set_cr8(vcpu, val);
5050 break;
5051 default:
5052 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5053 res = -1;
5054 }
5055
5056 return res;
5057 }
5058
5059 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5060 {
5061 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5062 }
5063
5064 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5065 {
5066 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5067 }
5068
5069 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5070 {
5071 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5072 }
5073
5074 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5075 {
5076 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5077 }
5078
5079 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5080 {
5081 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5082 }
5083
5084 static unsigned long emulator_get_cached_segment_base(
5085 struct x86_emulate_ctxt *ctxt, int seg)
5086 {
5087 return get_segment_base(emul_to_vcpu(ctxt), seg);
5088 }
5089
5090 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5091 struct desc_struct *desc, u32 *base3,
5092 int seg)
5093 {
5094 struct kvm_segment var;
5095
5096 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5097 *selector = var.selector;
5098
5099 if (var.unusable) {
5100 memset(desc, 0, sizeof(*desc));
5101 if (base3)
5102 *base3 = 0;
5103 return false;
5104 }
5105
5106 if (var.g)
5107 var.limit >>= 12;
5108 set_desc_limit(desc, var.limit);
5109 set_desc_base(desc, (unsigned long)var.base);
5110 #ifdef CONFIG_X86_64
5111 if (base3)
5112 *base3 = var.base >> 32;
5113 #endif
5114 desc->type = var.type;
5115 desc->s = var.s;
5116 desc->dpl = var.dpl;
5117 desc->p = var.present;
5118 desc->avl = var.avl;
5119 desc->l = var.l;
5120 desc->d = var.db;
5121 desc->g = var.g;
5122
5123 return true;
5124 }
5125
5126 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5127 struct desc_struct *desc, u32 base3,
5128 int seg)
5129 {
5130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5131 struct kvm_segment var;
5132
5133 var.selector = selector;
5134 var.base = get_desc_base(desc);
5135 #ifdef CONFIG_X86_64
5136 var.base |= ((u64)base3) << 32;
5137 #endif
5138 var.limit = get_desc_limit(desc);
5139 if (desc->g)
5140 var.limit = (var.limit << 12) | 0xfff;
5141 var.type = desc->type;
5142 var.dpl = desc->dpl;
5143 var.db = desc->d;
5144 var.s = desc->s;
5145 var.l = desc->l;
5146 var.g = desc->g;
5147 var.avl = desc->avl;
5148 var.present = desc->p;
5149 var.unusable = !var.present;
5150 var.padding = 0;
5151
5152 kvm_set_segment(vcpu, &var, seg);
5153 return;
5154 }
5155
5156 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5157 u32 msr_index, u64 *pdata)
5158 {
5159 struct msr_data msr;
5160 int r;
5161
5162 msr.index = msr_index;
5163 msr.host_initiated = false;
5164 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5165 if (r)
5166 return r;
5167
5168 *pdata = msr.data;
5169 return 0;
5170 }
5171
5172 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5173 u32 msr_index, u64 data)
5174 {
5175 struct msr_data msr;
5176
5177 msr.data = data;
5178 msr.index = msr_index;
5179 msr.host_initiated = false;
5180 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5181 }
5182
5183 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5184 {
5185 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5186
5187 return vcpu->arch.smbase;
5188 }
5189
5190 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5191 {
5192 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5193
5194 vcpu->arch.smbase = smbase;
5195 }
5196
5197 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5198 u32 pmc)
5199 {
5200 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5201 }
5202
5203 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5204 u32 pmc, u64 *pdata)
5205 {
5206 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5207 }
5208
5209 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5210 {
5211 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5212 }
5213
5214 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5215 {
5216 preempt_disable();
5217 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5218 }
5219
5220 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5221 {
5222 preempt_enable();
5223 }
5224
5225 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5226 struct x86_instruction_info *info,
5227 enum x86_intercept_stage stage)
5228 {
5229 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5230 }
5231
5232 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5233 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5234 {
5235 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5236 }
5237
5238 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5239 {
5240 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5241 }
5242
5243 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5244 {
5245 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5246 }
5247
5248 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5249 {
5250 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5251 }
5252
5253 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5254 {
5255 return emul_to_vcpu(ctxt)->arch.hflags;
5256 }
5257
5258 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5259 {
5260 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5261 }
5262
5263 static const struct x86_emulate_ops emulate_ops = {
5264 .read_gpr = emulator_read_gpr,
5265 .write_gpr = emulator_write_gpr,
5266 .read_std = kvm_read_guest_virt_system,
5267 .write_std = kvm_write_guest_virt_system,
5268 .read_phys = kvm_read_guest_phys_system,
5269 .fetch = kvm_fetch_guest_virt,
5270 .read_emulated = emulator_read_emulated,
5271 .write_emulated = emulator_write_emulated,
5272 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5273 .invlpg = emulator_invlpg,
5274 .pio_in_emulated = emulator_pio_in_emulated,
5275 .pio_out_emulated = emulator_pio_out_emulated,
5276 .get_segment = emulator_get_segment,
5277 .set_segment = emulator_set_segment,
5278 .get_cached_segment_base = emulator_get_cached_segment_base,
5279 .get_gdt = emulator_get_gdt,
5280 .get_idt = emulator_get_idt,
5281 .set_gdt = emulator_set_gdt,
5282 .set_idt = emulator_set_idt,
5283 .get_cr = emulator_get_cr,
5284 .set_cr = emulator_set_cr,
5285 .cpl = emulator_get_cpl,
5286 .get_dr = emulator_get_dr,
5287 .set_dr = emulator_set_dr,
5288 .get_smbase = emulator_get_smbase,
5289 .set_smbase = emulator_set_smbase,
5290 .set_msr = emulator_set_msr,
5291 .get_msr = emulator_get_msr,
5292 .check_pmc = emulator_check_pmc,
5293 .read_pmc = emulator_read_pmc,
5294 .halt = emulator_halt,
5295 .wbinvd = emulator_wbinvd,
5296 .fix_hypercall = emulator_fix_hypercall,
5297 .get_fpu = emulator_get_fpu,
5298 .put_fpu = emulator_put_fpu,
5299 .intercept = emulator_intercept,
5300 .get_cpuid = emulator_get_cpuid,
5301 .set_nmi_mask = emulator_set_nmi_mask,
5302 .get_hflags = emulator_get_hflags,
5303 .set_hflags = emulator_set_hflags,
5304 };
5305
5306 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5307 {
5308 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5309 /*
5310 * an sti; sti; sequence only disable interrupts for the first
5311 * instruction. So, if the last instruction, be it emulated or
5312 * not, left the system with the INT_STI flag enabled, it
5313 * means that the last instruction is an sti. We should not
5314 * leave the flag on in this case. The same goes for mov ss
5315 */
5316 if (int_shadow & mask)
5317 mask = 0;
5318 if (unlikely(int_shadow || mask)) {
5319 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5320 if (!mask)
5321 kvm_make_request(KVM_REQ_EVENT, vcpu);
5322 }
5323 }
5324
5325 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5326 {
5327 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5328 if (ctxt->exception.vector == PF_VECTOR)
5329 return kvm_propagate_fault(vcpu, &ctxt->exception);
5330
5331 if (ctxt->exception.error_code_valid)
5332 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5333 ctxt->exception.error_code);
5334 else
5335 kvm_queue_exception(vcpu, ctxt->exception.vector);
5336 return false;
5337 }
5338
5339 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5340 {
5341 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5342 int cs_db, cs_l;
5343
5344 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5345
5346 ctxt->eflags = kvm_get_rflags(vcpu);
5347 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5348
5349 ctxt->eip = kvm_rip_read(vcpu);
5350 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5351 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5352 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5353 cs_db ? X86EMUL_MODE_PROT32 :
5354 X86EMUL_MODE_PROT16;
5355 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5356 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5357 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5358
5359 init_decode_cache(ctxt);
5360 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5361 }
5362
5363 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5364 {
5365 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5366 int ret;
5367
5368 init_emulate_ctxt(vcpu);
5369
5370 ctxt->op_bytes = 2;
5371 ctxt->ad_bytes = 2;
5372 ctxt->_eip = ctxt->eip + inc_eip;
5373 ret = emulate_int_real(ctxt, irq);
5374
5375 if (ret != X86EMUL_CONTINUE)
5376 return EMULATE_FAIL;
5377
5378 ctxt->eip = ctxt->_eip;
5379 kvm_rip_write(vcpu, ctxt->eip);
5380 kvm_set_rflags(vcpu, ctxt->eflags);
5381
5382 if (irq == NMI_VECTOR)
5383 vcpu->arch.nmi_pending = 0;
5384 else
5385 vcpu->arch.interrupt.pending = false;
5386
5387 return EMULATE_DONE;
5388 }
5389 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5390
5391 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5392 {
5393 int r = EMULATE_DONE;
5394
5395 ++vcpu->stat.insn_emulation_fail;
5396 trace_kvm_emulate_insn_failed(vcpu);
5397 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5398 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5399 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5400 vcpu->run->internal.ndata = 0;
5401 r = EMULATE_FAIL;
5402 }
5403 kvm_queue_exception(vcpu, UD_VECTOR);
5404
5405 return r;
5406 }
5407
5408 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5409 bool write_fault_to_shadow_pgtable,
5410 int emulation_type)
5411 {
5412 gpa_t gpa = cr2;
5413 kvm_pfn_t pfn;
5414
5415 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5416 return false;
5417
5418 if (!vcpu->arch.mmu.direct_map) {
5419 /*
5420 * Write permission should be allowed since only
5421 * write access need to be emulated.
5422 */
5423 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5424
5425 /*
5426 * If the mapping is invalid in guest, let cpu retry
5427 * it to generate fault.
5428 */
5429 if (gpa == UNMAPPED_GVA)
5430 return true;
5431 }
5432
5433 /*
5434 * Do not retry the unhandleable instruction if it faults on the
5435 * readonly host memory, otherwise it will goto a infinite loop:
5436 * retry instruction -> write #PF -> emulation fail -> retry
5437 * instruction -> ...
5438 */
5439 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5440
5441 /*
5442 * If the instruction failed on the error pfn, it can not be fixed,
5443 * report the error to userspace.
5444 */
5445 if (is_error_noslot_pfn(pfn))
5446 return false;
5447
5448 kvm_release_pfn_clean(pfn);
5449
5450 /* The instructions are well-emulated on direct mmu. */
5451 if (vcpu->arch.mmu.direct_map) {
5452 unsigned int indirect_shadow_pages;
5453
5454 spin_lock(&vcpu->kvm->mmu_lock);
5455 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5456 spin_unlock(&vcpu->kvm->mmu_lock);
5457
5458 if (indirect_shadow_pages)
5459 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5460
5461 return true;
5462 }
5463
5464 /*
5465 * if emulation was due to access to shadowed page table
5466 * and it failed try to unshadow page and re-enter the
5467 * guest to let CPU execute the instruction.
5468 */
5469 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5470
5471 /*
5472 * If the access faults on its page table, it can not
5473 * be fixed by unprotecting shadow page and it should
5474 * be reported to userspace.
5475 */
5476 return !write_fault_to_shadow_pgtable;
5477 }
5478
5479 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5480 unsigned long cr2, int emulation_type)
5481 {
5482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5483 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5484
5485 last_retry_eip = vcpu->arch.last_retry_eip;
5486 last_retry_addr = vcpu->arch.last_retry_addr;
5487
5488 /*
5489 * If the emulation is caused by #PF and it is non-page_table
5490 * writing instruction, it means the VM-EXIT is caused by shadow
5491 * page protected, we can zap the shadow page and retry this
5492 * instruction directly.
5493 *
5494 * Note: if the guest uses a non-page-table modifying instruction
5495 * on the PDE that points to the instruction, then we will unmap
5496 * the instruction and go to an infinite loop. So, we cache the
5497 * last retried eip and the last fault address, if we meet the eip
5498 * and the address again, we can break out of the potential infinite
5499 * loop.
5500 */
5501 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5502
5503 if (!(emulation_type & EMULTYPE_RETRY))
5504 return false;
5505
5506 if (x86_page_table_writing_insn(ctxt))
5507 return false;
5508
5509 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5510 return false;
5511
5512 vcpu->arch.last_retry_eip = ctxt->eip;
5513 vcpu->arch.last_retry_addr = cr2;
5514
5515 if (!vcpu->arch.mmu.direct_map)
5516 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5517
5518 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5519
5520 return true;
5521 }
5522
5523 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5524 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5525
5526 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5527 {
5528 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5529 /* This is a good place to trace that we are exiting SMM. */
5530 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5531
5532 /* Process a latched INIT or SMI, if any. */
5533 kvm_make_request(KVM_REQ_EVENT, vcpu);
5534 }
5535
5536 kvm_mmu_reset_context(vcpu);
5537 }
5538
5539 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5540 {
5541 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5542
5543 vcpu->arch.hflags = emul_flags;
5544
5545 if (changed & HF_SMM_MASK)
5546 kvm_smm_changed(vcpu);
5547 }
5548
5549 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5550 unsigned long *db)
5551 {
5552 u32 dr6 = 0;
5553 int i;
5554 u32 enable, rwlen;
5555
5556 enable = dr7;
5557 rwlen = dr7 >> 16;
5558 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5559 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5560 dr6 |= (1 << i);
5561 return dr6;
5562 }
5563
5564 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5565 {
5566 struct kvm_run *kvm_run = vcpu->run;
5567
5568 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5569 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5570 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5571 kvm_run->debug.arch.exception = DB_VECTOR;
5572 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5573 *r = EMULATE_USER_EXIT;
5574 } else {
5575 /*
5576 * "Certain debug exceptions may clear bit 0-3. The
5577 * remaining contents of the DR6 register are never
5578 * cleared by the processor".
5579 */
5580 vcpu->arch.dr6 &= ~15;
5581 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5582 kvm_queue_exception(vcpu, DB_VECTOR);
5583 }
5584 }
5585
5586 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5587 {
5588 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5589 int r = EMULATE_DONE;
5590
5591 kvm_x86_ops->skip_emulated_instruction(vcpu);
5592
5593 /*
5594 * rflags is the old, "raw" value of the flags. The new value has
5595 * not been saved yet.
5596 *
5597 * This is correct even for TF set by the guest, because "the
5598 * processor will not generate this exception after the instruction
5599 * that sets the TF flag".
5600 */
5601 if (unlikely(rflags & X86_EFLAGS_TF))
5602 kvm_vcpu_do_singlestep(vcpu, &r);
5603 return r == EMULATE_DONE;
5604 }
5605 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5606
5607 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5608 {
5609 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5610 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5611 struct kvm_run *kvm_run = vcpu->run;
5612 unsigned long eip = kvm_get_linear_rip(vcpu);
5613 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5614 vcpu->arch.guest_debug_dr7,
5615 vcpu->arch.eff_db);
5616
5617 if (dr6 != 0) {
5618 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5619 kvm_run->debug.arch.pc = eip;
5620 kvm_run->debug.arch.exception = DB_VECTOR;
5621 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5622 *r = EMULATE_USER_EXIT;
5623 return true;
5624 }
5625 }
5626
5627 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5628 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5629 unsigned long eip = kvm_get_linear_rip(vcpu);
5630 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5631 vcpu->arch.dr7,
5632 vcpu->arch.db);
5633
5634 if (dr6 != 0) {
5635 vcpu->arch.dr6 &= ~15;
5636 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5637 kvm_queue_exception(vcpu, DB_VECTOR);
5638 *r = EMULATE_DONE;
5639 return true;
5640 }
5641 }
5642
5643 return false;
5644 }
5645
5646 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5647 unsigned long cr2,
5648 int emulation_type,
5649 void *insn,
5650 int insn_len)
5651 {
5652 int r;
5653 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5654 bool writeback = true;
5655 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5656
5657 /*
5658 * Clear write_fault_to_shadow_pgtable here to ensure it is
5659 * never reused.
5660 */
5661 vcpu->arch.write_fault_to_shadow_pgtable = false;
5662 kvm_clear_exception_queue(vcpu);
5663
5664 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5665 init_emulate_ctxt(vcpu);
5666
5667 /*
5668 * We will reenter on the same instruction since
5669 * we do not set complete_userspace_io. This does not
5670 * handle watchpoints yet, those would be handled in
5671 * the emulate_ops.
5672 */
5673 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5674 return r;
5675
5676 ctxt->interruptibility = 0;
5677 ctxt->have_exception = false;
5678 ctxt->exception.vector = -1;
5679 ctxt->perm_ok = false;
5680
5681 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5682
5683 r = x86_decode_insn(ctxt, insn, insn_len);
5684
5685 trace_kvm_emulate_insn_start(vcpu);
5686 ++vcpu->stat.insn_emulation;
5687 if (r != EMULATION_OK) {
5688 if (emulation_type & EMULTYPE_TRAP_UD)
5689 return EMULATE_FAIL;
5690 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5691 emulation_type))
5692 return EMULATE_DONE;
5693 if (emulation_type & EMULTYPE_SKIP)
5694 return EMULATE_FAIL;
5695 return handle_emulation_failure(vcpu);
5696 }
5697 }
5698
5699 if (emulation_type & EMULTYPE_SKIP) {
5700 kvm_rip_write(vcpu, ctxt->_eip);
5701 if (ctxt->eflags & X86_EFLAGS_RF)
5702 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5703 return EMULATE_DONE;
5704 }
5705
5706 if (retry_instruction(ctxt, cr2, emulation_type))
5707 return EMULATE_DONE;
5708
5709 /* this is needed for vmware backdoor interface to work since it
5710 changes registers values during IO operation */
5711 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5712 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5713 emulator_invalidate_register_cache(ctxt);
5714 }
5715
5716 restart:
5717 /* Save the faulting GPA (cr2) in the address field */
5718 ctxt->exception.address = cr2;
5719
5720 r = x86_emulate_insn(ctxt);
5721
5722 if (r == EMULATION_INTERCEPTED)
5723 return EMULATE_DONE;
5724
5725 if (r == EMULATION_FAILED) {
5726 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5727 emulation_type))
5728 return EMULATE_DONE;
5729
5730 return handle_emulation_failure(vcpu);
5731 }
5732
5733 if (ctxt->have_exception) {
5734 r = EMULATE_DONE;
5735 if (inject_emulated_exception(vcpu))
5736 return r;
5737 } else if (vcpu->arch.pio.count) {
5738 if (!vcpu->arch.pio.in) {
5739 /* FIXME: return into emulator if single-stepping. */
5740 vcpu->arch.pio.count = 0;
5741 } else {
5742 writeback = false;
5743 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5744 }
5745 r = EMULATE_USER_EXIT;
5746 } else if (vcpu->mmio_needed) {
5747 if (!vcpu->mmio_is_write)
5748 writeback = false;
5749 r = EMULATE_USER_EXIT;
5750 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5751 } else if (r == EMULATION_RESTART)
5752 goto restart;
5753 else
5754 r = EMULATE_DONE;
5755
5756 if (writeback) {
5757 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5758 toggle_interruptibility(vcpu, ctxt->interruptibility);
5759 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5760 kvm_rip_write(vcpu, ctxt->eip);
5761 if (r == EMULATE_DONE &&
5762 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5763 kvm_vcpu_do_singlestep(vcpu, &r);
5764 if (!ctxt->have_exception ||
5765 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5766 __kvm_set_rflags(vcpu, ctxt->eflags);
5767
5768 /*
5769 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5770 * do nothing, and it will be requested again as soon as
5771 * the shadow expires. But we still need to check here,
5772 * because POPF has no interrupt shadow.
5773 */
5774 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5775 kvm_make_request(KVM_REQ_EVENT, vcpu);
5776 } else
5777 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5778
5779 return r;
5780 }
5781 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5782
5783 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5784 {
5785 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5786 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5787 size, port, &val, 1);
5788 /* do not return to emulator after return from userspace */
5789 vcpu->arch.pio.count = 0;
5790 return ret;
5791 }
5792 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5793
5794 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5795 {
5796 unsigned long val;
5797
5798 /* We should only ever be called with arch.pio.count equal to 1 */
5799 BUG_ON(vcpu->arch.pio.count != 1);
5800
5801 /* For size less than 4 we merge, else we zero extend */
5802 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5803 : 0;
5804
5805 /*
5806 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5807 * the copy and tracing
5808 */
5809 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5810 vcpu->arch.pio.port, &val, 1);
5811 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5812
5813 return 1;
5814 }
5815
5816 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5817 {
5818 unsigned long val;
5819 int ret;
5820
5821 /* For size less than 4 we merge, else we zero extend */
5822 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5823
5824 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5825 &val, 1);
5826 if (ret) {
5827 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5828 return ret;
5829 }
5830
5831 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5832
5833 return 0;
5834 }
5835 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5836
5837 static int kvmclock_cpu_down_prep(unsigned int cpu)
5838 {
5839 __this_cpu_write(cpu_tsc_khz, 0);
5840 return 0;
5841 }
5842
5843 static void tsc_khz_changed(void *data)
5844 {
5845 struct cpufreq_freqs *freq = data;
5846 unsigned long khz = 0;
5847
5848 if (data)
5849 khz = freq->new;
5850 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5851 khz = cpufreq_quick_get(raw_smp_processor_id());
5852 if (!khz)
5853 khz = tsc_khz;
5854 __this_cpu_write(cpu_tsc_khz, khz);
5855 }
5856
5857 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5858 void *data)
5859 {
5860 struct cpufreq_freqs *freq = data;
5861 struct kvm *kvm;
5862 struct kvm_vcpu *vcpu;
5863 int i, send_ipi = 0;
5864
5865 /*
5866 * We allow guests to temporarily run on slowing clocks,
5867 * provided we notify them after, or to run on accelerating
5868 * clocks, provided we notify them before. Thus time never
5869 * goes backwards.
5870 *
5871 * However, we have a problem. We can't atomically update
5872 * the frequency of a given CPU from this function; it is
5873 * merely a notifier, which can be called from any CPU.
5874 * Changing the TSC frequency at arbitrary points in time
5875 * requires a recomputation of local variables related to
5876 * the TSC for each VCPU. We must flag these local variables
5877 * to be updated and be sure the update takes place with the
5878 * new frequency before any guests proceed.
5879 *
5880 * Unfortunately, the combination of hotplug CPU and frequency
5881 * change creates an intractable locking scenario; the order
5882 * of when these callouts happen is undefined with respect to
5883 * CPU hotplug, and they can race with each other. As such,
5884 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5885 * undefined; you can actually have a CPU frequency change take
5886 * place in between the computation of X and the setting of the
5887 * variable. To protect against this problem, all updates of
5888 * the per_cpu tsc_khz variable are done in an interrupt
5889 * protected IPI, and all callers wishing to update the value
5890 * must wait for a synchronous IPI to complete (which is trivial
5891 * if the caller is on the CPU already). This establishes the
5892 * necessary total order on variable updates.
5893 *
5894 * Note that because a guest time update may take place
5895 * anytime after the setting of the VCPU's request bit, the
5896 * correct TSC value must be set before the request. However,
5897 * to ensure the update actually makes it to any guest which
5898 * starts running in hardware virtualization between the set
5899 * and the acquisition of the spinlock, we must also ping the
5900 * CPU after setting the request bit.
5901 *
5902 */
5903
5904 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5905 return 0;
5906 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5907 return 0;
5908
5909 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5910
5911 spin_lock(&kvm_lock);
5912 list_for_each_entry(kvm, &vm_list, vm_list) {
5913 kvm_for_each_vcpu(i, vcpu, kvm) {
5914 if (vcpu->cpu != freq->cpu)
5915 continue;
5916 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5917 if (vcpu->cpu != smp_processor_id())
5918 send_ipi = 1;
5919 }
5920 }
5921 spin_unlock(&kvm_lock);
5922
5923 if (freq->old < freq->new && send_ipi) {
5924 /*
5925 * We upscale the frequency. Must make the guest
5926 * doesn't see old kvmclock values while running with
5927 * the new frequency, otherwise we risk the guest sees
5928 * time go backwards.
5929 *
5930 * In case we update the frequency for another cpu
5931 * (which might be in guest context) send an interrupt
5932 * to kick the cpu out of guest context. Next time
5933 * guest context is entered kvmclock will be updated,
5934 * so the guest will not see stale values.
5935 */
5936 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5937 }
5938 return 0;
5939 }
5940
5941 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5942 .notifier_call = kvmclock_cpufreq_notifier
5943 };
5944
5945 static int kvmclock_cpu_online(unsigned int cpu)
5946 {
5947 tsc_khz_changed(NULL);
5948 return 0;
5949 }
5950
5951 static void kvm_timer_init(void)
5952 {
5953 max_tsc_khz = tsc_khz;
5954
5955 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5956 #ifdef CONFIG_CPU_FREQ
5957 struct cpufreq_policy policy;
5958 int cpu;
5959
5960 memset(&policy, 0, sizeof(policy));
5961 cpu = get_cpu();
5962 cpufreq_get_policy(&policy, cpu);
5963 if (policy.cpuinfo.max_freq)
5964 max_tsc_khz = policy.cpuinfo.max_freq;
5965 put_cpu();
5966 #endif
5967 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5968 CPUFREQ_TRANSITION_NOTIFIER);
5969 }
5970 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5971
5972 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5973 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5974 }
5975
5976 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5977
5978 int kvm_is_in_guest(void)
5979 {
5980 return __this_cpu_read(current_vcpu) != NULL;
5981 }
5982
5983 static int kvm_is_user_mode(void)
5984 {
5985 int user_mode = 3;
5986
5987 if (__this_cpu_read(current_vcpu))
5988 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5989
5990 return user_mode != 0;
5991 }
5992
5993 static unsigned long kvm_get_guest_ip(void)
5994 {
5995 unsigned long ip = 0;
5996
5997 if (__this_cpu_read(current_vcpu))
5998 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5999
6000 return ip;
6001 }
6002
6003 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6004 .is_in_guest = kvm_is_in_guest,
6005 .is_user_mode = kvm_is_user_mode,
6006 .get_guest_ip = kvm_get_guest_ip,
6007 };
6008
6009 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6010 {
6011 __this_cpu_write(current_vcpu, vcpu);
6012 }
6013 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6014
6015 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6016 {
6017 __this_cpu_write(current_vcpu, NULL);
6018 }
6019 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6020
6021 static void kvm_set_mmio_spte_mask(void)
6022 {
6023 u64 mask;
6024 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6025
6026 /*
6027 * Set the reserved bits and the present bit of an paging-structure
6028 * entry to generate page fault with PFER.RSV = 1.
6029 */
6030 /* Mask the reserved physical address bits. */
6031 mask = rsvd_bits(maxphyaddr, 51);
6032
6033 /* Set the present bit. */
6034 mask |= 1ull;
6035
6036 #ifdef CONFIG_X86_64
6037 /*
6038 * If reserved bit is not supported, clear the present bit to disable
6039 * mmio page fault.
6040 */
6041 if (maxphyaddr == 52)
6042 mask &= ~1ull;
6043 #endif
6044
6045 kvm_mmu_set_mmio_spte_mask(mask);
6046 }
6047
6048 #ifdef CONFIG_X86_64
6049 static void pvclock_gtod_update_fn(struct work_struct *work)
6050 {
6051 struct kvm *kvm;
6052
6053 struct kvm_vcpu *vcpu;
6054 int i;
6055
6056 spin_lock(&kvm_lock);
6057 list_for_each_entry(kvm, &vm_list, vm_list)
6058 kvm_for_each_vcpu(i, vcpu, kvm)
6059 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6060 atomic_set(&kvm_guest_has_master_clock, 0);
6061 spin_unlock(&kvm_lock);
6062 }
6063
6064 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6065
6066 /*
6067 * Notification about pvclock gtod data update.
6068 */
6069 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6070 void *priv)
6071 {
6072 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6073 struct timekeeper *tk = priv;
6074
6075 update_pvclock_gtod(tk);
6076
6077 /* disable master clock if host does not trust, or does not
6078 * use, TSC clocksource
6079 */
6080 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6081 atomic_read(&kvm_guest_has_master_clock) != 0)
6082 queue_work(system_long_wq, &pvclock_gtod_work);
6083
6084 return 0;
6085 }
6086
6087 static struct notifier_block pvclock_gtod_notifier = {
6088 .notifier_call = pvclock_gtod_notify,
6089 };
6090 #endif
6091
6092 int kvm_arch_init(void *opaque)
6093 {
6094 int r;
6095 struct kvm_x86_ops *ops = opaque;
6096
6097 if (kvm_x86_ops) {
6098 printk(KERN_ERR "kvm: already loaded the other module\n");
6099 r = -EEXIST;
6100 goto out;
6101 }
6102
6103 if (!ops->cpu_has_kvm_support()) {
6104 printk(KERN_ERR "kvm: no hardware support\n");
6105 r = -EOPNOTSUPP;
6106 goto out;
6107 }
6108 if (ops->disabled_by_bios()) {
6109 printk(KERN_ERR "kvm: disabled by bios\n");
6110 r = -EOPNOTSUPP;
6111 goto out;
6112 }
6113
6114 r = -ENOMEM;
6115 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6116 if (!shared_msrs) {
6117 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6118 goto out;
6119 }
6120
6121 r = kvm_mmu_module_init();
6122 if (r)
6123 goto out_free_percpu;
6124
6125 kvm_set_mmio_spte_mask();
6126
6127 kvm_x86_ops = ops;
6128
6129 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6130 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6131 PT_PRESENT_MASK, 0);
6132 kvm_timer_init();
6133
6134 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6135
6136 if (boot_cpu_has(X86_FEATURE_XSAVE))
6137 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6138
6139 kvm_lapic_init();
6140 #ifdef CONFIG_X86_64
6141 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6142 #endif
6143
6144 return 0;
6145
6146 out_free_percpu:
6147 free_percpu(shared_msrs);
6148 out:
6149 return r;
6150 }
6151
6152 void kvm_arch_exit(void)
6153 {
6154 kvm_lapic_exit();
6155 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6156
6157 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6158 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6159 CPUFREQ_TRANSITION_NOTIFIER);
6160 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6161 #ifdef CONFIG_X86_64
6162 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6163 #endif
6164 kvm_x86_ops = NULL;
6165 kvm_mmu_module_exit();
6166 free_percpu(shared_msrs);
6167 }
6168
6169 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6170 {
6171 ++vcpu->stat.halt_exits;
6172 if (lapic_in_kernel(vcpu)) {
6173 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6174 return 1;
6175 } else {
6176 vcpu->run->exit_reason = KVM_EXIT_HLT;
6177 return 0;
6178 }
6179 }
6180 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6181
6182 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6183 {
6184 int ret = kvm_skip_emulated_instruction(vcpu);
6185 /*
6186 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6187 * KVM_EXIT_DEBUG here.
6188 */
6189 return kvm_vcpu_halt(vcpu) && ret;
6190 }
6191 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6192
6193 #ifdef CONFIG_X86_64
6194 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6195 unsigned long clock_type)
6196 {
6197 struct kvm_clock_pairing clock_pairing;
6198 struct timespec ts;
6199 u64 cycle;
6200 int ret;
6201
6202 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6203 return -KVM_EOPNOTSUPP;
6204
6205 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6206 return -KVM_EOPNOTSUPP;
6207
6208 clock_pairing.sec = ts.tv_sec;
6209 clock_pairing.nsec = ts.tv_nsec;
6210 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6211 clock_pairing.flags = 0;
6212
6213 ret = 0;
6214 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6215 sizeof(struct kvm_clock_pairing)))
6216 ret = -KVM_EFAULT;
6217
6218 return ret;
6219 }
6220 #endif
6221
6222 /*
6223 * kvm_pv_kick_cpu_op: Kick a vcpu.
6224 *
6225 * @apicid - apicid of vcpu to be kicked.
6226 */
6227 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6228 {
6229 struct kvm_lapic_irq lapic_irq;
6230
6231 lapic_irq.shorthand = 0;
6232 lapic_irq.dest_mode = 0;
6233 lapic_irq.dest_id = apicid;
6234 lapic_irq.msi_redir_hint = false;
6235
6236 lapic_irq.delivery_mode = APIC_DM_REMRD;
6237 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6238 }
6239
6240 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6241 {
6242 vcpu->arch.apicv_active = false;
6243 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6244 }
6245
6246 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6247 {
6248 unsigned long nr, a0, a1, a2, a3, ret;
6249 int op_64_bit, r;
6250
6251 r = kvm_skip_emulated_instruction(vcpu);
6252
6253 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6254 return kvm_hv_hypercall(vcpu);
6255
6256 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6257 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6258 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6259 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6260 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6261
6262 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6263
6264 op_64_bit = is_64_bit_mode(vcpu);
6265 if (!op_64_bit) {
6266 nr &= 0xFFFFFFFF;
6267 a0 &= 0xFFFFFFFF;
6268 a1 &= 0xFFFFFFFF;
6269 a2 &= 0xFFFFFFFF;
6270 a3 &= 0xFFFFFFFF;
6271 }
6272
6273 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6274 ret = -KVM_EPERM;
6275 goto out;
6276 }
6277
6278 switch (nr) {
6279 case KVM_HC_VAPIC_POLL_IRQ:
6280 ret = 0;
6281 break;
6282 case KVM_HC_KICK_CPU:
6283 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6284 ret = 0;
6285 break;
6286 #ifdef CONFIG_X86_64
6287 case KVM_HC_CLOCK_PAIRING:
6288 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6289 break;
6290 #endif
6291 default:
6292 ret = -KVM_ENOSYS;
6293 break;
6294 }
6295 out:
6296 if (!op_64_bit)
6297 ret = (u32)ret;
6298 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6299 ++vcpu->stat.hypercalls;
6300 return r;
6301 }
6302 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6303
6304 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6305 {
6306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6307 char instruction[3];
6308 unsigned long rip = kvm_rip_read(vcpu);
6309
6310 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6311
6312 return emulator_write_emulated(ctxt, rip, instruction, 3,
6313 &ctxt->exception);
6314 }
6315
6316 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6317 {
6318 return vcpu->run->request_interrupt_window &&
6319 likely(!pic_in_kernel(vcpu->kvm));
6320 }
6321
6322 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6323 {
6324 struct kvm_run *kvm_run = vcpu->run;
6325
6326 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6327 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6328 kvm_run->cr8 = kvm_get_cr8(vcpu);
6329 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6330 kvm_run->ready_for_interrupt_injection =
6331 pic_in_kernel(vcpu->kvm) ||
6332 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6333 }
6334
6335 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6336 {
6337 int max_irr, tpr;
6338
6339 if (!kvm_x86_ops->update_cr8_intercept)
6340 return;
6341
6342 if (!lapic_in_kernel(vcpu))
6343 return;
6344
6345 if (vcpu->arch.apicv_active)
6346 return;
6347
6348 if (!vcpu->arch.apic->vapic_addr)
6349 max_irr = kvm_lapic_find_highest_irr(vcpu);
6350 else
6351 max_irr = -1;
6352
6353 if (max_irr != -1)
6354 max_irr >>= 4;
6355
6356 tpr = kvm_lapic_get_cr8(vcpu);
6357
6358 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6359 }
6360
6361 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6362 {
6363 int r;
6364
6365 /* try to reinject previous events if any */
6366 if (vcpu->arch.exception.pending) {
6367 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6368 vcpu->arch.exception.has_error_code,
6369 vcpu->arch.exception.error_code);
6370
6371 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6372 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6373 X86_EFLAGS_RF);
6374
6375 if (vcpu->arch.exception.nr == DB_VECTOR &&
6376 (vcpu->arch.dr7 & DR7_GD)) {
6377 vcpu->arch.dr7 &= ~DR7_GD;
6378 kvm_update_dr7(vcpu);
6379 }
6380
6381 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6382 vcpu->arch.exception.has_error_code,
6383 vcpu->arch.exception.error_code,
6384 vcpu->arch.exception.reinject);
6385 return 0;
6386 }
6387
6388 if (vcpu->arch.nmi_injected) {
6389 kvm_x86_ops->set_nmi(vcpu);
6390 return 0;
6391 }
6392
6393 if (vcpu->arch.interrupt.pending) {
6394 kvm_x86_ops->set_irq(vcpu);
6395 return 0;
6396 }
6397
6398 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6399 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6400 if (r != 0)
6401 return r;
6402 }
6403
6404 /* try to inject new event if pending */
6405 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6406 vcpu->arch.smi_pending = false;
6407 enter_smm(vcpu);
6408 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6409 --vcpu->arch.nmi_pending;
6410 vcpu->arch.nmi_injected = true;
6411 kvm_x86_ops->set_nmi(vcpu);
6412 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6413 /*
6414 * Because interrupts can be injected asynchronously, we are
6415 * calling check_nested_events again here to avoid a race condition.
6416 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6417 * proposal and current concerns. Perhaps we should be setting
6418 * KVM_REQ_EVENT only on certain events and not unconditionally?
6419 */
6420 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6421 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6422 if (r != 0)
6423 return r;
6424 }
6425 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6426 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6427 false);
6428 kvm_x86_ops->set_irq(vcpu);
6429 }
6430 }
6431
6432 return 0;
6433 }
6434
6435 static void process_nmi(struct kvm_vcpu *vcpu)
6436 {
6437 unsigned limit = 2;
6438
6439 /*
6440 * x86 is limited to one NMI running, and one NMI pending after it.
6441 * If an NMI is already in progress, limit further NMIs to just one.
6442 * Otherwise, allow two (and we'll inject the first one immediately).
6443 */
6444 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6445 limit = 1;
6446
6447 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6448 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6449 kvm_make_request(KVM_REQ_EVENT, vcpu);
6450 }
6451
6452 #define put_smstate(type, buf, offset, val) \
6453 *(type *)((buf) + (offset) - 0x7e00) = val
6454
6455 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6456 {
6457 u32 flags = 0;
6458 flags |= seg->g << 23;
6459 flags |= seg->db << 22;
6460 flags |= seg->l << 21;
6461 flags |= seg->avl << 20;
6462 flags |= seg->present << 15;
6463 flags |= seg->dpl << 13;
6464 flags |= seg->s << 12;
6465 flags |= seg->type << 8;
6466 return flags;
6467 }
6468
6469 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6470 {
6471 struct kvm_segment seg;
6472 int offset;
6473
6474 kvm_get_segment(vcpu, &seg, n);
6475 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6476
6477 if (n < 3)
6478 offset = 0x7f84 + n * 12;
6479 else
6480 offset = 0x7f2c + (n - 3) * 12;
6481
6482 put_smstate(u32, buf, offset + 8, seg.base);
6483 put_smstate(u32, buf, offset + 4, seg.limit);
6484 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6485 }
6486
6487 #ifdef CONFIG_X86_64
6488 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6489 {
6490 struct kvm_segment seg;
6491 int offset;
6492 u16 flags;
6493
6494 kvm_get_segment(vcpu, &seg, n);
6495 offset = 0x7e00 + n * 16;
6496
6497 flags = enter_smm_get_segment_flags(&seg) >> 8;
6498 put_smstate(u16, buf, offset, seg.selector);
6499 put_smstate(u16, buf, offset + 2, flags);
6500 put_smstate(u32, buf, offset + 4, seg.limit);
6501 put_smstate(u64, buf, offset + 8, seg.base);
6502 }
6503 #endif
6504
6505 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6506 {
6507 struct desc_ptr dt;
6508 struct kvm_segment seg;
6509 unsigned long val;
6510 int i;
6511
6512 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6513 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6514 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6515 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6516
6517 for (i = 0; i < 8; i++)
6518 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6519
6520 kvm_get_dr(vcpu, 6, &val);
6521 put_smstate(u32, buf, 0x7fcc, (u32)val);
6522 kvm_get_dr(vcpu, 7, &val);
6523 put_smstate(u32, buf, 0x7fc8, (u32)val);
6524
6525 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6526 put_smstate(u32, buf, 0x7fc4, seg.selector);
6527 put_smstate(u32, buf, 0x7f64, seg.base);
6528 put_smstate(u32, buf, 0x7f60, seg.limit);
6529 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6530
6531 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6532 put_smstate(u32, buf, 0x7fc0, seg.selector);
6533 put_smstate(u32, buf, 0x7f80, seg.base);
6534 put_smstate(u32, buf, 0x7f7c, seg.limit);
6535 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6536
6537 kvm_x86_ops->get_gdt(vcpu, &dt);
6538 put_smstate(u32, buf, 0x7f74, dt.address);
6539 put_smstate(u32, buf, 0x7f70, dt.size);
6540
6541 kvm_x86_ops->get_idt(vcpu, &dt);
6542 put_smstate(u32, buf, 0x7f58, dt.address);
6543 put_smstate(u32, buf, 0x7f54, dt.size);
6544
6545 for (i = 0; i < 6; i++)
6546 enter_smm_save_seg_32(vcpu, buf, i);
6547
6548 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6549
6550 /* revision id */
6551 put_smstate(u32, buf, 0x7efc, 0x00020000);
6552 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6553 }
6554
6555 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6556 {
6557 #ifdef CONFIG_X86_64
6558 struct desc_ptr dt;
6559 struct kvm_segment seg;
6560 unsigned long val;
6561 int i;
6562
6563 for (i = 0; i < 16; i++)
6564 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6565
6566 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6567 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6568
6569 kvm_get_dr(vcpu, 6, &val);
6570 put_smstate(u64, buf, 0x7f68, val);
6571 kvm_get_dr(vcpu, 7, &val);
6572 put_smstate(u64, buf, 0x7f60, val);
6573
6574 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6575 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6576 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6577
6578 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6579
6580 /* revision id */
6581 put_smstate(u32, buf, 0x7efc, 0x00020064);
6582
6583 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6584
6585 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6586 put_smstate(u16, buf, 0x7e90, seg.selector);
6587 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6588 put_smstate(u32, buf, 0x7e94, seg.limit);
6589 put_smstate(u64, buf, 0x7e98, seg.base);
6590
6591 kvm_x86_ops->get_idt(vcpu, &dt);
6592 put_smstate(u32, buf, 0x7e84, dt.size);
6593 put_smstate(u64, buf, 0x7e88, dt.address);
6594
6595 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6596 put_smstate(u16, buf, 0x7e70, seg.selector);
6597 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6598 put_smstate(u32, buf, 0x7e74, seg.limit);
6599 put_smstate(u64, buf, 0x7e78, seg.base);
6600
6601 kvm_x86_ops->get_gdt(vcpu, &dt);
6602 put_smstate(u32, buf, 0x7e64, dt.size);
6603 put_smstate(u64, buf, 0x7e68, dt.address);
6604
6605 for (i = 0; i < 6; i++)
6606 enter_smm_save_seg_64(vcpu, buf, i);
6607 #else
6608 WARN_ON_ONCE(1);
6609 #endif
6610 }
6611
6612 static void enter_smm(struct kvm_vcpu *vcpu)
6613 {
6614 struct kvm_segment cs, ds;
6615 struct desc_ptr dt;
6616 char buf[512];
6617 u32 cr0;
6618
6619 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6620 vcpu->arch.hflags |= HF_SMM_MASK;
6621 memset(buf, 0, 512);
6622 if (guest_cpuid_has_longmode(vcpu))
6623 enter_smm_save_state_64(vcpu, buf);
6624 else
6625 enter_smm_save_state_32(vcpu, buf);
6626
6627 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6628
6629 if (kvm_x86_ops->get_nmi_mask(vcpu))
6630 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6631 else
6632 kvm_x86_ops->set_nmi_mask(vcpu, true);
6633
6634 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6635 kvm_rip_write(vcpu, 0x8000);
6636
6637 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6638 kvm_x86_ops->set_cr0(vcpu, cr0);
6639 vcpu->arch.cr0 = cr0;
6640
6641 kvm_x86_ops->set_cr4(vcpu, 0);
6642
6643 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6644 dt.address = dt.size = 0;
6645 kvm_x86_ops->set_idt(vcpu, &dt);
6646
6647 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6648
6649 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6650 cs.base = vcpu->arch.smbase;
6651
6652 ds.selector = 0;
6653 ds.base = 0;
6654
6655 cs.limit = ds.limit = 0xffffffff;
6656 cs.type = ds.type = 0x3;
6657 cs.dpl = ds.dpl = 0;
6658 cs.db = ds.db = 0;
6659 cs.s = ds.s = 1;
6660 cs.l = ds.l = 0;
6661 cs.g = ds.g = 1;
6662 cs.avl = ds.avl = 0;
6663 cs.present = ds.present = 1;
6664 cs.unusable = ds.unusable = 0;
6665 cs.padding = ds.padding = 0;
6666
6667 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6668 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6669 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6670 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6671 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6672 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6673
6674 if (guest_cpuid_has_longmode(vcpu))
6675 kvm_x86_ops->set_efer(vcpu, 0);
6676
6677 kvm_update_cpuid(vcpu);
6678 kvm_mmu_reset_context(vcpu);
6679 }
6680
6681 static void process_smi(struct kvm_vcpu *vcpu)
6682 {
6683 vcpu->arch.smi_pending = true;
6684 kvm_make_request(KVM_REQ_EVENT, vcpu);
6685 }
6686
6687 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6688 {
6689 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6690 }
6691
6692 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6693 {
6694 u64 eoi_exit_bitmap[4];
6695
6696 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6697 return;
6698
6699 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6700
6701 if (irqchip_split(vcpu->kvm))
6702 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6703 else {
6704 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6705 kvm_x86_ops->sync_pir_to_irr(vcpu);
6706 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6707 }
6708 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6709 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6710 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6711 }
6712
6713 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6714 {
6715 ++vcpu->stat.tlb_flush;
6716 kvm_x86_ops->tlb_flush(vcpu);
6717 }
6718
6719 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6720 {
6721 struct page *page = NULL;
6722
6723 if (!lapic_in_kernel(vcpu))
6724 return;
6725
6726 if (!kvm_x86_ops->set_apic_access_page_addr)
6727 return;
6728
6729 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6730 if (is_error_page(page))
6731 return;
6732 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6733
6734 /*
6735 * Do not pin apic access page in memory, the MMU notifier
6736 * will call us again if it is migrated or swapped out.
6737 */
6738 put_page(page);
6739 }
6740 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6741
6742 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6743 unsigned long address)
6744 {
6745 /*
6746 * The physical address of apic access page is stored in the VMCS.
6747 * Update it when it becomes invalid.
6748 */
6749 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6750 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6751 }
6752
6753 /*
6754 * Returns 1 to let vcpu_run() continue the guest execution loop without
6755 * exiting to the userspace. Otherwise, the value will be returned to the
6756 * userspace.
6757 */
6758 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6759 {
6760 int r;
6761 bool req_int_win =
6762 dm_request_for_irq_injection(vcpu) &&
6763 kvm_cpu_accept_dm_intr(vcpu);
6764
6765 bool req_immediate_exit = false;
6766
6767 if (vcpu->requests) {
6768 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6769 kvm_mmu_unload(vcpu);
6770 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6771 __kvm_migrate_timers(vcpu);
6772 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6773 kvm_gen_update_masterclock(vcpu->kvm);
6774 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6775 kvm_gen_kvmclock_update(vcpu);
6776 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6777 r = kvm_guest_time_update(vcpu);
6778 if (unlikely(r))
6779 goto out;
6780 }
6781 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6782 kvm_mmu_sync_roots(vcpu);
6783 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6784 kvm_vcpu_flush_tlb(vcpu);
6785 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6786 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6787 r = 0;
6788 goto out;
6789 }
6790 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6791 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6792 r = 0;
6793 goto out;
6794 }
6795 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6796 /* Page is swapped out. Do synthetic halt */
6797 vcpu->arch.apf.halted = true;
6798 r = 1;
6799 goto out;
6800 }
6801 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6802 record_steal_time(vcpu);
6803 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6804 process_smi(vcpu);
6805 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6806 process_nmi(vcpu);
6807 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6808 kvm_pmu_handle_event(vcpu);
6809 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6810 kvm_pmu_deliver_pmi(vcpu);
6811 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6812 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6813 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6814 vcpu->arch.ioapic_handled_vectors)) {
6815 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6816 vcpu->run->eoi.vector =
6817 vcpu->arch.pending_ioapic_eoi;
6818 r = 0;
6819 goto out;
6820 }
6821 }
6822 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6823 vcpu_scan_ioapic(vcpu);
6824 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6825 kvm_vcpu_reload_apic_access_page(vcpu);
6826 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6827 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6828 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6829 r = 0;
6830 goto out;
6831 }
6832 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6833 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6834 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6835 r = 0;
6836 goto out;
6837 }
6838 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6839 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6840 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6841 r = 0;
6842 goto out;
6843 }
6844
6845 /*
6846 * KVM_REQ_HV_STIMER has to be processed after
6847 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6848 * depend on the guest clock being up-to-date
6849 */
6850 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6851 kvm_hv_process_stimers(vcpu);
6852 }
6853
6854 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6855 ++vcpu->stat.req_event;
6856 kvm_apic_accept_events(vcpu);
6857 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6858 r = 1;
6859 goto out;
6860 }
6861
6862 if (inject_pending_event(vcpu, req_int_win) != 0)
6863 req_immediate_exit = true;
6864 else {
6865 /* Enable NMI/IRQ window open exits if needed.
6866 *
6867 * SMIs have two cases: 1) they can be nested, and
6868 * then there is nothing to do here because RSM will
6869 * cause a vmexit anyway; 2) or the SMI can be pending
6870 * because inject_pending_event has completed the
6871 * injection of an IRQ or NMI from the previous vmexit,
6872 * and then we request an immediate exit to inject the SMI.
6873 */
6874 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6875 req_immediate_exit = true;
6876 if (vcpu->arch.nmi_pending)
6877 kvm_x86_ops->enable_nmi_window(vcpu);
6878 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6879 kvm_x86_ops->enable_irq_window(vcpu);
6880 }
6881
6882 if (kvm_lapic_enabled(vcpu)) {
6883 update_cr8_intercept(vcpu);
6884 kvm_lapic_sync_to_vapic(vcpu);
6885 }
6886 }
6887
6888 r = kvm_mmu_reload(vcpu);
6889 if (unlikely(r)) {
6890 goto cancel_injection;
6891 }
6892
6893 preempt_disable();
6894
6895 kvm_x86_ops->prepare_guest_switch(vcpu);
6896 kvm_load_guest_fpu(vcpu);
6897
6898 /*
6899 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6900 * IPI are then delayed after guest entry, which ensures that they
6901 * result in virtual interrupt delivery.
6902 */
6903 local_irq_disable();
6904 vcpu->mode = IN_GUEST_MODE;
6905
6906 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6907
6908 /*
6909 * 1) We should set ->mode before checking ->requests. Please see
6910 * the comment in kvm_make_all_cpus_request.
6911 *
6912 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6913 * pairs with the memory barrier implicit in pi_test_and_set_on
6914 * (see vmx_deliver_posted_interrupt).
6915 *
6916 * 3) This also orders the write to mode from any reads to the page
6917 * tables done while the VCPU is running. Please see the comment
6918 * in kvm_flush_remote_tlbs.
6919 */
6920 smp_mb__after_srcu_read_unlock();
6921
6922 /*
6923 * This handles the case where a posted interrupt was
6924 * notified with kvm_vcpu_kick.
6925 */
6926 if (kvm_lapic_enabled(vcpu)) {
6927 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6928 kvm_x86_ops->sync_pir_to_irr(vcpu);
6929 }
6930
6931 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6932 || need_resched() || signal_pending(current)) {
6933 vcpu->mode = OUTSIDE_GUEST_MODE;
6934 smp_wmb();
6935 local_irq_enable();
6936 preempt_enable();
6937 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6938 r = 1;
6939 goto cancel_injection;
6940 }
6941
6942 kvm_load_guest_xcr0(vcpu);
6943
6944 if (req_immediate_exit) {
6945 kvm_make_request(KVM_REQ_EVENT, vcpu);
6946 smp_send_reschedule(vcpu->cpu);
6947 }
6948
6949 trace_kvm_entry(vcpu->vcpu_id);
6950 wait_lapic_expire(vcpu);
6951 guest_enter_irqoff();
6952
6953 if (unlikely(vcpu->arch.switch_db_regs)) {
6954 set_debugreg(0, 7);
6955 set_debugreg(vcpu->arch.eff_db[0], 0);
6956 set_debugreg(vcpu->arch.eff_db[1], 1);
6957 set_debugreg(vcpu->arch.eff_db[2], 2);
6958 set_debugreg(vcpu->arch.eff_db[3], 3);
6959 set_debugreg(vcpu->arch.dr6, 6);
6960 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6961 }
6962
6963 kvm_x86_ops->run(vcpu);
6964
6965 /*
6966 * Do this here before restoring debug registers on the host. And
6967 * since we do this before handling the vmexit, a DR access vmexit
6968 * can (a) read the correct value of the debug registers, (b) set
6969 * KVM_DEBUGREG_WONT_EXIT again.
6970 */
6971 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6972 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6973 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6974 kvm_update_dr0123(vcpu);
6975 kvm_update_dr6(vcpu);
6976 kvm_update_dr7(vcpu);
6977 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6978 }
6979
6980 /*
6981 * If the guest has used debug registers, at least dr7
6982 * will be disabled while returning to the host.
6983 * If we don't have active breakpoints in the host, we don't
6984 * care about the messed up debug address registers. But if
6985 * we have some of them active, restore the old state.
6986 */
6987 if (hw_breakpoint_active())
6988 hw_breakpoint_restore();
6989
6990 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6991
6992 vcpu->mode = OUTSIDE_GUEST_MODE;
6993 smp_wmb();
6994
6995 kvm_put_guest_xcr0(vcpu);
6996
6997 kvm_x86_ops->handle_external_intr(vcpu);
6998
6999 ++vcpu->stat.exits;
7000
7001 guest_exit_irqoff();
7002
7003 local_irq_enable();
7004 preempt_enable();
7005
7006 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7007
7008 /*
7009 * Profile KVM exit RIPs:
7010 */
7011 if (unlikely(prof_on == KVM_PROFILING)) {
7012 unsigned long rip = kvm_rip_read(vcpu);
7013 profile_hit(KVM_PROFILING, (void *)rip);
7014 }
7015
7016 if (unlikely(vcpu->arch.tsc_always_catchup))
7017 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7018
7019 if (vcpu->arch.apic_attention)
7020 kvm_lapic_sync_from_vapic(vcpu);
7021
7022 r = kvm_x86_ops->handle_exit(vcpu);
7023 return r;
7024
7025 cancel_injection:
7026 kvm_x86_ops->cancel_injection(vcpu);
7027 if (unlikely(vcpu->arch.apic_attention))
7028 kvm_lapic_sync_from_vapic(vcpu);
7029 out:
7030 return r;
7031 }
7032
7033 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7034 {
7035 if (!kvm_arch_vcpu_runnable(vcpu) &&
7036 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7037 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7038 kvm_vcpu_block(vcpu);
7039 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7040
7041 if (kvm_x86_ops->post_block)
7042 kvm_x86_ops->post_block(vcpu);
7043
7044 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7045 return 1;
7046 }
7047
7048 kvm_apic_accept_events(vcpu);
7049 switch(vcpu->arch.mp_state) {
7050 case KVM_MP_STATE_HALTED:
7051 vcpu->arch.pv.pv_unhalted = false;
7052 vcpu->arch.mp_state =
7053 KVM_MP_STATE_RUNNABLE;
7054 case KVM_MP_STATE_RUNNABLE:
7055 vcpu->arch.apf.halted = false;
7056 break;
7057 case KVM_MP_STATE_INIT_RECEIVED:
7058 break;
7059 default:
7060 return -EINTR;
7061 break;
7062 }
7063 return 1;
7064 }
7065
7066 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7067 {
7068 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7069 kvm_x86_ops->check_nested_events(vcpu, false);
7070
7071 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7072 !vcpu->arch.apf.halted);
7073 }
7074
7075 static int vcpu_run(struct kvm_vcpu *vcpu)
7076 {
7077 int r;
7078 struct kvm *kvm = vcpu->kvm;
7079
7080 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7081
7082 for (;;) {
7083 if (kvm_vcpu_running(vcpu)) {
7084 r = vcpu_enter_guest(vcpu);
7085 } else {
7086 r = vcpu_block(kvm, vcpu);
7087 }
7088
7089 if (r <= 0)
7090 break;
7091
7092 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7093 if (kvm_cpu_has_pending_timer(vcpu))
7094 kvm_inject_pending_timer_irqs(vcpu);
7095
7096 if (dm_request_for_irq_injection(vcpu) &&
7097 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7098 r = 0;
7099 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7100 ++vcpu->stat.request_irq_exits;
7101 break;
7102 }
7103
7104 kvm_check_async_pf_completion(vcpu);
7105
7106 if (signal_pending(current)) {
7107 r = -EINTR;
7108 vcpu->run->exit_reason = KVM_EXIT_INTR;
7109 ++vcpu->stat.signal_exits;
7110 break;
7111 }
7112 if (need_resched()) {
7113 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7114 cond_resched();
7115 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7116 }
7117 }
7118
7119 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7120
7121 return r;
7122 }
7123
7124 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7125 {
7126 int r;
7127 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7128 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7129 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7130 if (r != EMULATE_DONE)
7131 return 0;
7132 return 1;
7133 }
7134
7135 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7136 {
7137 BUG_ON(!vcpu->arch.pio.count);
7138
7139 return complete_emulated_io(vcpu);
7140 }
7141
7142 /*
7143 * Implements the following, as a state machine:
7144 *
7145 * read:
7146 * for each fragment
7147 * for each mmio piece in the fragment
7148 * write gpa, len
7149 * exit
7150 * copy data
7151 * execute insn
7152 *
7153 * write:
7154 * for each fragment
7155 * for each mmio piece in the fragment
7156 * write gpa, len
7157 * copy data
7158 * exit
7159 */
7160 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7161 {
7162 struct kvm_run *run = vcpu->run;
7163 struct kvm_mmio_fragment *frag;
7164 unsigned len;
7165
7166 BUG_ON(!vcpu->mmio_needed);
7167
7168 /* Complete previous fragment */
7169 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7170 len = min(8u, frag->len);
7171 if (!vcpu->mmio_is_write)
7172 memcpy(frag->data, run->mmio.data, len);
7173
7174 if (frag->len <= 8) {
7175 /* Switch to the next fragment. */
7176 frag++;
7177 vcpu->mmio_cur_fragment++;
7178 } else {
7179 /* Go forward to the next mmio piece. */
7180 frag->data += len;
7181 frag->gpa += len;
7182 frag->len -= len;
7183 }
7184
7185 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7186 vcpu->mmio_needed = 0;
7187
7188 /* FIXME: return into emulator if single-stepping. */
7189 if (vcpu->mmio_is_write)
7190 return 1;
7191 vcpu->mmio_read_completed = 1;
7192 return complete_emulated_io(vcpu);
7193 }
7194
7195 run->exit_reason = KVM_EXIT_MMIO;
7196 run->mmio.phys_addr = frag->gpa;
7197 if (vcpu->mmio_is_write)
7198 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7199 run->mmio.len = min(8u, frag->len);
7200 run->mmio.is_write = vcpu->mmio_is_write;
7201 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7202 return 0;
7203 }
7204
7205
7206 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7207 {
7208 struct fpu *fpu = &current->thread.fpu;
7209 int r;
7210 sigset_t sigsaved;
7211
7212 fpu__activate_curr(fpu);
7213
7214 if (vcpu->sigset_active)
7215 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7216
7217 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7218 kvm_vcpu_block(vcpu);
7219 kvm_apic_accept_events(vcpu);
7220 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
7221 r = -EAGAIN;
7222 goto out;
7223 }
7224
7225 /* re-sync apic's tpr */
7226 if (!lapic_in_kernel(vcpu)) {
7227 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7228 r = -EINVAL;
7229 goto out;
7230 }
7231 }
7232
7233 if (unlikely(vcpu->arch.complete_userspace_io)) {
7234 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7235 vcpu->arch.complete_userspace_io = NULL;
7236 r = cui(vcpu);
7237 if (r <= 0)
7238 goto out;
7239 } else
7240 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7241
7242 if (kvm_run->immediate_exit)
7243 r = -EINTR;
7244 else
7245 r = vcpu_run(vcpu);
7246
7247 out:
7248 post_kvm_run_save(vcpu);
7249 if (vcpu->sigset_active)
7250 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7251
7252 return r;
7253 }
7254
7255 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7256 {
7257 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7258 /*
7259 * We are here if userspace calls get_regs() in the middle of
7260 * instruction emulation. Registers state needs to be copied
7261 * back from emulation context to vcpu. Userspace shouldn't do
7262 * that usually, but some bad designed PV devices (vmware
7263 * backdoor interface) need this to work
7264 */
7265 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7266 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7267 }
7268 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7269 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7270 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7271 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7272 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7273 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7274 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7275 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7276 #ifdef CONFIG_X86_64
7277 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7278 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7279 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7280 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7281 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7282 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7283 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7284 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7285 #endif
7286
7287 regs->rip = kvm_rip_read(vcpu);
7288 regs->rflags = kvm_get_rflags(vcpu);
7289
7290 return 0;
7291 }
7292
7293 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7294 {
7295 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7296 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7297
7298 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7299 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7300 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7301 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7302 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7303 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7304 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7305 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7306 #ifdef CONFIG_X86_64
7307 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7308 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7309 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7310 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7311 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7312 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7313 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7314 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7315 #endif
7316
7317 kvm_rip_write(vcpu, regs->rip);
7318 kvm_set_rflags(vcpu, regs->rflags);
7319
7320 vcpu->arch.exception.pending = false;
7321
7322 kvm_make_request(KVM_REQ_EVENT, vcpu);
7323
7324 return 0;
7325 }
7326
7327 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7328 {
7329 struct kvm_segment cs;
7330
7331 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7332 *db = cs.db;
7333 *l = cs.l;
7334 }
7335 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7336
7337 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7338 struct kvm_sregs *sregs)
7339 {
7340 struct desc_ptr dt;
7341
7342 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7343 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7344 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7345 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7346 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7347 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7348
7349 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7350 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7351
7352 kvm_x86_ops->get_idt(vcpu, &dt);
7353 sregs->idt.limit = dt.size;
7354 sregs->idt.base = dt.address;
7355 kvm_x86_ops->get_gdt(vcpu, &dt);
7356 sregs->gdt.limit = dt.size;
7357 sregs->gdt.base = dt.address;
7358
7359 sregs->cr0 = kvm_read_cr0(vcpu);
7360 sregs->cr2 = vcpu->arch.cr2;
7361 sregs->cr3 = kvm_read_cr3(vcpu);
7362 sregs->cr4 = kvm_read_cr4(vcpu);
7363 sregs->cr8 = kvm_get_cr8(vcpu);
7364 sregs->efer = vcpu->arch.efer;
7365 sregs->apic_base = kvm_get_apic_base(vcpu);
7366
7367 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7368
7369 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7370 set_bit(vcpu->arch.interrupt.nr,
7371 (unsigned long *)sregs->interrupt_bitmap);
7372
7373 return 0;
7374 }
7375
7376 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7377 struct kvm_mp_state *mp_state)
7378 {
7379 kvm_apic_accept_events(vcpu);
7380 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7381 vcpu->arch.pv.pv_unhalted)
7382 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7383 else
7384 mp_state->mp_state = vcpu->arch.mp_state;
7385
7386 return 0;
7387 }
7388
7389 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7390 struct kvm_mp_state *mp_state)
7391 {
7392 if (!lapic_in_kernel(vcpu) &&
7393 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7394 return -EINVAL;
7395
7396 /* INITs are latched while in SMM */
7397 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7398 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7399 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7400 return -EINVAL;
7401
7402 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7403 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7404 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7405 } else
7406 vcpu->arch.mp_state = mp_state->mp_state;
7407 kvm_make_request(KVM_REQ_EVENT, vcpu);
7408 return 0;
7409 }
7410
7411 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7412 int reason, bool has_error_code, u32 error_code)
7413 {
7414 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7415 int ret;
7416
7417 init_emulate_ctxt(vcpu);
7418
7419 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7420 has_error_code, error_code);
7421
7422 if (ret)
7423 return EMULATE_FAIL;
7424
7425 kvm_rip_write(vcpu, ctxt->eip);
7426 kvm_set_rflags(vcpu, ctxt->eflags);
7427 kvm_make_request(KVM_REQ_EVENT, vcpu);
7428 return EMULATE_DONE;
7429 }
7430 EXPORT_SYMBOL_GPL(kvm_task_switch);
7431
7432 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7433 struct kvm_sregs *sregs)
7434 {
7435 struct msr_data apic_base_msr;
7436 int mmu_reset_needed = 0;
7437 int pending_vec, max_bits, idx;
7438 struct desc_ptr dt;
7439
7440 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7441 return -EINVAL;
7442
7443 dt.size = sregs->idt.limit;
7444 dt.address = sregs->idt.base;
7445 kvm_x86_ops->set_idt(vcpu, &dt);
7446 dt.size = sregs->gdt.limit;
7447 dt.address = sregs->gdt.base;
7448 kvm_x86_ops->set_gdt(vcpu, &dt);
7449
7450 vcpu->arch.cr2 = sregs->cr2;
7451 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7452 vcpu->arch.cr3 = sregs->cr3;
7453 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7454
7455 kvm_set_cr8(vcpu, sregs->cr8);
7456
7457 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7458 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7459 apic_base_msr.data = sregs->apic_base;
7460 apic_base_msr.host_initiated = true;
7461 kvm_set_apic_base(vcpu, &apic_base_msr);
7462
7463 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7464 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7465 vcpu->arch.cr0 = sregs->cr0;
7466
7467 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7468 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7469 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7470 kvm_update_cpuid(vcpu);
7471
7472 idx = srcu_read_lock(&vcpu->kvm->srcu);
7473 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7474 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7475 mmu_reset_needed = 1;
7476 }
7477 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7478
7479 if (mmu_reset_needed)
7480 kvm_mmu_reset_context(vcpu);
7481
7482 max_bits = KVM_NR_INTERRUPTS;
7483 pending_vec = find_first_bit(
7484 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7485 if (pending_vec < max_bits) {
7486 kvm_queue_interrupt(vcpu, pending_vec, false);
7487 pr_debug("Set back pending irq %d\n", pending_vec);
7488 }
7489
7490 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7491 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7492 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7493 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7494 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7495 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7496
7497 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7498 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7499
7500 update_cr8_intercept(vcpu);
7501
7502 /* Older userspace won't unhalt the vcpu on reset. */
7503 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7504 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7505 !is_protmode(vcpu))
7506 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7507
7508 kvm_make_request(KVM_REQ_EVENT, vcpu);
7509
7510 return 0;
7511 }
7512
7513 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7514 struct kvm_guest_debug *dbg)
7515 {
7516 unsigned long rflags;
7517 int i, r;
7518
7519 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7520 r = -EBUSY;
7521 if (vcpu->arch.exception.pending)
7522 goto out;
7523 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7524 kvm_queue_exception(vcpu, DB_VECTOR);
7525 else
7526 kvm_queue_exception(vcpu, BP_VECTOR);
7527 }
7528
7529 /*
7530 * Read rflags as long as potentially injected trace flags are still
7531 * filtered out.
7532 */
7533 rflags = kvm_get_rflags(vcpu);
7534
7535 vcpu->guest_debug = dbg->control;
7536 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7537 vcpu->guest_debug = 0;
7538
7539 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7540 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7541 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7542 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7543 } else {
7544 for (i = 0; i < KVM_NR_DB_REGS; i++)
7545 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7546 }
7547 kvm_update_dr7(vcpu);
7548
7549 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7550 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7551 get_segment_base(vcpu, VCPU_SREG_CS);
7552
7553 /*
7554 * Trigger an rflags update that will inject or remove the trace
7555 * flags.
7556 */
7557 kvm_set_rflags(vcpu, rflags);
7558
7559 kvm_x86_ops->update_bp_intercept(vcpu);
7560
7561 r = 0;
7562
7563 out:
7564
7565 return r;
7566 }
7567
7568 /*
7569 * Translate a guest virtual address to a guest physical address.
7570 */
7571 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7572 struct kvm_translation *tr)
7573 {
7574 unsigned long vaddr = tr->linear_address;
7575 gpa_t gpa;
7576 int idx;
7577
7578 idx = srcu_read_lock(&vcpu->kvm->srcu);
7579 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7580 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7581 tr->physical_address = gpa;
7582 tr->valid = gpa != UNMAPPED_GVA;
7583 tr->writeable = 1;
7584 tr->usermode = 0;
7585
7586 return 0;
7587 }
7588
7589 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7590 {
7591 struct fxregs_state *fxsave =
7592 &vcpu->arch.guest_fpu.state.fxsave;
7593
7594 memcpy(fpu->fpr, fxsave->st_space, 128);
7595 fpu->fcw = fxsave->cwd;
7596 fpu->fsw = fxsave->swd;
7597 fpu->ftwx = fxsave->twd;
7598 fpu->last_opcode = fxsave->fop;
7599 fpu->last_ip = fxsave->rip;
7600 fpu->last_dp = fxsave->rdp;
7601 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7602
7603 return 0;
7604 }
7605
7606 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7607 {
7608 struct fxregs_state *fxsave =
7609 &vcpu->arch.guest_fpu.state.fxsave;
7610
7611 memcpy(fxsave->st_space, fpu->fpr, 128);
7612 fxsave->cwd = fpu->fcw;
7613 fxsave->swd = fpu->fsw;
7614 fxsave->twd = fpu->ftwx;
7615 fxsave->fop = fpu->last_opcode;
7616 fxsave->rip = fpu->last_ip;
7617 fxsave->rdp = fpu->last_dp;
7618 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7619
7620 return 0;
7621 }
7622
7623 static void fx_init(struct kvm_vcpu *vcpu)
7624 {
7625 fpstate_init(&vcpu->arch.guest_fpu.state);
7626 if (boot_cpu_has(X86_FEATURE_XSAVES))
7627 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7628 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7629
7630 /*
7631 * Ensure guest xcr0 is valid for loading
7632 */
7633 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7634
7635 vcpu->arch.cr0 |= X86_CR0_ET;
7636 }
7637
7638 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7639 {
7640 if (vcpu->guest_fpu_loaded)
7641 return;
7642
7643 /*
7644 * Restore all possible states in the guest,
7645 * and assume host would use all available bits.
7646 * Guest xcr0 would be loaded later.
7647 */
7648 vcpu->guest_fpu_loaded = 1;
7649 __kernel_fpu_begin();
7650 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7651 trace_kvm_fpu(1);
7652 }
7653
7654 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7655 {
7656 if (!vcpu->guest_fpu_loaded)
7657 return;
7658
7659 vcpu->guest_fpu_loaded = 0;
7660 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7661 __kernel_fpu_end();
7662 ++vcpu->stat.fpu_reload;
7663 trace_kvm_fpu(0);
7664 }
7665
7666 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7667 {
7668 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7669
7670 kvmclock_reset(vcpu);
7671
7672 kvm_x86_ops->vcpu_free(vcpu);
7673 free_cpumask_var(wbinvd_dirty_mask);
7674 }
7675
7676 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7677 unsigned int id)
7678 {
7679 struct kvm_vcpu *vcpu;
7680
7681 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7682 printk_once(KERN_WARNING
7683 "kvm: SMP vm created on host with unstable TSC; "
7684 "guest TSC will not be reliable\n");
7685
7686 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7687
7688 return vcpu;
7689 }
7690
7691 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7692 {
7693 int r;
7694
7695 kvm_vcpu_mtrr_init(vcpu);
7696 r = vcpu_load(vcpu);
7697 if (r)
7698 return r;
7699 kvm_vcpu_reset(vcpu, false);
7700 kvm_mmu_setup(vcpu);
7701 vcpu_put(vcpu);
7702 return r;
7703 }
7704
7705 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7706 {
7707 struct msr_data msr;
7708 struct kvm *kvm = vcpu->kvm;
7709
7710 if (vcpu_load(vcpu))
7711 return;
7712 msr.data = 0x0;
7713 msr.index = MSR_IA32_TSC;
7714 msr.host_initiated = true;
7715 kvm_write_tsc(vcpu, &msr);
7716 vcpu_put(vcpu);
7717
7718 if (!kvmclock_periodic_sync)
7719 return;
7720
7721 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7722 KVMCLOCK_SYNC_PERIOD);
7723 }
7724
7725 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7726 {
7727 int r;
7728 vcpu->arch.apf.msr_val = 0;
7729
7730 r = vcpu_load(vcpu);
7731 BUG_ON(r);
7732 kvm_mmu_unload(vcpu);
7733 vcpu_put(vcpu);
7734
7735 kvm_x86_ops->vcpu_free(vcpu);
7736 }
7737
7738 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7739 {
7740 vcpu->arch.hflags = 0;
7741
7742 vcpu->arch.smi_pending = 0;
7743 atomic_set(&vcpu->arch.nmi_queued, 0);
7744 vcpu->arch.nmi_pending = 0;
7745 vcpu->arch.nmi_injected = false;
7746 kvm_clear_interrupt_queue(vcpu);
7747 kvm_clear_exception_queue(vcpu);
7748
7749 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7750 kvm_update_dr0123(vcpu);
7751 vcpu->arch.dr6 = DR6_INIT;
7752 kvm_update_dr6(vcpu);
7753 vcpu->arch.dr7 = DR7_FIXED_1;
7754 kvm_update_dr7(vcpu);
7755
7756 vcpu->arch.cr2 = 0;
7757
7758 kvm_make_request(KVM_REQ_EVENT, vcpu);
7759 vcpu->arch.apf.msr_val = 0;
7760 vcpu->arch.st.msr_val = 0;
7761
7762 kvmclock_reset(vcpu);
7763
7764 kvm_clear_async_pf_completion_queue(vcpu);
7765 kvm_async_pf_hash_reset(vcpu);
7766 vcpu->arch.apf.halted = false;
7767
7768 if (!init_event) {
7769 kvm_pmu_reset(vcpu);
7770 vcpu->arch.smbase = 0x30000;
7771 }
7772
7773 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7774 vcpu->arch.regs_avail = ~0;
7775 vcpu->arch.regs_dirty = ~0;
7776
7777 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7778 }
7779
7780 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7781 {
7782 struct kvm_segment cs;
7783
7784 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7785 cs.selector = vector << 8;
7786 cs.base = vector << 12;
7787 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7788 kvm_rip_write(vcpu, 0);
7789 }
7790
7791 int kvm_arch_hardware_enable(void)
7792 {
7793 struct kvm *kvm;
7794 struct kvm_vcpu *vcpu;
7795 int i;
7796 int ret;
7797 u64 local_tsc;
7798 u64 max_tsc = 0;
7799 bool stable, backwards_tsc = false;
7800
7801 kvm_shared_msr_cpu_online();
7802 ret = kvm_x86_ops->hardware_enable();
7803 if (ret != 0)
7804 return ret;
7805
7806 local_tsc = rdtsc();
7807 stable = !check_tsc_unstable();
7808 list_for_each_entry(kvm, &vm_list, vm_list) {
7809 kvm_for_each_vcpu(i, vcpu, kvm) {
7810 if (!stable && vcpu->cpu == smp_processor_id())
7811 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7812 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7813 backwards_tsc = true;
7814 if (vcpu->arch.last_host_tsc > max_tsc)
7815 max_tsc = vcpu->arch.last_host_tsc;
7816 }
7817 }
7818 }
7819
7820 /*
7821 * Sometimes, even reliable TSCs go backwards. This happens on
7822 * platforms that reset TSC during suspend or hibernate actions, but
7823 * maintain synchronization. We must compensate. Fortunately, we can
7824 * detect that condition here, which happens early in CPU bringup,
7825 * before any KVM threads can be running. Unfortunately, we can't
7826 * bring the TSCs fully up to date with real time, as we aren't yet far
7827 * enough into CPU bringup that we know how much real time has actually
7828 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7829 * variables that haven't been updated yet.
7830 *
7831 * So we simply find the maximum observed TSC above, then record the
7832 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7833 * the adjustment will be applied. Note that we accumulate
7834 * adjustments, in case multiple suspend cycles happen before some VCPU
7835 * gets a chance to run again. In the event that no KVM threads get a
7836 * chance to run, we will miss the entire elapsed period, as we'll have
7837 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7838 * loose cycle time. This isn't too big a deal, since the loss will be
7839 * uniform across all VCPUs (not to mention the scenario is extremely
7840 * unlikely). It is possible that a second hibernate recovery happens
7841 * much faster than a first, causing the observed TSC here to be
7842 * smaller; this would require additional padding adjustment, which is
7843 * why we set last_host_tsc to the local tsc observed here.
7844 *
7845 * N.B. - this code below runs only on platforms with reliable TSC,
7846 * as that is the only way backwards_tsc is set above. Also note
7847 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7848 * have the same delta_cyc adjustment applied if backwards_tsc
7849 * is detected. Note further, this adjustment is only done once,
7850 * as we reset last_host_tsc on all VCPUs to stop this from being
7851 * called multiple times (one for each physical CPU bringup).
7852 *
7853 * Platforms with unreliable TSCs don't have to deal with this, they
7854 * will be compensated by the logic in vcpu_load, which sets the TSC to
7855 * catchup mode. This will catchup all VCPUs to real time, but cannot
7856 * guarantee that they stay in perfect synchronization.
7857 */
7858 if (backwards_tsc) {
7859 u64 delta_cyc = max_tsc - local_tsc;
7860 backwards_tsc_observed = true;
7861 list_for_each_entry(kvm, &vm_list, vm_list) {
7862 kvm_for_each_vcpu(i, vcpu, kvm) {
7863 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7864 vcpu->arch.last_host_tsc = local_tsc;
7865 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7866 }
7867
7868 /*
7869 * We have to disable TSC offset matching.. if you were
7870 * booting a VM while issuing an S4 host suspend....
7871 * you may have some problem. Solving this issue is
7872 * left as an exercise to the reader.
7873 */
7874 kvm->arch.last_tsc_nsec = 0;
7875 kvm->arch.last_tsc_write = 0;
7876 }
7877
7878 }
7879 return 0;
7880 }
7881
7882 void kvm_arch_hardware_disable(void)
7883 {
7884 kvm_x86_ops->hardware_disable();
7885 drop_user_return_notifiers();
7886 }
7887
7888 int kvm_arch_hardware_setup(void)
7889 {
7890 int r;
7891
7892 r = kvm_x86_ops->hardware_setup();
7893 if (r != 0)
7894 return r;
7895
7896 if (kvm_has_tsc_control) {
7897 /*
7898 * Make sure the user can only configure tsc_khz values that
7899 * fit into a signed integer.
7900 * A min value is not calculated needed because it will always
7901 * be 1 on all machines.
7902 */
7903 u64 max = min(0x7fffffffULL,
7904 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7905 kvm_max_guest_tsc_khz = max;
7906
7907 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7908 }
7909
7910 kvm_init_msr_list();
7911 return 0;
7912 }
7913
7914 void kvm_arch_hardware_unsetup(void)
7915 {
7916 kvm_x86_ops->hardware_unsetup();
7917 }
7918
7919 void kvm_arch_check_processor_compat(void *rtn)
7920 {
7921 kvm_x86_ops->check_processor_compatibility(rtn);
7922 }
7923
7924 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7925 {
7926 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7927 }
7928 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7929
7930 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7931 {
7932 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7933 }
7934
7935 struct static_key kvm_no_apic_vcpu __read_mostly;
7936 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7937
7938 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7939 {
7940 struct page *page;
7941 struct kvm *kvm;
7942 int r;
7943
7944 BUG_ON(vcpu->kvm == NULL);
7945 kvm = vcpu->kvm;
7946
7947 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7948 vcpu->arch.pv.pv_unhalted = false;
7949 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7950 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7951 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7952 else
7953 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7954
7955 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7956 if (!page) {
7957 r = -ENOMEM;
7958 goto fail;
7959 }
7960 vcpu->arch.pio_data = page_address(page);
7961
7962 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7963
7964 r = kvm_mmu_create(vcpu);
7965 if (r < 0)
7966 goto fail_free_pio_data;
7967
7968 if (irqchip_in_kernel(kvm)) {
7969 r = kvm_create_lapic(vcpu);
7970 if (r < 0)
7971 goto fail_mmu_destroy;
7972 } else
7973 static_key_slow_inc(&kvm_no_apic_vcpu);
7974
7975 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7976 GFP_KERNEL);
7977 if (!vcpu->arch.mce_banks) {
7978 r = -ENOMEM;
7979 goto fail_free_lapic;
7980 }
7981 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7982
7983 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7984 r = -ENOMEM;
7985 goto fail_free_mce_banks;
7986 }
7987
7988 fx_init(vcpu);
7989
7990 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7991 vcpu->arch.pv_time_enabled = false;
7992
7993 vcpu->arch.guest_supported_xcr0 = 0;
7994 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7995
7996 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7997
7998 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7999
8000 kvm_async_pf_hash_reset(vcpu);
8001 kvm_pmu_init(vcpu);
8002
8003 vcpu->arch.pending_external_vector = -1;
8004
8005 kvm_hv_vcpu_init(vcpu);
8006
8007 return 0;
8008
8009 fail_free_mce_banks:
8010 kfree(vcpu->arch.mce_banks);
8011 fail_free_lapic:
8012 kvm_free_lapic(vcpu);
8013 fail_mmu_destroy:
8014 kvm_mmu_destroy(vcpu);
8015 fail_free_pio_data:
8016 free_page((unsigned long)vcpu->arch.pio_data);
8017 fail:
8018 return r;
8019 }
8020
8021 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8022 {
8023 int idx;
8024
8025 kvm_hv_vcpu_uninit(vcpu);
8026 kvm_pmu_destroy(vcpu);
8027 kfree(vcpu->arch.mce_banks);
8028 kvm_free_lapic(vcpu);
8029 idx = srcu_read_lock(&vcpu->kvm->srcu);
8030 kvm_mmu_destroy(vcpu);
8031 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8032 free_page((unsigned long)vcpu->arch.pio_data);
8033 if (!lapic_in_kernel(vcpu))
8034 static_key_slow_dec(&kvm_no_apic_vcpu);
8035 }
8036
8037 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8038 {
8039 kvm_x86_ops->sched_in(vcpu, cpu);
8040 }
8041
8042 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8043 {
8044 if (type)
8045 return -EINVAL;
8046
8047 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8048 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8049 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8050 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8051 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8052
8053 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8054 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8055 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8056 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8057 &kvm->arch.irq_sources_bitmap);
8058
8059 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8060 mutex_init(&kvm->arch.apic_map_lock);
8061 mutex_init(&kvm->arch.hyperv.hv_lock);
8062 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8063
8064 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8065 pvclock_update_vm_gtod_copy(kvm);
8066
8067 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8068 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8069
8070 kvm_page_track_init(kvm);
8071 kvm_mmu_init_vm(kvm);
8072
8073 if (kvm_x86_ops->vm_init)
8074 return kvm_x86_ops->vm_init(kvm);
8075
8076 return 0;
8077 }
8078
8079 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8080 {
8081 int r;
8082 r = vcpu_load(vcpu);
8083 BUG_ON(r);
8084 kvm_mmu_unload(vcpu);
8085 vcpu_put(vcpu);
8086 }
8087
8088 static void kvm_free_vcpus(struct kvm *kvm)
8089 {
8090 unsigned int i;
8091 struct kvm_vcpu *vcpu;
8092
8093 /*
8094 * Unpin any mmu pages first.
8095 */
8096 kvm_for_each_vcpu(i, vcpu, kvm) {
8097 kvm_clear_async_pf_completion_queue(vcpu);
8098 kvm_unload_vcpu_mmu(vcpu);
8099 }
8100 kvm_for_each_vcpu(i, vcpu, kvm)
8101 kvm_arch_vcpu_free(vcpu);
8102
8103 mutex_lock(&kvm->lock);
8104 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8105 kvm->vcpus[i] = NULL;
8106
8107 atomic_set(&kvm->online_vcpus, 0);
8108 mutex_unlock(&kvm->lock);
8109 }
8110
8111 void kvm_arch_sync_events(struct kvm *kvm)
8112 {
8113 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8114 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8115 kvm_free_all_assigned_devices(kvm);
8116 kvm_free_pit(kvm);
8117 }
8118
8119 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8120 {
8121 int i, r;
8122 unsigned long hva;
8123 struct kvm_memslots *slots = kvm_memslots(kvm);
8124 struct kvm_memory_slot *slot, old;
8125
8126 /* Called with kvm->slots_lock held. */
8127 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8128 return -EINVAL;
8129
8130 slot = id_to_memslot(slots, id);
8131 if (size) {
8132 if (slot->npages)
8133 return -EEXIST;
8134
8135 /*
8136 * MAP_SHARED to prevent internal slot pages from being moved
8137 * by fork()/COW.
8138 */
8139 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8140 MAP_SHARED | MAP_ANONYMOUS, 0);
8141 if (IS_ERR((void *)hva))
8142 return PTR_ERR((void *)hva);
8143 } else {
8144 if (!slot->npages)
8145 return 0;
8146
8147 hva = 0;
8148 }
8149
8150 old = *slot;
8151 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8152 struct kvm_userspace_memory_region m;
8153
8154 m.slot = id | (i << 16);
8155 m.flags = 0;
8156 m.guest_phys_addr = gpa;
8157 m.userspace_addr = hva;
8158 m.memory_size = size;
8159 r = __kvm_set_memory_region(kvm, &m);
8160 if (r < 0)
8161 return r;
8162 }
8163
8164 if (!size) {
8165 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8166 WARN_ON(r < 0);
8167 }
8168
8169 return 0;
8170 }
8171 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8172
8173 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8174 {
8175 int r;
8176
8177 mutex_lock(&kvm->slots_lock);
8178 r = __x86_set_memory_region(kvm, id, gpa, size);
8179 mutex_unlock(&kvm->slots_lock);
8180
8181 return r;
8182 }
8183 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8184
8185 void kvm_arch_destroy_vm(struct kvm *kvm)
8186 {
8187 if (current->mm == kvm->mm) {
8188 /*
8189 * Free memory regions allocated on behalf of userspace,
8190 * unless the the memory map has changed due to process exit
8191 * or fd copying.
8192 */
8193 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8194 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8195 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8196 }
8197 if (kvm_x86_ops->vm_destroy)
8198 kvm_x86_ops->vm_destroy(kvm);
8199 kvm_iommu_unmap_guest(kvm);
8200 kvm_pic_destroy(kvm);
8201 kvm_ioapic_destroy(kvm);
8202 kvm_free_vcpus(kvm);
8203 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8204 kvm_mmu_uninit_vm(kvm);
8205 kvm_page_track_cleanup(kvm);
8206 }
8207
8208 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8209 struct kvm_memory_slot *dont)
8210 {
8211 int i;
8212
8213 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8214 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8215 kvfree(free->arch.rmap[i]);
8216 free->arch.rmap[i] = NULL;
8217 }
8218 if (i == 0)
8219 continue;
8220
8221 if (!dont || free->arch.lpage_info[i - 1] !=
8222 dont->arch.lpage_info[i - 1]) {
8223 kvfree(free->arch.lpage_info[i - 1]);
8224 free->arch.lpage_info[i - 1] = NULL;
8225 }
8226 }
8227
8228 kvm_page_track_free_memslot(free, dont);
8229 }
8230
8231 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8232 unsigned long npages)
8233 {
8234 int i;
8235
8236 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8237 struct kvm_lpage_info *linfo;
8238 unsigned long ugfn;
8239 int lpages;
8240 int level = i + 1;
8241
8242 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8243 slot->base_gfn, level) + 1;
8244
8245 slot->arch.rmap[i] =
8246 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8247 if (!slot->arch.rmap[i])
8248 goto out_free;
8249 if (i == 0)
8250 continue;
8251
8252 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8253 if (!linfo)
8254 goto out_free;
8255
8256 slot->arch.lpage_info[i - 1] = linfo;
8257
8258 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8259 linfo[0].disallow_lpage = 1;
8260 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8261 linfo[lpages - 1].disallow_lpage = 1;
8262 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8263 /*
8264 * If the gfn and userspace address are not aligned wrt each
8265 * other, or if explicitly asked to, disable large page
8266 * support for this slot
8267 */
8268 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8269 !kvm_largepages_enabled()) {
8270 unsigned long j;
8271
8272 for (j = 0; j < lpages; ++j)
8273 linfo[j].disallow_lpage = 1;
8274 }
8275 }
8276
8277 if (kvm_page_track_create_memslot(slot, npages))
8278 goto out_free;
8279
8280 return 0;
8281
8282 out_free:
8283 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8284 kvfree(slot->arch.rmap[i]);
8285 slot->arch.rmap[i] = NULL;
8286 if (i == 0)
8287 continue;
8288
8289 kvfree(slot->arch.lpage_info[i - 1]);
8290 slot->arch.lpage_info[i - 1] = NULL;
8291 }
8292 return -ENOMEM;
8293 }
8294
8295 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8296 {
8297 /*
8298 * memslots->generation has been incremented.
8299 * mmio generation may have reached its maximum value.
8300 */
8301 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8302 }
8303
8304 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8305 struct kvm_memory_slot *memslot,
8306 const struct kvm_userspace_memory_region *mem,
8307 enum kvm_mr_change change)
8308 {
8309 return 0;
8310 }
8311
8312 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8313 struct kvm_memory_slot *new)
8314 {
8315 /* Still write protect RO slot */
8316 if (new->flags & KVM_MEM_READONLY) {
8317 kvm_mmu_slot_remove_write_access(kvm, new);
8318 return;
8319 }
8320
8321 /*
8322 * Call kvm_x86_ops dirty logging hooks when they are valid.
8323 *
8324 * kvm_x86_ops->slot_disable_log_dirty is called when:
8325 *
8326 * - KVM_MR_CREATE with dirty logging is disabled
8327 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8328 *
8329 * The reason is, in case of PML, we need to set D-bit for any slots
8330 * with dirty logging disabled in order to eliminate unnecessary GPA
8331 * logging in PML buffer (and potential PML buffer full VMEXT). This
8332 * guarantees leaving PML enabled during guest's lifetime won't have
8333 * any additonal overhead from PML when guest is running with dirty
8334 * logging disabled for memory slots.
8335 *
8336 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8337 * to dirty logging mode.
8338 *
8339 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8340 *
8341 * In case of write protect:
8342 *
8343 * Write protect all pages for dirty logging.
8344 *
8345 * All the sptes including the large sptes which point to this
8346 * slot are set to readonly. We can not create any new large
8347 * spte on this slot until the end of the logging.
8348 *
8349 * See the comments in fast_page_fault().
8350 */
8351 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8352 if (kvm_x86_ops->slot_enable_log_dirty)
8353 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8354 else
8355 kvm_mmu_slot_remove_write_access(kvm, new);
8356 } else {
8357 if (kvm_x86_ops->slot_disable_log_dirty)
8358 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8359 }
8360 }
8361
8362 void kvm_arch_commit_memory_region(struct kvm *kvm,
8363 const struct kvm_userspace_memory_region *mem,
8364 const struct kvm_memory_slot *old,
8365 const struct kvm_memory_slot *new,
8366 enum kvm_mr_change change)
8367 {
8368 int nr_mmu_pages = 0;
8369
8370 if (!kvm->arch.n_requested_mmu_pages)
8371 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8372
8373 if (nr_mmu_pages)
8374 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8375
8376 /*
8377 * Dirty logging tracks sptes in 4k granularity, meaning that large
8378 * sptes have to be split. If live migration is successful, the guest
8379 * in the source machine will be destroyed and large sptes will be
8380 * created in the destination. However, if the guest continues to run
8381 * in the source machine (for example if live migration fails), small
8382 * sptes will remain around and cause bad performance.
8383 *
8384 * Scan sptes if dirty logging has been stopped, dropping those
8385 * which can be collapsed into a single large-page spte. Later
8386 * page faults will create the large-page sptes.
8387 */
8388 if ((change != KVM_MR_DELETE) &&
8389 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8390 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8391 kvm_mmu_zap_collapsible_sptes(kvm, new);
8392
8393 /*
8394 * Set up write protection and/or dirty logging for the new slot.
8395 *
8396 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8397 * been zapped so no dirty logging staff is needed for old slot. For
8398 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8399 * new and it's also covered when dealing with the new slot.
8400 *
8401 * FIXME: const-ify all uses of struct kvm_memory_slot.
8402 */
8403 if (change != KVM_MR_DELETE)
8404 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8405 }
8406
8407 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8408 {
8409 kvm_mmu_invalidate_zap_all_pages(kvm);
8410 }
8411
8412 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8413 struct kvm_memory_slot *slot)
8414 {
8415 kvm_page_track_flush_slot(kvm, slot);
8416 }
8417
8418 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8419 {
8420 if (!list_empty_careful(&vcpu->async_pf.done))
8421 return true;
8422
8423 if (kvm_apic_has_events(vcpu))
8424 return true;
8425
8426 if (vcpu->arch.pv.pv_unhalted)
8427 return true;
8428
8429 if (atomic_read(&vcpu->arch.nmi_queued))
8430 return true;
8431
8432 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8433 return true;
8434
8435 if (kvm_arch_interrupt_allowed(vcpu) &&
8436 kvm_cpu_has_interrupt(vcpu))
8437 return true;
8438
8439 if (kvm_hv_has_stimer_pending(vcpu))
8440 return true;
8441
8442 return false;
8443 }
8444
8445 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8446 {
8447 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8448 }
8449
8450 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8451 {
8452 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8453 }
8454
8455 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8456 {
8457 return kvm_x86_ops->interrupt_allowed(vcpu);
8458 }
8459
8460 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8461 {
8462 if (is_64_bit_mode(vcpu))
8463 return kvm_rip_read(vcpu);
8464 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8465 kvm_rip_read(vcpu));
8466 }
8467 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8468
8469 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8470 {
8471 return kvm_get_linear_rip(vcpu) == linear_rip;
8472 }
8473 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8474
8475 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8476 {
8477 unsigned long rflags;
8478
8479 rflags = kvm_x86_ops->get_rflags(vcpu);
8480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8481 rflags &= ~X86_EFLAGS_TF;
8482 return rflags;
8483 }
8484 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8485
8486 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8487 {
8488 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8489 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8490 rflags |= X86_EFLAGS_TF;
8491 kvm_x86_ops->set_rflags(vcpu, rflags);
8492 }
8493
8494 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8495 {
8496 __kvm_set_rflags(vcpu, rflags);
8497 kvm_make_request(KVM_REQ_EVENT, vcpu);
8498 }
8499 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8500
8501 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8502 {
8503 int r;
8504
8505 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8506 work->wakeup_all)
8507 return;
8508
8509 r = kvm_mmu_reload(vcpu);
8510 if (unlikely(r))
8511 return;
8512
8513 if (!vcpu->arch.mmu.direct_map &&
8514 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8515 return;
8516
8517 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8518 }
8519
8520 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8521 {
8522 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8523 }
8524
8525 static inline u32 kvm_async_pf_next_probe(u32 key)
8526 {
8527 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8528 }
8529
8530 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8531 {
8532 u32 key = kvm_async_pf_hash_fn(gfn);
8533
8534 while (vcpu->arch.apf.gfns[key] != ~0)
8535 key = kvm_async_pf_next_probe(key);
8536
8537 vcpu->arch.apf.gfns[key] = gfn;
8538 }
8539
8540 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8541 {
8542 int i;
8543 u32 key = kvm_async_pf_hash_fn(gfn);
8544
8545 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8546 (vcpu->arch.apf.gfns[key] != gfn &&
8547 vcpu->arch.apf.gfns[key] != ~0); i++)
8548 key = kvm_async_pf_next_probe(key);
8549
8550 return key;
8551 }
8552
8553 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8554 {
8555 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8556 }
8557
8558 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8559 {
8560 u32 i, j, k;
8561
8562 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8563 while (true) {
8564 vcpu->arch.apf.gfns[i] = ~0;
8565 do {
8566 j = kvm_async_pf_next_probe(j);
8567 if (vcpu->arch.apf.gfns[j] == ~0)
8568 return;
8569 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8570 /*
8571 * k lies cyclically in ]i,j]
8572 * | i.k.j |
8573 * |....j i.k.| or |.k..j i...|
8574 */
8575 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8576 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8577 i = j;
8578 }
8579 }
8580
8581 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8582 {
8583
8584 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8585 sizeof(val));
8586 }
8587
8588 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8589 struct kvm_async_pf *work)
8590 {
8591 struct x86_exception fault;
8592
8593 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8594 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8595
8596 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8597 (vcpu->arch.apf.send_user_only &&
8598 kvm_x86_ops->get_cpl(vcpu) == 0))
8599 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8600 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8601 fault.vector = PF_VECTOR;
8602 fault.error_code_valid = true;
8603 fault.error_code = 0;
8604 fault.nested_page_fault = false;
8605 fault.address = work->arch.token;
8606 kvm_inject_page_fault(vcpu, &fault);
8607 }
8608 }
8609
8610 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8611 struct kvm_async_pf *work)
8612 {
8613 struct x86_exception fault;
8614
8615 if (work->wakeup_all)
8616 work->arch.token = ~0; /* broadcast wakeup */
8617 else
8618 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8619 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8620
8621 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8622 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8623 fault.vector = PF_VECTOR;
8624 fault.error_code_valid = true;
8625 fault.error_code = 0;
8626 fault.nested_page_fault = false;
8627 fault.address = work->arch.token;
8628 kvm_inject_page_fault(vcpu, &fault);
8629 }
8630 vcpu->arch.apf.halted = false;
8631 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8632 }
8633
8634 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8635 {
8636 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8637 return true;
8638 else
8639 return kvm_can_do_async_pf(vcpu);
8640 }
8641
8642 void kvm_arch_start_assignment(struct kvm *kvm)
8643 {
8644 atomic_inc(&kvm->arch.assigned_device_count);
8645 }
8646 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8647
8648 void kvm_arch_end_assignment(struct kvm *kvm)
8649 {
8650 atomic_dec(&kvm->arch.assigned_device_count);
8651 }
8652 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8653
8654 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8655 {
8656 return atomic_read(&kvm->arch.assigned_device_count);
8657 }
8658 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8659
8660 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8661 {
8662 atomic_inc(&kvm->arch.noncoherent_dma_count);
8663 }
8664 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8665
8666 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8667 {
8668 atomic_dec(&kvm->arch.noncoherent_dma_count);
8669 }
8670 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8671
8672 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8673 {
8674 return atomic_read(&kvm->arch.noncoherent_dma_count);
8675 }
8676 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8677
8678 bool kvm_arch_has_irq_bypass(void)
8679 {
8680 return kvm_x86_ops->update_pi_irte != NULL;
8681 }
8682
8683 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8684 struct irq_bypass_producer *prod)
8685 {
8686 struct kvm_kernel_irqfd *irqfd =
8687 container_of(cons, struct kvm_kernel_irqfd, consumer);
8688
8689 irqfd->producer = prod;
8690
8691 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8692 prod->irq, irqfd->gsi, 1);
8693 }
8694
8695 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8696 struct irq_bypass_producer *prod)
8697 {
8698 int ret;
8699 struct kvm_kernel_irqfd *irqfd =
8700 container_of(cons, struct kvm_kernel_irqfd, consumer);
8701
8702 WARN_ON(irqfd->producer != prod);
8703 irqfd->producer = NULL;
8704
8705 /*
8706 * When producer of consumer is unregistered, we change back to
8707 * remapped mode, so we can re-use the current implementation
8708 * when the irq is masked/disabled or the consumer side (KVM
8709 * int this case doesn't want to receive the interrupts.
8710 */
8711 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8712 if (ret)
8713 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8714 " fails: %d\n", irqfd->consumer.token, ret);
8715 }
8716
8717 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8718 uint32_t guest_irq, bool set)
8719 {
8720 if (!kvm_x86_ops->update_pi_irte)
8721 return -EINVAL;
8722
8723 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8724 }
8725
8726 bool kvm_vector_hashing_enabled(void)
8727 {
8728 return vector_hashing;
8729 }
8730 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8731
8732 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8733 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8734 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8735 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8736 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8737 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8738 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8739 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8740 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8741 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8742 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8743 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8744 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8745 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8746 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8747 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8748 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8749 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8750 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux with added FPC-III support