2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 #include <linux/gpio.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/gpio-davinci.h>
25 #include <linux/irqchip/chained_irq.h>
27 struct davinci_gpio_regs
{
40 typedef struct irq_chip
*(*gpio_get_irq_chip_cb_t
)(unsigned int irq
);
42 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43 #define MAX_LABEL_SIZE 20
45 static void __iomem
*gpio_base
;
46 static unsigned int offset_array
[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
48 static inline struct davinci_gpio_regs __iomem
*irq2regs(struct irq_data
*d
)
50 struct davinci_gpio_regs __iomem
*g
;
52 g
= (__force
struct davinci_gpio_regs __iomem
*)irq_data_get_irq_chip_data(d
);
57 static int davinci_gpio_irq_setup(struct platform_device
*pdev
);
59 /*--------------------------------------------------------------------------*/
61 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
62 static inline int __davinci_direction(struct gpio_chip
*chip
,
63 unsigned offset
, bool out
, int value
)
65 struct davinci_gpio_controller
*d
= gpiochip_get_data(chip
);
66 struct davinci_gpio_regs __iomem
*g
;
69 int bank
= offset
/ 32;
70 u32 mask
= __gpio_mask(offset
);
73 spin_lock_irqsave(&d
->lock
, flags
);
74 temp
= readl_relaxed(&g
->dir
);
77 writel_relaxed(mask
, value
? &g
->set_data
: &g
->clr_data
);
81 writel_relaxed(temp
, &g
->dir
);
82 spin_unlock_irqrestore(&d
->lock
, flags
);
87 static int davinci_direction_in(struct gpio_chip
*chip
, unsigned offset
)
89 return __davinci_direction(chip
, offset
, false, 0);
93 davinci_direction_out(struct gpio_chip
*chip
, unsigned offset
, int value
)
95 return __davinci_direction(chip
, offset
, true, value
);
99 * Read the pin's value (works even if it's set up as output);
100 * returns zero/nonzero.
102 * Note that changes are synched to the GPIO clock, so reading values back
103 * right after you've set them may give old values.
105 static int davinci_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
107 struct davinci_gpio_controller
*d
= gpiochip_get_data(chip
);
108 struct davinci_gpio_regs __iomem
*g
;
109 int bank
= offset
/ 32;
113 return !!(__gpio_mask(offset
) & readl_relaxed(&g
->in_data
));
117 * Assuming the pin is muxed as a gpio output, set its output value.
120 davinci_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
122 struct davinci_gpio_controller
*d
= gpiochip_get_data(chip
);
123 struct davinci_gpio_regs __iomem
*g
;
124 int bank
= offset
/ 32;
128 writel_relaxed(__gpio_mask(offset
),
129 value
? &g
->set_data
: &g
->clr_data
);
132 static struct davinci_gpio_platform_data
*
133 davinci_gpio_get_pdata(struct platform_device
*pdev
)
135 struct device_node
*dn
= pdev
->dev
.of_node
;
136 struct davinci_gpio_platform_data
*pdata
;
140 if (!IS_ENABLED(CONFIG_OF
) || !pdev
->dev
.of_node
)
141 return dev_get_platdata(&pdev
->dev
);
143 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
147 ret
= of_property_read_u32(dn
, "ti,ngpio", &val
);
153 ret
= of_property_read_u32(dn
, "ti,davinci-gpio-unbanked", &val
);
157 pdata
->gpio_unbanked
= val
;
162 dev_err(&pdev
->dev
, "Populating pdata from DT failed: err %d\n", ret
);
166 static int davinci_gpio_probe(struct platform_device
*pdev
)
168 static int ctrl_num
, bank_base
;
170 unsigned ngpio
, nbank
;
171 struct davinci_gpio_controller
*chips
;
172 struct davinci_gpio_platform_data
*pdata
;
173 struct device
*dev
= &pdev
->dev
;
174 struct resource
*res
;
175 char label
[MAX_LABEL_SIZE
];
177 pdata
= davinci_gpio_get_pdata(pdev
);
179 dev_err(dev
, "No platform data found\n");
183 dev
->platform_data
= pdata
;
186 * The gpio banks conceptually expose a segmented bitmap,
187 * and "ngpio" is one more than the largest zero-based
188 * bit index that's valid.
190 ngpio
= pdata
->ngpio
;
192 dev_err(dev
, "How many GPIOs?\n");
196 if (WARN_ON(ARCH_NR_GPIOS
< ngpio
))
197 ngpio
= ARCH_NR_GPIOS
;
199 nbank
= DIV_ROUND_UP(ngpio
, 32);
200 chips
= devm_kzalloc(dev
,
201 nbank
* sizeof(struct davinci_gpio_controller
),
206 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
207 gpio_base
= devm_ioremap_resource(dev
, res
);
208 if (IS_ERR(gpio_base
))
209 return PTR_ERR(gpio_base
);
211 snprintf(label
, MAX_LABEL_SIZE
, "davinci_gpio.%d", ctrl_num
++);
212 chips
->chip
.label
= devm_kstrdup(dev
, label
, GFP_KERNEL
);
213 if (!chips
->chip
.label
)
216 chips
->chip
.direction_input
= davinci_direction_in
;
217 chips
->chip
.get
= davinci_gpio_get
;
218 chips
->chip
.direction_output
= davinci_direction_out
;
219 chips
->chip
.set
= davinci_gpio_set
;
221 chips
->chip
.ngpio
= ngpio
;
222 chips
->chip
.base
= bank_base
;
224 #ifdef CONFIG_OF_GPIO
225 chips
->chip
.of_gpio_n_cells
= 2;
226 chips
->chip
.parent
= dev
;
227 chips
->chip
.of_node
= dev
->of_node
;
229 spin_lock_init(&chips
->lock
);
232 for (gpio
= 0, bank
= 0; gpio
< ngpio
; gpio
+= 32, bank
++)
233 chips
->regs
[bank
] = gpio_base
+ offset_array
[bank
];
235 gpiochip_add_data(&chips
->chip
, chips
);
236 platform_set_drvdata(pdev
, chips
);
237 davinci_gpio_irq_setup(pdev
);
241 /*--------------------------------------------------------------------------*/
243 * We expect irqs will normally be set up as input pins, but they can also be
244 * used as output pins ... which is convenient for testing.
246 * NOTE: The first few GPIOs also have direct INTC hookups in addition
247 * to their GPIOBNK0 irq, with a bit less overhead.
249 * All those INTC hookups (direct, plus several IRQ banks) can also
250 * serve as EDMA event triggers.
253 static void gpio_irq_disable(struct irq_data
*d
)
255 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
);
256 u32 mask
= (u32
) irq_data_get_irq_handler_data(d
);
258 writel_relaxed(mask
, &g
->clr_falling
);
259 writel_relaxed(mask
, &g
->clr_rising
);
262 static void gpio_irq_enable(struct irq_data
*d
)
264 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
);
265 u32 mask
= (u32
) irq_data_get_irq_handler_data(d
);
266 unsigned status
= irqd_get_trigger_type(d
);
268 status
&= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
270 status
= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
272 if (status
& IRQ_TYPE_EDGE_FALLING
)
273 writel_relaxed(mask
, &g
->set_falling
);
274 if (status
& IRQ_TYPE_EDGE_RISING
)
275 writel_relaxed(mask
, &g
->set_rising
);
278 static int gpio_irq_type(struct irq_data
*d
, unsigned trigger
)
280 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
286 static struct irq_chip gpio_irqchip
= {
288 .irq_enable
= gpio_irq_enable
,
289 .irq_disable
= gpio_irq_disable
,
290 .irq_set_type
= gpio_irq_type
,
291 .flags
= IRQCHIP_SET_TYPE_MASKED
,
294 static void gpio_irq_handler(struct irq_desc
*desc
)
296 struct davinci_gpio_regs __iomem
*g
;
299 struct davinci_gpio_controller
*d
;
300 struct davinci_gpio_irq_data
*irqdata
;
302 irqdata
= (struct davinci_gpio_irq_data
*)irq_desc_get_handler_data(desc
);
303 bank_num
= irqdata
->bank_num
;
307 /* we only care about one bank */
308 if ((bank_num
% 2) == 1)
311 /* temporarily mask (level sensitive) parent IRQ */
312 chained_irq_enter(irq_desc_get_chip(desc
), desc
);
316 irq_hw_number_t hw_irq
;
319 status
= readl_relaxed(&g
->intstat
) & mask
;
322 writel_relaxed(status
, &g
->intstat
);
324 /* now demux them to the right lowlevel handler */
329 /* Max number of gpios per controller is 144 so
330 * hw_irq will be in [0..143]
332 hw_irq
= (bank_num
/ 2) * 32 + bit
;
335 irq_find_mapping(d
->irq_domain
, hw_irq
));
338 chained_irq_exit(irq_desc_get_chip(desc
), desc
);
339 /* now it may re-trigger */
342 static int gpio_to_irq_banked(struct gpio_chip
*chip
, unsigned offset
)
344 struct davinci_gpio_controller
*d
= gpiochip_get_data(chip
);
347 return irq_create_mapping(d
->irq_domain
, offset
);
352 static int gpio_to_irq_unbanked(struct gpio_chip
*chip
, unsigned offset
)
354 struct davinci_gpio_controller
*d
= gpiochip_get_data(chip
);
357 * NOTE: we assume for now that only irqs in the first gpio_chip
358 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
360 if (offset
< d
->gpio_unbanked
)
361 return d
->base_irq
+ offset
;
366 static int gpio_irq_type_unbanked(struct irq_data
*data
, unsigned trigger
)
368 struct davinci_gpio_controller
*d
;
369 struct davinci_gpio_regs __iomem
*g
;
372 d
= (struct davinci_gpio_controller
*)irq_data_get_irq_handler_data(data
);
373 g
= (struct davinci_gpio_regs __iomem
*)d
->regs
;
374 mask
= __gpio_mask(data
->irq
- d
->base_irq
);
376 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
379 writel_relaxed(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
380 ? &g
->set_falling
: &g
->clr_falling
);
381 writel_relaxed(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
382 ? &g
->set_rising
: &g
->clr_rising
);
388 davinci_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
391 struct davinci_gpio_controller
*chips
=
392 (struct davinci_gpio_controller
*)d
->host_data
;
393 struct davinci_gpio_regs __iomem
*g
= chips
->regs
[hw
/ 32];
395 irq_set_chip_and_handler_name(irq
, &gpio_irqchip
, handle_simple_irq
,
397 irq_set_irq_type(irq
, IRQ_TYPE_NONE
);
398 irq_set_chip_data(irq
, (__force
void *)g
);
399 irq_set_handler_data(irq
, (void *)__gpio_mask(hw
));
404 static const struct irq_domain_ops davinci_gpio_irq_ops
= {
405 .map
= davinci_gpio_irq_map
,
406 .xlate
= irq_domain_xlate_onetwocell
,
409 static struct irq_chip
*davinci_gpio_get_irq_chip(unsigned int irq
)
411 static struct irq_chip_type gpio_unbanked
;
413 gpio_unbanked
= *irq_data_get_chip_type(irq_get_irq_data(irq
));
415 return &gpio_unbanked
.chip
;
418 static struct irq_chip
*keystone_gpio_get_irq_chip(unsigned int irq
)
420 static struct irq_chip gpio_unbanked
;
422 gpio_unbanked
= *irq_get_chip(irq
);
423 return &gpio_unbanked
;
426 static const struct of_device_id davinci_gpio_ids
[];
429 * NOTE: for suspend/resume, probably best to make a platform_device with
430 * suspend_late/resume_resume calls hooking into results of the set_wake()
431 * calls ... so if no gpios are wakeup events the clock can be disabled,
432 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
433 * (dm6446) can be set appropriately for GPIOV33 pins.
436 static int davinci_gpio_irq_setup(struct platform_device
*pdev
)
442 unsigned ngpio
, bank_irq
;
443 struct device
*dev
= &pdev
->dev
;
444 struct resource
*res
;
445 struct davinci_gpio_controller
*chips
= platform_get_drvdata(pdev
);
446 struct davinci_gpio_platform_data
*pdata
= dev
->platform_data
;
447 struct davinci_gpio_regs __iomem
*g
;
448 struct irq_domain
*irq_domain
= NULL
;
449 const struct of_device_id
*match
;
450 struct irq_chip
*irq_chip
;
451 struct davinci_gpio_irq_data
*irqdata
;
452 gpio_get_irq_chip_cb_t gpio_get_irq_chip
;
455 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
457 gpio_get_irq_chip
= davinci_gpio_get_irq_chip
;
458 match
= of_match_device(of_match_ptr(davinci_gpio_ids
),
461 gpio_get_irq_chip
= (gpio_get_irq_chip_cb_t
)match
->data
;
463 ngpio
= pdata
->ngpio
;
464 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
466 dev_err(dev
, "Invalid IRQ resource\n");
470 bank_irq
= res
->start
;
473 dev_err(dev
, "Invalid IRQ resource\n");
477 clk
= devm_clk_get(dev
, "gpio");
479 printk(KERN_ERR
"Error %ld getting gpio clock?\n",
483 clk_prepare_enable(clk
);
485 if (!pdata
->gpio_unbanked
) {
486 irq
= irq_alloc_descs(-1, 0, ngpio
, 0);
488 dev_err(dev
, "Couldn't allocate IRQ numbers\n");
492 irq_domain
= irq_domain_add_legacy(dev
->of_node
, ngpio
, irq
, 0,
493 &davinci_gpio_irq_ops
,
496 dev_err(dev
, "Couldn't register an IRQ domain\n");
502 * Arrange gpio_to_irq() support, handling either direct IRQs or
503 * banked IRQs. Having GPIOs in the first GPIO bank use direct
504 * IRQs, while the others use banked IRQs, would need some setup
505 * tweaks to recognize hardware which can do that.
507 chips
->chip
.to_irq
= gpio_to_irq_banked
;
508 chips
->irq_domain
= irq_domain
;
511 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
512 * controller only handling trigger modes. We currently assume no
513 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
515 if (pdata
->gpio_unbanked
) {
516 /* pass "bank 0" GPIO IRQs to AINTC */
517 chips
->chip
.to_irq
= gpio_to_irq_unbanked
;
518 chips
->base_irq
= bank_irq
;
519 chips
->gpio_unbanked
= pdata
->gpio_unbanked
;
520 binten
= GENMASK(pdata
->gpio_unbanked
/ 16, 0);
522 /* AINTC handles mask/unmask; GPIO handles triggering */
524 irq_chip
= gpio_get_irq_chip(irq
);
525 irq_chip
->name
= "GPIO-AINTC";
526 irq_chip
->irq_set_type
= gpio_irq_type_unbanked
;
528 /* default trigger: both edges */
530 writel_relaxed(~0, &g
->set_falling
);
531 writel_relaxed(~0, &g
->set_rising
);
533 /* set the direct IRQs up to use that irqchip */
534 for (gpio
= 0; gpio
< pdata
->gpio_unbanked
; gpio
++, irq
++) {
535 irq_set_chip(irq
, irq_chip
);
536 irq_set_handler_data(irq
, chips
);
537 irq_set_status_flags(irq
, IRQ_TYPE_EDGE_BOTH
);
544 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
545 * then chain through our own handler.
547 for (gpio
= 0, bank
= 0; gpio
< ngpio
; bank
++, bank_irq
++, gpio
+= 16) {
548 /* disabled by default, enabled only as needed
549 * There are register sets for 32 GPIOs. 2 banks of 16
550 * GPIOs are covered by each set of registers hence divide by 2
552 g
= chips
->regs
[bank
/ 2];
553 writel_relaxed(~0, &g
->clr_falling
);
554 writel_relaxed(~0, &g
->clr_rising
);
557 * Each chip handles 32 gpios, and each irq bank consists of 16
558 * gpio irqs. Pass the irq bank's corresponding controller to
559 * the chained irq handler.
561 irqdata
= devm_kzalloc(&pdev
->dev
,
563 davinci_gpio_irq_data
),
569 irqdata
->bank_num
= bank
;
570 irqdata
->chip
= chips
;
572 irq_set_chained_handler_and_data(bank_irq
, gpio_irq_handler
,
580 * BINTEN -- per-bank interrupt enable. genirq would also let these
581 * bits be set/cleared dynamically.
583 writel_relaxed(binten
, gpio_base
+ BINTEN
);
588 #if IS_ENABLED(CONFIG_OF)
589 static const struct of_device_id davinci_gpio_ids
[] = {
590 { .compatible
= "ti,keystone-gpio", keystone_gpio_get_irq_chip
},
591 { .compatible
= "ti,dm6441-gpio", davinci_gpio_get_irq_chip
},
594 MODULE_DEVICE_TABLE(of
, davinci_gpio_ids
);
597 static struct platform_driver davinci_gpio_driver
= {
598 .probe
= davinci_gpio_probe
,
600 .name
= "davinci_gpio",
601 .of_match_table
= of_match_ptr(davinci_gpio_ids
),
606 * GPIO driver registration needs to be done before machine_init functions
607 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
609 static int __init
davinci_gpio_drv_reg(void)
611 return platform_driver_register(&davinci_gpio_driver
);
613 postcore_initcall(davinci_gpio_drv_reg
);