2 * arch/arm/mach-tegra/gpio.c
4 * Copyright (c) 2010 Google, Inc
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
25 #include <linux/gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
60 #define GPIO_INT_LVL_MASK 0x010101
61 #define GPIO_INT_LVL_EDGE_RISING 0x000101
62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
67 struct tegra_gpio_info
;
69 struct tegra_gpio_bank
{
72 spinlock_t lvl_lock
[4];
73 spinlock_t dbc_lock
[4]; /* Lock for updating debounce count register */
74 #ifdef CONFIG_PM_SLEEP
84 struct tegra_gpio_info
*tgi
;
87 struct tegra_gpio_soc_config
{
88 bool debounce_supported
;
93 struct tegra_gpio_info
{
96 struct irq_domain
*irq_domain
;
97 struct tegra_gpio_bank
*bank_info
;
98 const struct tegra_gpio_soc_config
*soc
;
104 static inline void tegra_gpio_writel(struct tegra_gpio_info
*tgi
,
107 __raw_writel(val
, tgi
->regs
+ reg
);
110 static inline u32
tegra_gpio_readl(struct tegra_gpio_info
*tgi
, u32 reg
)
112 return __raw_readl(tgi
->regs
+ reg
);
115 static int tegra_gpio_compose(int bank
, int port
, int bit
)
117 return (bank
<< 5) | ((port
& 0x3) << 3) | (bit
& 0x7);
120 static void tegra_gpio_mask_write(struct tegra_gpio_info
*tgi
, u32 reg
,
125 val
= 0x100 << GPIO_BIT(gpio
);
127 val
|= 1 << GPIO_BIT(gpio
);
128 tegra_gpio_writel(tgi
, val
, reg
);
131 static void tegra_gpio_enable(struct tegra_gpio_info
*tgi
, int gpio
)
133 tegra_gpio_mask_write(tgi
, GPIO_MSK_CNF(tgi
, gpio
), gpio
, 1);
136 static void tegra_gpio_disable(struct tegra_gpio_info
*tgi
, int gpio
)
138 tegra_gpio_mask_write(tgi
, GPIO_MSK_CNF(tgi
, gpio
), gpio
, 0);
141 static int tegra_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
143 return pinctrl_request_gpio(offset
);
146 static void tegra_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
148 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
150 pinctrl_free_gpio(offset
);
151 tegra_gpio_disable(tgi
, offset
);
154 static void tegra_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
156 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
158 tegra_gpio_mask_write(tgi
, GPIO_MSK_OUT(tgi
, offset
), offset
, value
);
161 static int tegra_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
163 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
164 int bval
= BIT(GPIO_BIT(offset
));
166 /* If gpio is in output mode then read from the out value */
167 if (tegra_gpio_readl(tgi
, GPIO_OE(tgi
, offset
)) & bval
)
168 return !!(tegra_gpio_readl(tgi
, GPIO_OUT(tgi
, offset
)) & bval
);
170 return !!(tegra_gpio_readl(tgi
, GPIO_IN(tgi
, offset
)) & bval
);
173 static int tegra_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
175 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
177 tegra_gpio_mask_write(tgi
, GPIO_MSK_OE(tgi
, offset
), offset
, 0);
178 tegra_gpio_enable(tgi
, offset
);
182 static int tegra_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
185 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
187 tegra_gpio_set(chip
, offset
, value
);
188 tegra_gpio_mask_write(tgi
, GPIO_MSK_OE(tgi
, offset
), offset
, 1);
189 tegra_gpio_enable(tgi
, offset
);
193 static int tegra_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
195 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
196 u32 pin_mask
= BIT(GPIO_BIT(offset
));
199 cnf
= tegra_gpio_readl(tgi
, GPIO_CNF(tgi
, offset
));
200 if (!(cnf
& pin_mask
))
203 oe
= tegra_gpio_readl(tgi
, GPIO_OE(tgi
, offset
));
205 return (oe
& pin_mask
) ? GPIOF_DIR_OUT
: GPIOF_DIR_IN
;
208 static int tegra_gpio_set_debounce(struct gpio_chip
*chip
, unsigned int offset
,
209 unsigned int debounce
)
211 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
212 struct tegra_gpio_bank
*bank
= &tgi
->bank_info
[GPIO_BANK(offset
)];
213 unsigned int debounce_ms
= DIV_ROUND_UP(debounce
, 1000);
218 tegra_gpio_mask_write(tgi
, GPIO_MSK_DBC_EN(tgi
, offset
),
223 debounce_ms
= min(debounce_ms
, 255U);
224 port
= GPIO_PORT(offset
);
226 /* There is only one debounce count register per port and hence
227 * set the maximum of current and requested debounce time.
229 spin_lock_irqsave(&bank
->dbc_lock
[port
], flags
);
230 if (bank
->dbc_cnt
[port
] < debounce_ms
) {
231 tegra_gpio_writel(tgi
, debounce_ms
, GPIO_DBC_CNT(tgi
, offset
));
232 bank
->dbc_cnt
[port
] = debounce_ms
;
234 spin_unlock_irqrestore(&bank
->dbc_lock
[port
], flags
);
236 tegra_gpio_mask_write(tgi
, GPIO_MSK_DBC_EN(tgi
, offset
), offset
, 1);
241 static int tegra_gpio_set_config(struct gpio_chip
*chip
, unsigned int offset
,
242 unsigned long config
)
246 if (pinconf_to_config_param(config
) != PIN_CONFIG_INPUT_DEBOUNCE
)
249 debounce
= pinconf_to_config_argument(config
);
250 return tegra_gpio_set_debounce(chip
, offset
, debounce
);
253 static int tegra_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
255 struct tegra_gpio_info
*tgi
= gpiochip_get_data(chip
);
257 return irq_find_mapping(tgi
->irq_domain
, offset
);
260 static void tegra_gpio_irq_ack(struct irq_data
*d
)
262 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
263 struct tegra_gpio_info
*tgi
= bank
->tgi
;
266 tegra_gpio_writel(tgi
, 1 << GPIO_BIT(gpio
), GPIO_INT_CLR(tgi
, gpio
));
269 static void tegra_gpio_irq_mask(struct irq_data
*d
)
271 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
272 struct tegra_gpio_info
*tgi
= bank
->tgi
;
275 tegra_gpio_mask_write(tgi
, GPIO_MSK_INT_ENB(tgi
, gpio
), gpio
, 0);
278 static void tegra_gpio_irq_unmask(struct irq_data
*d
)
280 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
281 struct tegra_gpio_info
*tgi
= bank
->tgi
;
284 tegra_gpio_mask_write(tgi
, GPIO_MSK_INT_ENB(tgi
, gpio
), gpio
, 1);
287 static int tegra_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
290 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
291 struct tegra_gpio_info
*tgi
= bank
->tgi
;
292 int port
= GPIO_PORT(gpio
);
298 switch (type
& IRQ_TYPE_SENSE_MASK
) {
299 case IRQ_TYPE_EDGE_RISING
:
300 lvl_type
= GPIO_INT_LVL_EDGE_RISING
;
303 case IRQ_TYPE_EDGE_FALLING
:
304 lvl_type
= GPIO_INT_LVL_EDGE_FALLING
;
307 case IRQ_TYPE_EDGE_BOTH
:
308 lvl_type
= GPIO_INT_LVL_EDGE_BOTH
;
311 case IRQ_TYPE_LEVEL_HIGH
:
312 lvl_type
= GPIO_INT_LVL_LEVEL_HIGH
;
315 case IRQ_TYPE_LEVEL_LOW
:
316 lvl_type
= GPIO_INT_LVL_LEVEL_LOW
;
323 ret
= gpiochip_lock_as_irq(&tgi
->gc
, gpio
);
326 "unable to lock Tegra GPIO %d as IRQ\n", gpio
);
330 spin_lock_irqsave(&bank
->lvl_lock
[port
], flags
);
332 val
= tegra_gpio_readl(tgi
, GPIO_INT_LVL(tgi
, gpio
));
333 val
&= ~(GPIO_INT_LVL_MASK
<< GPIO_BIT(gpio
));
334 val
|= lvl_type
<< GPIO_BIT(gpio
);
335 tegra_gpio_writel(tgi
, val
, GPIO_INT_LVL(tgi
, gpio
));
337 spin_unlock_irqrestore(&bank
->lvl_lock
[port
], flags
);
339 tegra_gpio_mask_write(tgi
, GPIO_MSK_OE(tgi
, gpio
), gpio
, 0);
340 tegra_gpio_enable(tgi
, gpio
);
342 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
343 irq_set_handler_locked(d
, handle_level_irq
);
344 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
345 irq_set_handler_locked(d
, handle_edge_irq
);
350 static void tegra_gpio_irq_shutdown(struct irq_data
*d
)
352 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
353 struct tegra_gpio_info
*tgi
= bank
->tgi
;
356 gpiochip_unlock_as_irq(&tgi
->gc
, gpio
);
359 static void tegra_gpio_irq_handler(struct irq_desc
*desc
)
367 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
368 struct tegra_gpio_bank
*bank
= irq_desc_get_handler_data(desc
);
369 struct tegra_gpio_info
*tgi
= bank
->tgi
;
371 chained_irq_enter(chip
, desc
);
373 for (port
= 0; port
< 4; port
++) {
374 gpio
= tegra_gpio_compose(bank
->bank
, port
, 0);
375 sta
= tegra_gpio_readl(tgi
, GPIO_INT_STA(tgi
, gpio
)) &
376 tegra_gpio_readl(tgi
, GPIO_INT_ENB(tgi
, gpio
));
377 lvl
= tegra_gpio_readl(tgi
, GPIO_INT_LVL(tgi
, gpio
));
379 for_each_set_bit(pin
, &sta
, 8) {
380 tegra_gpio_writel(tgi
, 1 << pin
,
381 GPIO_INT_CLR(tgi
, gpio
));
383 /* if gpio is edge triggered, clear condition
384 * before executing the handler so that we don't
387 if (lvl
& (0x100 << pin
)) {
389 chained_irq_exit(chip
, desc
);
392 generic_handle_irq(gpio_to_irq(gpio
+ pin
));
397 chained_irq_exit(chip
, desc
);
401 #ifdef CONFIG_PM_SLEEP
402 static int tegra_gpio_resume(struct device
*dev
)
404 struct platform_device
*pdev
= to_platform_device(dev
);
405 struct tegra_gpio_info
*tgi
= platform_get_drvdata(pdev
);
410 local_irq_save(flags
);
412 for (b
= 0; b
< tgi
->bank_count
; b
++) {
413 struct tegra_gpio_bank
*bank
= &tgi
->bank_info
[b
];
415 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
416 unsigned int gpio
= (b
<<5) | (p
<<3);
417 tegra_gpio_writel(tgi
, bank
->cnf
[p
],
418 GPIO_CNF(tgi
, gpio
));
420 if (tgi
->soc
->debounce_supported
) {
421 tegra_gpio_writel(tgi
, bank
->dbc_cnt
[p
],
422 GPIO_DBC_CNT(tgi
, gpio
));
423 tegra_gpio_writel(tgi
, bank
->dbc_enb
[p
],
424 GPIO_MSK_DBC_EN(tgi
, gpio
));
427 tegra_gpio_writel(tgi
, bank
->out
[p
],
428 GPIO_OUT(tgi
, gpio
));
429 tegra_gpio_writel(tgi
, bank
->oe
[p
],
431 tegra_gpio_writel(tgi
, bank
->int_lvl
[p
],
432 GPIO_INT_LVL(tgi
, gpio
));
433 tegra_gpio_writel(tgi
, bank
->int_enb
[p
],
434 GPIO_INT_ENB(tgi
, gpio
));
438 local_irq_restore(flags
);
442 static int tegra_gpio_suspend(struct device
*dev
)
444 struct platform_device
*pdev
= to_platform_device(dev
);
445 struct tegra_gpio_info
*tgi
= platform_get_drvdata(pdev
);
450 local_irq_save(flags
);
451 for (b
= 0; b
< tgi
->bank_count
; b
++) {
452 struct tegra_gpio_bank
*bank
= &tgi
->bank_info
[b
];
454 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
455 unsigned int gpio
= (b
<<5) | (p
<<3);
456 bank
->cnf
[p
] = tegra_gpio_readl(tgi
,
457 GPIO_CNF(tgi
, gpio
));
458 bank
->out
[p
] = tegra_gpio_readl(tgi
,
459 GPIO_OUT(tgi
, gpio
));
460 bank
->oe
[p
] = tegra_gpio_readl(tgi
,
462 if (tgi
->soc
->debounce_supported
) {
463 bank
->dbc_enb
[p
] = tegra_gpio_readl(tgi
,
464 GPIO_MSK_DBC_EN(tgi
, gpio
));
465 bank
->dbc_enb
[p
] = (bank
->dbc_enb
[p
] << 8) |
469 bank
->int_enb
[p
] = tegra_gpio_readl(tgi
,
470 GPIO_INT_ENB(tgi
, gpio
));
471 bank
->int_lvl
[p
] = tegra_gpio_readl(tgi
,
472 GPIO_INT_LVL(tgi
, gpio
));
474 /* Enable gpio irq for wake up source */
475 tegra_gpio_writel(tgi
, bank
->wake_enb
[p
],
476 GPIO_INT_ENB(tgi
, gpio
));
479 local_irq_restore(flags
);
483 static int tegra_gpio_irq_set_wake(struct irq_data
*d
, unsigned int enable
)
485 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
489 port
= GPIO_PORT(gpio
);
490 bit
= GPIO_BIT(gpio
);
494 bank
->wake_enb
[port
] |= mask
;
496 bank
->wake_enb
[port
] &= ~mask
;
498 return irq_set_irq_wake(bank
->irq
, enable
);
502 #ifdef CONFIG_DEBUG_FS
504 #include <linux/debugfs.h>
505 #include <linux/seq_file.h>
507 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
509 struct tegra_gpio_info
*tgi
= s
->private;
513 for (i
= 0; i
< tgi
->bank_count
; i
++) {
514 for (j
= 0; j
< 4; j
++) {
515 int gpio
= tegra_gpio_compose(i
, j
, 0);
517 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
519 tegra_gpio_readl(tgi
, GPIO_CNF(tgi
, gpio
)),
520 tegra_gpio_readl(tgi
, GPIO_OE(tgi
, gpio
)),
521 tegra_gpio_readl(tgi
, GPIO_OUT(tgi
, gpio
)),
522 tegra_gpio_readl(tgi
, GPIO_IN(tgi
, gpio
)),
523 tegra_gpio_readl(tgi
, GPIO_INT_STA(tgi
, gpio
)),
524 tegra_gpio_readl(tgi
, GPIO_INT_ENB(tgi
, gpio
)),
525 tegra_gpio_readl(tgi
, GPIO_INT_LVL(tgi
, gpio
)));
531 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
533 return single_open(file
, dbg_gpio_show
, inode
->i_private
);
536 static const struct file_operations debug_fops
= {
537 .open
= dbg_gpio_open
,
540 .release
= single_release
,
543 static void tegra_gpio_debuginit(struct tegra_gpio_info
*tgi
)
545 (void) debugfs_create_file("tegra_gpio", S_IRUGO
,
546 NULL
, tgi
, &debug_fops
);
551 static inline void tegra_gpio_debuginit(struct tegra_gpio_info
*tgi
)
557 static const struct dev_pm_ops tegra_gpio_pm_ops
= {
558 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend
, tegra_gpio_resume
)
562 * This lock class tells lockdep that GPIO irqs are in a different category
563 * than their parents, so it won't report false recursion.
565 static struct lock_class_key gpio_lock_class
;
567 static int tegra_gpio_probe(struct platform_device
*pdev
)
569 const struct tegra_gpio_soc_config
*config
;
570 struct tegra_gpio_info
*tgi
;
571 struct resource
*res
;
572 struct tegra_gpio_bank
*bank
;
578 config
= of_device_get_match_data(&pdev
->dev
);
580 dev_err(&pdev
->dev
, "Error: No device match found\n");
584 tgi
= devm_kzalloc(&pdev
->dev
, sizeof(*tgi
), GFP_KERNEL
);
589 tgi
->dev
= &pdev
->dev
;
592 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
,
598 if (!tgi
->bank_count
) {
599 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
603 tgi
->gc
.label
= "tegra-gpio";
604 tgi
->gc
.request
= tegra_gpio_request
;
605 tgi
->gc
.free
= tegra_gpio_free
;
606 tgi
->gc
.direction_input
= tegra_gpio_direction_input
;
607 tgi
->gc
.get
= tegra_gpio_get
;
608 tgi
->gc
.direction_output
= tegra_gpio_direction_output
;
609 tgi
->gc
.set
= tegra_gpio_set
;
610 tgi
->gc
.get_direction
= tegra_gpio_get_direction
;
611 tgi
->gc
.to_irq
= tegra_gpio_to_irq
;
613 tgi
->gc
.ngpio
= tgi
->bank_count
* 32;
614 tgi
->gc
.parent
= &pdev
->dev
;
615 tgi
->gc
.of_node
= pdev
->dev
.of_node
;
617 tgi
->ic
.name
= "GPIO";
618 tgi
->ic
.irq_ack
= tegra_gpio_irq_ack
;
619 tgi
->ic
.irq_mask
= tegra_gpio_irq_mask
;
620 tgi
->ic
.irq_unmask
= tegra_gpio_irq_unmask
;
621 tgi
->ic
.irq_set_type
= tegra_gpio_irq_set_type
;
622 tgi
->ic
.irq_shutdown
= tegra_gpio_irq_shutdown
;
623 #ifdef CONFIG_PM_SLEEP
624 tgi
->ic
.irq_set_wake
= tegra_gpio_irq_set_wake
;
627 platform_set_drvdata(pdev
, tgi
);
629 if (config
->debounce_supported
)
630 tgi
->gc
.set_config
= tegra_gpio_set_config
;
632 tgi
->bank_info
= devm_kzalloc(&pdev
->dev
, tgi
->bank_count
*
633 sizeof(*tgi
->bank_info
), GFP_KERNEL
);
637 tgi
->irq_domain
= irq_domain_add_linear(pdev
->dev
.of_node
,
639 &irq_domain_simple_ops
, NULL
);
640 if (!tgi
->irq_domain
)
643 for (i
= 0; i
< tgi
->bank_count
; i
++) {
644 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
646 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
650 bank
= &tgi
->bank_info
[i
];
652 bank
->irq
= res
->start
;
656 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
657 tgi
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
658 if (IS_ERR(tgi
->regs
))
659 return PTR_ERR(tgi
->regs
);
661 for (i
= 0; i
< tgi
->bank_count
; i
++) {
662 for (j
= 0; j
< 4; j
++) {
663 int gpio
= tegra_gpio_compose(i
, j
, 0);
664 tegra_gpio_writel(tgi
, 0x00, GPIO_INT_ENB(tgi
, gpio
));
668 ret
= devm_gpiochip_add_data(&pdev
->dev
, &tgi
->gc
, tgi
);
670 irq_domain_remove(tgi
->irq_domain
);
674 for (gpio
= 0; gpio
< tgi
->gc
.ngpio
; gpio
++) {
675 int irq
= irq_create_mapping(tgi
->irq_domain
, gpio
);
676 /* No validity check; all Tegra GPIOs are valid IRQs */
678 bank
= &tgi
->bank_info
[GPIO_BANK(gpio
)];
680 irq_set_lockdep_class(irq
, &gpio_lock_class
);
681 irq_set_chip_data(irq
, bank
);
682 irq_set_chip_and_handler(irq
, &tgi
->ic
, handle_simple_irq
);
685 for (i
= 0; i
< tgi
->bank_count
; i
++) {
686 bank
= &tgi
->bank_info
[i
];
688 irq_set_chained_handler_and_data(bank
->irq
,
689 tegra_gpio_irq_handler
, bank
);
691 for (j
= 0; j
< 4; j
++) {
692 spin_lock_init(&bank
->lvl_lock
[j
]);
693 spin_lock_init(&bank
->dbc_lock
[j
]);
697 tegra_gpio_debuginit(tgi
);
702 static const struct tegra_gpio_soc_config tegra20_gpio_config
= {
704 .upper_offset
= 0x800,
707 static const struct tegra_gpio_soc_config tegra30_gpio_config
= {
708 .bank_stride
= 0x100,
709 .upper_offset
= 0x80,
712 static const struct tegra_gpio_soc_config tegra210_gpio_config
= {
713 .debounce_supported
= true,
714 .bank_stride
= 0x100,
715 .upper_offset
= 0x80,
718 static const struct of_device_id tegra_gpio_of_match
[] = {
719 { .compatible
= "nvidia,tegra210-gpio", .data
= &tegra210_gpio_config
},
720 { .compatible
= "nvidia,tegra30-gpio", .data
= &tegra30_gpio_config
},
721 { .compatible
= "nvidia,tegra20-gpio", .data
= &tegra20_gpio_config
},
725 static struct platform_driver tegra_gpio_driver
= {
727 .name
= "tegra-gpio",
728 .pm
= &tegra_gpio_pm_ops
,
729 .of_match_table
= tegra_gpio_of_match
,
731 .probe
= tegra_gpio_probe
,
734 static int __init
tegra_gpio_init(void)
736 return platform_driver_register(&tegra_gpio_driver
);
738 postcore_initcall(tegra_gpio_init
);