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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / media / platform / coda / coda-bit.c
blob466a44e4549e5e611d13a5b3d08f91571524301d
1 /*
2 * Coda multi-standard codec IP - BIT processor functions
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/log2.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-v4l2.h>
29 #include <media/videobuf2-dma-contig.h>
30 #include <media/videobuf2-vmalloc.h>
31
32 #include "coda.h"
33 #include "imx-vdoa.h"
34 #define CREATE_TRACE_POINTS
35 #include "trace.h"
36
37 #define CODA_PARA_BUF_SIZE (10 * 1024)
38 #define CODA7_PS_BUF_SIZE 0x28000
39 #define CODA9_PS_SAVE_SIZE (512 * 1024)
40
41 #define CODA_DEFAULT_GAMMA 4096
42 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
43
44 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
45
46 static inline int coda_is_initialized(struct coda_dev *dev)
47 {
48 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
49 }
50
51 static inline unsigned long coda_isbusy(struct coda_dev *dev)
52 {
53 return coda_read(dev, CODA_REG_BIT_BUSY);
54 }
55
56 static int coda_wait_timeout(struct coda_dev *dev)
57 {
58 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
59
60 while (coda_isbusy(dev)) {
61 if (time_after(jiffies, timeout))
62 return -ETIMEDOUT;
63 }
64 return 0;
65 }
66
67 static void coda_command_async(struct coda_ctx *ctx, int cmd)
68 {
69 struct coda_dev *dev = ctx->dev;
70
71 if (dev->devtype->product == CODA_960 ||
72 dev->devtype->product == CODA_7541) {
73 /* Restore context related registers to CODA */
74 coda_write(dev, ctx->bit_stream_param,
75 CODA_REG_BIT_BIT_STREAM_PARAM);
76 coda_write(dev, ctx->frm_dis_flg,
77 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
78 coda_write(dev, ctx->frame_mem_ctrl,
79 CODA_REG_BIT_FRAME_MEM_CTRL);
80 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
81 }
82
83 if (dev->devtype->product == CODA_960) {
84 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
85 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
86 }
87
88 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
89
90 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
91 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
92 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
93
94 trace_coda_bit_run(ctx, cmd);
95
96 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
97 }
98
99 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
100 {
101 struct coda_dev *dev = ctx->dev;
102 int ret;
103
104 coda_command_async(ctx, cmd);
105 ret = coda_wait_timeout(dev);
106 trace_coda_bit_done(ctx);
107
108 return ret;
109 }
110
111 int coda_hw_reset(struct coda_ctx *ctx)
112 {
113 struct coda_dev *dev = ctx->dev;
114 unsigned long timeout;
115 unsigned int idx;
116 int ret;
117
118 if (!dev->rstc)
119 return -ENOENT;
120
121 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
122
123 if (dev->devtype->product == CODA_960) {
124 timeout = jiffies + msecs_to_jiffies(100);
125 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
126 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
127 if (time_after(jiffies, timeout))
128 return -ETIME;
129 cpu_relax();
130 }
131 }
132
133 ret = reset_control_reset(dev->rstc);
134 if (ret < 0)
135 return ret;
136
137 if (dev->devtype->product == CODA_960)
138 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
139 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
140 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
141 ret = coda_wait_timeout(dev);
142 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
143
144 return ret;
145 }
146
147 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
148 {
149 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
150 struct coda_dev *dev = ctx->dev;
151 u32 rd_ptr;
152
153 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
154 kfifo->out = (kfifo->in & ~kfifo->mask) |
155 (rd_ptr - ctx->bitstream.paddr);
156 if (kfifo->out > kfifo->in)
157 kfifo->out -= kfifo->mask + 1;
158 }
159
160 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
161 {
162 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
163 struct coda_dev *dev = ctx->dev;
164 u32 rd_ptr, wr_ptr;
165
166 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
167 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
168 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
169 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
170 }
171
172 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
173 {
174 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
175 struct coda_dev *dev = ctx->dev;
176 u32 wr_ptr;
177
178 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
179 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
180 }
181
182 static int coda_bitstream_queue(struct coda_ctx *ctx,
183 struct vb2_v4l2_buffer *src_buf)
184 {
185 u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
186 u32 n;
187
188 n = kfifo_in(&ctx->bitstream_fifo,
189 vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
190 if (n < src_size)
191 return -ENOSPC;
192
193 src_buf->sequence = ctx->qsequence++;
194
195 return 0;
196 }
197
198 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
199 struct vb2_v4l2_buffer *src_buf)
200 {
201 int ret;
202
203 if (coda_get_bitstream_payload(ctx) +
204 vb2_get_plane_payload(&src_buf->vb2_buf, 0) + 512 >=
205 ctx->bitstream.size)
206 return false;
207
208 if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
209 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
210 return true;
211 }
212
213 ret = coda_bitstream_queue(ctx, src_buf);
214 if (ret < 0) {
215 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
216 return false;
217 }
218 /* Sync read pointer to device */
219 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
220 coda_kfifo_sync_to_device_write(ctx);
221
222 ctx->hold = false;
223
224 return true;
225 }
226
227 void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
228 {
229 struct vb2_v4l2_buffer *src_buf;
230 struct coda_buffer_meta *meta;
231 unsigned long flags;
232 u32 start;
233
234 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
235 return;
236
237 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
238 /*
239 * Only queue a single JPEG into the bitstream buffer, except
240 * to increase payload over 512 bytes or if in hold state.
241 */
242 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
243 (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
244 break;
245
246 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
247
248 /* Drop frames that do not start/end with a SOI/EOI markers */
249 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
250 !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
251 v4l2_err(&ctx->dev->v4l2_dev,
252 "dropping invalid JPEG frame %d\n",
253 ctx->qsequence);
254 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
255 v4l2_m2m_buf_done(src_buf, streaming ?
256 VB2_BUF_STATE_ERROR :
257 VB2_BUF_STATE_QUEUED);
258 continue;
259 }
260
261 /* Dump empty buffers */
262 if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
263 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
264 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
265 continue;
266 }
267
268 /* Buffer start position */
269 start = ctx->bitstream_fifo.kfifo.in &
270 ctx->bitstream_fifo.kfifo.mask;
271
272 if (coda_bitstream_try_queue(ctx, src_buf)) {
273 /*
274 * Source buffer is queued in the bitstream ringbuffer;
275 * queue the timestamp and mark source buffer as done
276 */
277 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
278
279 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
280 if (meta) {
281 meta->sequence = src_buf->sequence;
282 meta->timecode = src_buf->timecode;
283 meta->timestamp = src_buf->vb2_buf.timestamp;
284 meta->start = start;
285 meta->end = ctx->bitstream_fifo.kfifo.in &
286 ctx->bitstream_fifo.kfifo.mask;
287 spin_lock_irqsave(&ctx->buffer_meta_lock,
288 flags);
289 list_add_tail(&meta->list,
290 &ctx->buffer_meta_list);
291 ctx->num_metas++;
292 spin_unlock_irqrestore(&ctx->buffer_meta_lock,
293 flags);
294
295 trace_coda_bit_queue(ctx, src_buf, meta);
296 }
297
298 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
299 } else {
300 break;
301 }
302 }
303 }
304
305 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
306 {
307 struct coda_dev *dev = ctx->dev;
308
309 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
310
311 /* If this context is currently running, update the hardware flag */
312 if ((dev->devtype->product == CODA_960) &&
313 coda_isbusy(dev) &&
314 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
315 coda_write(dev, ctx->bit_stream_param,
316 CODA_REG_BIT_BIT_STREAM_PARAM);
317 }
318 }
319
320 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
321 {
322 struct coda_dev *dev = ctx->dev;
323 u32 *p = ctx->parabuf.vaddr;
324
325 if (dev->devtype->product == CODA_DX6)
326 p[index] = value;
327 else
328 p[index ^ 1] = value;
329 }
330
331 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
332 struct coda_aux_buf *buf, size_t size,
333 const char *name)
334 {
335 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
336 }
337
338
339 static void coda_free_framebuffers(struct coda_ctx *ctx)
340 {
341 int i;
342
343 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
344 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
345 }
346
347 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
348 struct coda_q_data *q_data, u32 fourcc)
349 {
350 struct coda_dev *dev = ctx->dev;
351 int width, height;
352 int ysize;
353 int ret;
354 int i;
355
356 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
357 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
358 width = round_up(q_data->width, 16);
359 height = round_up(q_data->height, 16);
360 } else {
361 width = round_up(q_data->width, 8);
362 height = q_data->height;
363 }
364 ysize = width * height;
365
366 /* Allocate frame buffers */
367 for (i = 0; i < ctx->num_internal_frames; i++) {
368 size_t size;
369 char *name;
370
371 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
372 size = round_up(ysize, 4096) + ysize / 2;
373 else
374 size = ysize + ysize / 2;
375 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
376 dev->devtype->product != CODA_DX6)
377 size += ysize / 4;
378 name = kasprintf(GFP_KERNEL, "fb%d", i);
379 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
380 size, name);
381 kfree(name);
382 if (ret < 0) {
383 coda_free_framebuffers(ctx);
384 return ret;
385 }
386 }
387
388 /* Register frame buffers in the parameter buffer */
389 for (i = 0; i < ctx->num_internal_frames; i++) {
390 u32 y, cb, cr;
391
392 /* Start addresses of Y, Cb, Cr planes */
393 y = ctx->internal_frames[i].paddr;
394 cb = y + ysize;
395 cr = y + ysize + ysize/4;
396 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
397 cb = round_up(cb, 4096);
398 cr = 0;
399 /* Packed 20-bit MSB of base addresses */
400 /* YYYYYCCC, CCyyyyyc, cccc.... */
401 y = (y & 0xfffff000) | cb >> 20;
402 cb = (cb & 0x000ff000) << 12;
403 }
404 coda_parabuf_write(ctx, i * 3 + 0, y);
405 coda_parabuf_write(ctx, i * 3 + 1, cb);
406 coda_parabuf_write(ctx, i * 3 + 2, cr);
407
408 /* mvcol buffer for h.264 */
409 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
410 dev->devtype->product != CODA_DX6)
411 coda_parabuf_write(ctx, 96 + i,
412 ctx->internal_frames[i].paddr +
413 ysize + ysize/4 + ysize/4);
414 }
415
416 /* mvcol buffer for mpeg4 */
417 if ((dev->devtype->product != CODA_DX6) &&
418 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
419 coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
420 ysize + ysize/4 + ysize/4);
421
422 return 0;
423 }
424
425 static void coda_free_context_buffers(struct coda_ctx *ctx)
426 {
427 struct coda_dev *dev = ctx->dev;
428
429 coda_free_aux_buf(dev, &ctx->slicebuf);
430 coda_free_aux_buf(dev, &ctx->psbuf);
431 if (dev->devtype->product != CODA_DX6)
432 coda_free_aux_buf(dev, &ctx->workbuf);
433 coda_free_aux_buf(dev, &ctx->parabuf);
434 }
435
436 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
437 struct coda_q_data *q_data)
438 {
439 struct coda_dev *dev = ctx->dev;
440 size_t size;
441 int ret;
442
443 if (!ctx->parabuf.vaddr) {
444 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
445 CODA_PARA_BUF_SIZE, "parabuf");
446 if (ret < 0)
447 return ret;
448 }
449
450 if (dev->devtype->product == CODA_DX6)
451 return 0;
452
453 if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
454 /* worst case slice size */
455 size = (DIV_ROUND_UP(q_data->width, 16) *
456 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
457 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
458 "slicebuf");
459 if (ret < 0)
460 goto err;
461 }
462
463 if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
464 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
465 CODA7_PS_BUF_SIZE, "psbuf");
466 if (ret < 0)
467 goto err;
468 }
469
470 if (!ctx->workbuf.vaddr) {
471 size = dev->devtype->workbuf_size;
472 if (dev->devtype->product == CODA_960 &&
473 q_data->fourcc == V4L2_PIX_FMT_H264)
474 size += CODA9_PS_SAVE_SIZE;
475 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
476 "workbuf");
477 if (ret < 0)
478 goto err;
479 }
480
481 return 0;
482
483 err:
484 coda_free_context_buffers(ctx);
485 return ret;
486 }
487
488 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
489 int header_code, u8 *header, int *size)
490 {
491 struct vb2_buffer *vb = &buf->vb2_buf;
492 struct coda_dev *dev = ctx->dev;
493 size_t bufsize;
494 int ret;
495 int i;
496
497 if (dev->devtype->product == CODA_960)
498 memset(vb2_plane_vaddr(vb, 0), 0, 64);
499
500 coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
501 CODA_CMD_ENC_HEADER_BB_START);
502 bufsize = vb2_plane_size(vb, 0);
503 if (dev->devtype->product == CODA_960)
504 bufsize /= 1024;
505 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
506 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
507 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
508 if (ret < 0) {
509 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
510 return ret;
511 }
512
513 if (dev->devtype->product == CODA_960) {
514 for (i = 63; i > 0; i--)
515 if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
516 break;
517 *size = i + 1;
518 } else {
519 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
520 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
521 }
522 memcpy(header, vb2_plane_vaddr(vb, 0), *size);
523
524 return 0;
525 }
526
527 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
528 {
529 phys_addr_t ret;
530
531 size = round_up(size, 1024);
532 if (size > iram->remaining)
533 return 0;
534 iram->remaining -= size;
535
536 ret = iram->next_paddr;
537 iram->next_paddr += size;
538
539 return ret;
540 }
541
542 static void coda_setup_iram(struct coda_ctx *ctx)
543 {
544 struct coda_iram_info *iram_info = &ctx->iram_info;
545 struct coda_dev *dev = ctx->dev;
546 int w64, w128;
547 int mb_width;
548 int dbk_bits;
549 int bit_bits;
550 int ip_bits;
551
552 memset(iram_info, 0, sizeof(*iram_info));
553 iram_info->next_paddr = dev->iram.paddr;
554 iram_info->remaining = dev->iram.size;
555
556 if (!dev->iram.vaddr)
557 return;
558
559 switch (dev->devtype->product) {
560 case CODA_7541:
561 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
562 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
563 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
564 break;
565 case CODA_960:
566 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
567 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
568 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
569 break;
570 default: /* CODA_DX6 */
571 return;
572 }
573
574 if (ctx->inst_type == CODA_INST_ENCODER) {
575 struct coda_q_data *q_data_src;
576
577 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
578 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
579 w128 = mb_width * 128;
580 w64 = mb_width * 64;
581
582 /* Prioritize in case IRAM is too small for everything */
583 if (dev->devtype->product == CODA_7541) {
584 iram_info->search_ram_size = round_up(mb_width * 16 *
585 36 + 2048, 1024);
586 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
587 iram_info->search_ram_size);
588 if (!iram_info->search_ram_paddr) {
589 pr_err("IRAM is smaller than the search ram size\n");
590 goto out;
591 }
592 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
593 CODA7_USE_ME_ENABLE;
594 }
595
596 /* Only H.264BP and H.263P3 are considered */
597 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
598 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
599 if (!iram_info->buf_dbk_c_use)
600 goto out;
601 iram_info->axi_sram_use |= dbk_bits;
602
603 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
604 if (!iram_info->buf_bit_use)
605 goto out;
606 iram_info->axi_sram_use |= bit_bits;
607
608 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
609 if (!iram_info->buf_ip_ac_dc_use)
610 goto out;
611 iram_info->axi_sram_use |= ip_bits;
612
613 /* OVL and BTP disabled for encoder */
614 } else if (ctx->inst_type == CODA_INST_DECODER) {
615 struct coda_q_data *q_data_dst;
616
617 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
618 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
619 w128 = mb_width * 128;
620
621 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
622 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
623 if (!iram_info->buf_dbk_c_use)
624 goto out;
625 iram_info->axi_sram_use |= dbk_bits;
626
627 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
628 if (!iram_info->buf_bit_use)
629 goto out;
630 iram_info->axi_sram_use |= bit_bits;
631
632 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
633 if (!iram_info->buf_ip_ac_dc_use)
634 goto out;
635 iram_info->axi_sram_use |= ip_bits;
636
637 /* OVL and BTP unused as there is no VC1 support yet */
638 }
639
640 out:
641 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
642 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
643 "IRAM smaller than needed\n");
644
645 if (dev->devtype->product == CODA_7541) {
646 /* TODO - Enabling these causes picture errors on CODA7541 */
647 if (ctx->inst_type == CODA_INST_DECODER) {
648 /* fw 1.4.50 */
649 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
650 CODA7_USE_IP_ENABLE);
651 } else {
652 /* fw 13.4.29 */
653 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
654 CODA7_USE_HOST_DBK_ENABLE |
655 CODA7_USE_IP_ENABLE |
656 CODA7_USE_DBK_ENABLE);
657 }
658 }
659 }
660
661 static u32 coda_supported_firmwares[] = {
662 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
663 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
664 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
665 };
666
667 static bool coda_firmware_supported(u32 vernum)
668 {
669 int i;
670
671 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
672 if (vernum == coda_supported_firmwares[i])
673 return true;
674 return false;
675 }
676
677 int coda_check_firmware(struct coda_dev *dev)
678 {
679 u16 product, major, minor, release;
680 u32 data;
681 int ret;
682
683 ret = clk_prepare_enable(dev->clk_per);
684 if (ret)
685 goto err_clk_per;
686
687 ret = clk_prepare_enable(dev->clk_ahb);
688 if (ret)
689 goto err_clk_ahb;
690
691 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
692 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
693 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
694 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
695 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
696 if (coda_wait_timeout(dev)) {
697 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
698 ret = -EIO;
699 goto err_run_cmd;
700 }
701
702 if (dev->devtype->product == CODA_960) {
703 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
704 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
705 data);
706 }
707
708 /* Check we are compatible with the loaded firmware */
709 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
710 product = CODA_FIRMWARE_PRODUCT(data);
711 major = CODA_FIRMWARE_MAJOR(data);
712 minor = CODA_FIRMWARE_MINOR(data);
713 release = CODA_FIRMWARE_RELEASE(data);
714
715 clk_disable_unprepare(dev->clk_per);
716 clk_disable_unprepare(dev->clk_ahb);
717
718 if (product != dev->devtype->product) {
719 v4l2_err(&dev->v4l2_dev,
720 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
721 coda_product_name(dev->devtype->product),
722 coda_product_name(product), major, minor, release);
723 return -EINVAL;
724 }
725
726 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
727 coda_product_name(product));
728
729 if (coda_firmware_supported(data)) {
730 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
731 major, minor, release);
732 } else {
733 v4l2_warn(&dev->v4l2_dev,
734 "Unsupported firmware version: %u.%u.%u\n",
735 major, minor, release);
736 }
737
738 return 0;
739
740 err_run_cmd:
741 clk_disable_unprepare(dev->clk_ahb);
742 err_clk_ahb:
743 clk_disable_unprepare(dev->clk_per);
744 err_clk_per:
745 return ret;
746 }
747
748 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
749 {
750 u32 cache_size, cache_config;
751
752 if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
753 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
754 cache_size = 0x20262024;
755 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
756 } else {
757 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
758 cache_size = 0x02440243;
759 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
760 }
761 coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
762 if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
763 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
764 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
765 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
766 } else {
767 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
768 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
769 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
770 }
771 coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
772 }
773
774 /*
775 * Encoder context operations
776 */
777
778 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
779 struct v4l2_requestbuffers *rb)
780 {
781 struct coda_q_data *q_data_src;
782 int ret;
783
784 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
785 return 0;
786
787 if (rb->count) {
788 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
789 ret = coda_alloc_context_buffers(ctx, q_data_src);
790 if (ret < 0)
791 return ret;
792 } else {
793 coda_free_context_buffers(ctx);
794 }
795
796 return 0;
797 }
798
799 static int coda_start_encoding(struct coda_ctx *ctx)
800 {
801 struct coda_dev *dev = ctx->dev;
802 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
803 struct coda_q_data *q_data_src, *q_data_dst;
804 u32 bitstream_buf, bitstream_size;
805 struct vb2_v4l2_buffer *buf;
806 int gamma, ret, value;
807 u32 dst_fourcc;
808 int num_fb;
809 u32 stride;
810
811 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
812 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
813 dst_fourcc = q_data_dst->fourcc;
814
815 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
816 bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
817 bitstream_size = q_data_dst->sizeimage;
818
819 if (!coda_is_initialized(dev)) {
820 v4l2_err(v4l2_dev, "coda is not initialized.\n");
821 return -EFAULT;
822 }
823
824 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
825 if (!ctx->params.jpeg_qmat_tab[0])
826 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
827 if (!ctx->params.jpeg_qmat_tab[1])
828 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
829 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
830 }
831
832 mutex_lock(&dev->coda_mutex);
833
834 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
835 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
836 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
837 switch (dev->devtype->product) {
838 case CODA_DX6:
839 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
840 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
841 break;
842 case CODA_960:
843 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
844 /* fallthrough */
845 case CODA_7541:
846 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
847 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
848 break;
849 }
850
851 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
852 CODA9_FRAME_TILED2LINEAR);
853 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
854 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
855 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
856 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
857 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
858
859 if (dev->devtype->product == CODA_DX6) {
860 /* Configure the coda */
861 coda_write(dev, dev->iram.paddr,
862 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
863 }
864
865 /* Could set rotation here if needed */
866 value = 0;
867 switch (dev->devtype->product) {
868 case CODA_DX6:
869 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
870 << CODADX6_PICWIDTH_OFFSET;
871 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
872 << CODA_PICHEIGHT_OFFSET;
873 break;
874 case CODA_7541:
875 if (dst_fourcc == V4L2_PIX_FMT_H264) {
876 value = (round_up(q_data_src->width, 16) &
877 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
878 value |= (round_up(q_data_src->height, 16) &
879 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
880 break;
881 }
882 /* fallthrough */
883 case CODA_960:
884 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
885 << CODA7_PICWIDTH_OFFSET;
886 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
887 << CODA_PICHEIGHT_OFFSET;
888 }
889 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
890 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
891 ctx->params.framerate = 0;
892 coda_write(dev, ctx->params.framerate,
893 CODA_CMD_ENC_SEQ_SRC_F_RATE);
894
895 ctx->params.codec_mode = ctx->codec->mode;
896 switch (dst_fourcc) {
897 case V4L2_PIX_FMT_MPEG4:
898 if (dev->devtype->product == CODA_960)
899 coda_write(dev, CODA9_STD_MPEG4,
900 CODA_CMD_ENC_SEQ_COD_STD);
901 else
902 coda_write(dev, CODA_STD_MPEG4,
903 CODA_CMD_ENC_SEQ_COD_STD);
904 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
905 break;
906 case V4L2_PIX_FMT_H264:
907 if (dev->devtype->product == CODA_960)
908 coda_write(dev, CODA9_STD_H264,
909 CODA_CMD_ENC_SEQ_COD_STD);
910 else
911 coda_write(dev, CODA_STD_H264,
912 CODA_CMD_ENC_SEQ_COD_STD);
913 if (ctx->params.h264_deblk_enabled) {
914 value = ((ctx->params.h264_deblk_alpha &
915 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
916 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
917 ((ctx->params.h264_deblk_beta &
918 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
919 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
920 } else {
921 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
922 }
923 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
924 break;
925 case V4L2_PIX_FMT_JPEG:
926 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
927 coda_write(dev, ctx->params.jpeg_restart_interval,
928 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
929 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
930 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
931 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
932
933 coda_jpeg_write_tables(ctx);
934 break;
935 default:
936 v4l2_err(v4l2_dev,
937 "dst format (0x%08x) invalid.\n", dst_fourcc);
938 ret = -EINVAL;
939 goto out;
940 }
941
942 /*
943 * slice mode and GOP size registers are used for thumb size/offset
944 * in JPEG mode
945 */
946 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
947 switch (ctx->params.slice_mode) {
948 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
949 value = 0;
950 break;
951 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
952 value = (ctx->params.slice_max_mb &
953 CODA_SLICING_SIZE_MASK)
954 << CODA_SLICING_SIZE_OFFSET;
955 value |= (1 & CODA_SLICING_UNIT_MASK)
956 << CODA_SLICING_UNIT_OFFSET;
957 value |= 1 & CODA_SLICING_MODE_MASK;
958 break;
959 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
960 value = (ctx->params.slice_max_bits &
961 CODA_SLICING_SIZE_MASK)
962 << CODA_SLICING_SIZE_OFFSET;
963 value |= (0 & CODA_SLICING_UNIT_MASK)
964 << CODA_SLICING_UNIT_OFFSET;
965 value |= 1 & CODA_SLICING_MODE_MASK;
966 break;
967 }
968 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
969 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
970 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
971 }
972
973 if (ctx->params.bitrate) {
974 /* Rate control enabled */
975 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
976 << CODA_RATECONTROL_BITRATE_OFFSET;
977 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
978 value |= (ctx->params.vbv_delay &
979 CODA_RATECONTROL_INITIALDELAY_MASK)
980 << CODA_RATECONTROL_INITIALDELAY_OFFSET;
981 if (dev->devtype->product == CODA_960)
982 value |= BIT(31); /* disable autoskip */
983 } else {
984 value = 0;
985 }
986 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
987
988 coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
989 coda_write(dev, ctx->params.intra_refresh,
990 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
991
992 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
993 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
994
995
996 value = 0;
997 if (dev->devtype->product == CODA_960)
998 gamma = CODA9_DEFAULT_GAMMA;
999 else
1000 gamma = CODA_DEFAULT_GAMMA;
1001 if (gamma > 0) {
1002 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1003 CODA_CMD_ENC_SEQ_RC_GAMMA);
1004 }
1005
1006 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1007 coda_write(dev,
1008 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1009 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1010 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1011 }
1012 if (dev->devtype->product == CODA_960) {
1013 if (ctx->params.h264_max_qp)
1014 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1015 if (CODA_DEFAULT_GAMMA > 0)
1016 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1017 } else {
1018 if (CODA_DEFAULT_GAMMA > 0) {
1019 if (dev->devtype->product == CODA_DX6)
1020 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1021 else
1022 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1023 }
1024 if (ctx->params.h264_min_qp)
1025 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1026 if (ctx->params.h264_max_qp)
1027 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1028 }
1029 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1030
1031 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1032
1033 coda_setup_iram(ctx);
1034
1035 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1036 switch (dev->devtype->product) {
1037 case CODA_DX6:
1038 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1039 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1040 break;
1041 case CODA_7541:
1042 coda_write(dev, ctx->iram_info.search_ram_paddr,
1043 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1044 coda_write(dev, ctx->iram_info.search_ram_size,
1045 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1046 break;
1047 case CODA_960:
1048 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1049 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1050 }
1051 }
1052
1053 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1054 if (ret < 0) {
1055 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1056 goto out;
1057 }
1058
1059 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1060 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1061 ret = -EFAULT;
1062 goto out;
1063 }
1064 ctx->initialized = 1;
1065
1066 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1067 if (dev->devtype->product == CODA_960)
1068 ctx->num_internal_frames = 4;
1069 else
1070 ctx->num_internal_frames = 2;
1071 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1072 if (ret < 0) {
1073 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1074 goto out;
1075 }
1076 num_fb = 2;
1077 stride = q_data_src->bytesperline;
1078 } else {
1079 ctx->num_internal_frames = 0;
1080 num_fb = 0;
1081 stride = 0;
1082 }
1083 coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1084 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1085
1086 if (dev->devtype->product == CODA_7541) {
1087 coda_write(dev, q_data_src->bytesperline,
1088 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1089 }
1090 if (dev->devtype->product != CODA_DX6) {
1091 coda_write(dev, ctx->iram_info.buf_bit_use,
1092 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1093 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1094 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1095 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1096 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1097 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1098 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1099 coda_write(dev, ctx->iram_info.buf_ovl_use,
1100 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1101 if (dev->devtype->product == CODA_960) {
1102 coda_write(dev, ctx->iram_info.buf_btp_use,
1103 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1104
1105 coda9_set_frame_cache(ctx, q_data_src->fourcc);
1106
1107 /* FIXME */
1108 coda_write(dev, ctx->internal_frames[2].paddr,
1109 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1110 coda_write(dev, ctx->internal_frames[3].paddr,
1111 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1112 }
1113 }
1114
1115 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1116 if (ret < 0) {
1117 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1118 goto out;
1119 }
1120
1121 /* Save stream headers */
1122 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1123 switch (dst_fourcc) {
1124 case V4L2_PIX_FMT_H264:
1125 /*
1126 * Get SPS in the first frame and copy it to an
1127 * intermediate buffer.
1128 */
1129 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1130 &ctx->vpu_header[0][0],
1131 &ctx->vpu_header_size[0]);
1132 if (ret < 0)
1133 goto out;
1134
1135 /*
1136 * Get PPS in the first frame and copy it to an
1137 * intermediate buffer.
1138 */
1139 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1140 &ctx->vpu_header[1][0],
1141 &ctx->vpu_header_size[1]);
1142 if (ret < 0)
1143 goto out;
1144
1145 /*
1146 * Length of H.264 headers is variable and thus it might not be
1147 * aligned for the coda to append the encoded frame. In that is
1148 * the case a filler NAL must be added to header 2.
1149 */
1150 ctx->vpu_header_size[2] = coda_h264_padding(
1151 (ctx->vpu_header_size[0] +
1152 ctx->vpu_header_size[1]),
1153 ctx->vpu_header[2]);
1154 break;
1155 case V4L2_PIX_FMT_MPEG4:
1156 /*
1157 * Get VOS in the first frame and copy it to an
1158 * intermediate buffer
1159 */
1160 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1161 &ctx->vpu_header[0][0],
1162 &ctx->vpu_header_size[0]);
1163 if (ret < 0)
1164 goto out;
1165
1166 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1167 &ctx->vpu_header[1][0],
1168 &ctx->vpu_header_size[1]);
1169 if (ret < 0)
1170 goto out;
1171
1172 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1173 &ctx->vpu_header[2][0],
1174 &ctx->vpu_header_size[2]);
1175 if (ret < 0)
1176 goto out;
1177 break;
1178 default:
1179 /* No more formats need to save headers at the moment */
1180 break;
1181 }
1182
1183 out:
1184 mutex_unlock(&dev->coda_mutex);
1185 return ret;
1186 }
1187
1188 static int coda_prepare_encode(struct coda_ctx *ctx)
1189 {
1190 struct coda_q_data *q_data_src, *q_data_dst;
1191 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1192 struct coda_dev *dev = ctx->dev;
1193 int force_ipicture;
1194 int quant_param = 0;
1195 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1196 u32 rot_mode = 0;
1197 u32 dst_fourcc;
1198 u32 reg;
1199
1200 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1201 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1202 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1203 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1204 dst_fourcc = q_data_dst->fourcc;
1205
1206 src_buf->sequence = ctx->osequence;
1207 dst_buf->sequence = ctx->osequence;
1208 ctx->osequence++;
1209
1210 /*
1211 * Workaround coda firmware BUG that only marks the first
1212 * frame as IDR. This is a problem for some decoders that can't
1213 * recover when a frame is lost.
1214 */
1215 if (src_buf->sequence % ctx->params.gop_size) {
1216 src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1217 src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1218 } else {
1219 src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1220 src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1221 }
1222
1223 if (dev->devtype->product == CODA_960)
1224 coda_set_gdi_regs(ctx);
1225
1226 /*
1227 * Copy headers at the beginning of the first frame for H.264 only.
1228 * In MPEG4 they are already copied by the coda.
1229 */
1230 if (src_buf->sequence == 0) {
1231 pic_stream_buffer_addr =
1232 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
1233 ctx->vpu_header_size[0] +
1234 ctx->vpu_header_size[1] +
1235 ctx->vpu_header_size[2];
1236 pic_stream_buffer_size = q_data_dst->sizeimage -
1237 ctx->vpu_header_size[0] -
1238 ctx->vpu_header_size[1] -
1239 ctx->vpu_header_size[2];
1240 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
1241 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1242 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1243 + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
1244 ctx->vpu_header_size[1]);
1245 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1246 + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
1247 &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
1248 } else {
1249 pic_stream_buffer_addr =
1250 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1251 pic_stream_buffer_size = q_data_dst->sizeimage;
1252 }
1253
1254 if (src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
1255 force_ipicture = 1;
1256 switch (dst_fourcc) {
1257 case V4L2_PIX_FMT_H264:
1258 quant_param = ctx->params.h264_intra_qp;
1259 break;
1260 case V4L2_PIX_FMT_MPEG4:
1261 quant_param = ctx->params.mpeg4_intra_qp;
1262 break;
1263 case V4L2_PIX_FMT_JPEG:
1264 quant_param = 30;
1265 break;
1266 default:
1267 v4l2_warn(&ctx->dev->v4l2_dev,
1268 "cannot set intra qp, fmt not supported\n");
1269 break;
1270 }
1271 } else {
1272 force_ipicture = 0;
1273 switch (dst_fourcc) {
1274 case V4L2_PIX_FMT_H264:
1275 quant_param = ctx->params.h264_inter_qp;
1276 break;
1277 case V4L2_PIX_FMT_MPEG4:
1278 quant_param = ctx->params.mpeg4_inter_qp;
1279 break;
1280 default:
1281 v4l2_warn(&ctx->dev->v4l2_dev,
1282 "cannot set inter qp, fmt not supported\n");
1283 break;
1284 }
1285 }
1286
1287 /* submit */
1288 if (ctx->params.rot_mode)
1289 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1290 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1291 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1292
1293 if (dev->devtype->product == CODA_960) {
1294 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1295 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1296 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1297
1298 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1299 } else {
1300 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1301 }
1302 coda_write_base(ctx, q_data_src, src_buf, reg);
1303
1304 coda_write(dev, force_ipicture << 1 & 0x2,
1305 CODA_CMD_ENC_PIC_OPTION);
1306
1307 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1308 coda_write(dev, pic_stream_buffer_size / 1024,
1309 CODA_CMD_ENC_PIC_BB_SIZE);
1310
1311 if (!ctx->streamon_out) {
1312 /* After streamoff on the output side, set stream end flag */
1313 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1314 coda_write(dev, ctx->bit_stream_param,
1315 CODA_REG_BIT_BIT_STREAM_PARAM);
1316 }
1317
1318 if (dev->devtype->product != CODA_DX6)
1319 coda_write(dev, ctx->iram_info.axi_sram_use,
1320 CODA7_REG_BIT_AXI_SRAM_USE);
1321
1322 trace_coda_enc_pic_run(ctx, src_buf);
1323
1324 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1325
1326 return 0;
1327 }
1328
1329 static void coda_finish_encode(struct coda_ctx *ctx)
1330 {
1331 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1332 struct coda_dev *dev = ctx->dev;
1333 u32 wr_ptr, start_ptr;
1334
1335 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1336 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1337
1338 trace_coda_enc_pic_done(ctx, dst_buf);
1339
1340 /* Get results from the coda */
1341 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1342 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1343
1344 /* Calculate bytesused field */
1345 if (dst_buf->sequence == 0) {
1346 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
1347 ctx->vpu_header_size[0] +
1348 ctx->vpu_header_size[1] +
1349 ctx->vpu_header_size[2]);
1350 } else {
1351 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
1352 }
1353
1354 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1355 wr_ptr - start_ptr);
1356
1357 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1358 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1359
1360 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1361 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1362 dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1363 } else {
1364 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1365 dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1366 }
1367
1368 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1369 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1370 dst_buf->flags |=
1371 src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1372 dst_buf->timecode = src_buf->timecode;
1373
1374 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1375
1376 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1377 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1378
1379 ctx->gopcounter--;
1380 if (ctx->gopcounter < 0)
1381 ctx->gopcounter = ctx->params.gop_size - 1;
1382
1383 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1384 "job finished: encoding frame (%d) (%s)\n",
1385 dst_buf->sequence,
1386 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
1387 "KEYFRAME" : "PFRAME");
1388 }
1389
1390 static void coda_seq_end_work(struct work_struct *work)
1391 {
1392 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1393 struct coda_dev *dev = ctx->dev;
1394
1395 mutex_lock(&ctx->buffer_mutex);
1396 mutex_lock(&dev->coda_mutex);
1397
1398 if (ctx->initialized == 0)
1399 goto out;
1400
1401 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1402 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1403 __func__);
1404 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1405 v4l2_err(&dev->v4l2_dev,
1406 "CODA_COMMAND_SEQ_END failed\n");
1407 }
1408
1409 /*
1410 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1411 * from the output stream after the h.264 decoder has run. Resetting the
1412 * hardware after the decoder has finished seems to help.
1413 */
1414 if (dev->devtype->product == CODA_960)
1415 coda_hw_reset(ctx);
1416
1417 kfifo_init(&ctx->bitstream_fifo,
1418 ctx->bitstream.vaddr, ctx->bitstream.size);
1419
1420 coda_free_framebuffers(ctx);
1421
1422 ctx->initialized = 0;
1423
1424 out:
1425 mutex_unlock(&dev->coda_mutex);
1426 mutex_unlock(&ctx->buffer_mutex);
1427 }
1428
1429 static void coda_bit_release(struct coda_ctx *ctx)
1430 {
1431 mutex_lock(&ctx->buffer_mutex);
1432 coda_free_framebuffers(ctx);
1433 coda_free_context_buffers(ctx);
1434 coda_free_bitstream_buffer(ctx);
1435 mutex_unlock(&ctx->buffer_mutex);
1436 }
1437
1438 const struct coda_context_ops coda_bit_encode_ops = {
1439 .queue_init = coda_encoder_queue_init,
1440 .reqbufs = coda_encoder_reqbufs,
1441 .start_streaming = coda_start_encoding,
1442 .prepare_run = coda_prepare_encode,
1443 .finish_run = coda_finish_encode,
1444 .seq_end_work = coda_seq_end_work,
1445 .release = coda_bit_release,
1446 };
1447
1448 /*
1449 * Decoder context operations
1450 */
1451
1452 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1453 struct coda_q_data *q_data)
1454 {
1455 if (ctx->bitstream.vaddr)
1456 return 0;
1457
1458 ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1459 ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
1460 ctx->bitstream.size,
1461 &ctx->bitstream.paddr, GFP_KERNEL);
1462 if (!ctx->bitstream.vaddr) {
1463 v4l2_err(&ctx->dev->v4l2_dev,
1464 "failed to allocate bitstream ringbuffer");
1465 return -ENOMEM;
1466 }
1467 kfifo_init(&ctx->bitstream_fifo,
1468 ctx->bitstream.vaddr, ctx->bitstream.size);
1469
1470 return 0;
1471 }
1472
1473 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1474 {
1475 if (ctx->bitstream.vaddr == NULL)
1476 return;
1477
1478 dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1479 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1480 ctx->bitstream.vaddr = NULL;
1481 kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1482 }
1483
1484 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1485 struct v4l2_requestbuffers *rb)
1486 {
1487 struct coda_q_data *q_data_src;
1488 int ret;
1489
1490 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1491 return 0;
1492
1493 if (rb->count) {
1494 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1495 ret = coda_alloc_context_buffers(ctx, q_data_src);
1496 if (ret < 0)
1497 return ret;
1498 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1499 if (ret < 0) {
1500 coda_free_context_buffers(ctx);
1501 return ret;
1502 }
1503 } else {
1504 coda_free_bitstream_buffer(ctx);
1505 coda_free_context_buffers(ctx);
1506 }
1507
1508 return 0;
1509 }
1510
1511 static int __coda_start_decoding(struct coda_ctx *ctx)
1512 {
1513 struct coda_q_data *q_data_src, *q_data_dst;
1514 u32 bitstream_buf, bitstream_size;
1515 struct coda_dev *dev = ctx->dev;
1516 int width, height;
1517 u32 src_fourcc, dst_fourcc;
1518 u32 val;
1519 int ret;
1520
1521 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1522 "Video Data Order Adapter: %s\n",
1523 ctx->use_vdoa ? "Enabled" : "Disabled");
1524
1525 /* Start decoding */
1526 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1527 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1528 bitstream_buf = ctx->bitstream.paddr;
1529 bitstream_size = ctx->bitstream.size;
1530 src_fourcc = q_data_src->fourcc;
1531 dst_fourcc = q_data_dst->fourcc;
1532
1533 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1534
1535 /* Update coda bitstream read and write pointers from kfifo */
1536 coda_kfifo_sync_to_device_full(ctx);
1537
1538 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1539 CODA9_FRAME_TILED2LINEAR);
1540 if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
1541 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1542 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1543 ctx->frame_mem_ctrl |= (0x3 << 9) |
1544 ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
1545 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1546
1547 ctx->display_idx = -1;
1548 ctx->frm_dis_flg = 0;
1549 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1550
1551 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1552 CODA_REG_BIT_BIT_STREAM_PARAM);
1553
1554 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1555 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1556 val = 0;
1557 if ((dev->devtype->product == CODA_7541) ||
1558 (dev->devtype->product == CODA_960))
1559 val |= CODA_REORDER_ENABLE;
1560 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1561 val |= CODA_NO_INT_ENABLE;
1562 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1563
1564 ctx->params.codec_mode = ctx->codec->mode;
1565 if (dev->devtype->product == CODA_960 &&
1566 src_fourcc == V4L2_PIX_FMT_MPEG4)
1567 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1568 else
1569 ctx->params.codec_mode_aux = 0;
1570 if (src_fourcc == V4L2_PIX_FMT_H264) {
1571 if (dev->devtype->product == CODA_7541) {
1572 coda_write(dev, ctx->psbuf.paddr,
1573 CODA_CMD_DEC_SEQ_PS_BB_START);
1574 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1575 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1576 }
1577 if (dev->devtype->product == CODA_960) {
1578 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1579 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1580 }
1581 }
1582 if (dev->devtype->product != CODA_960)
1583 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1584
1585 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1586 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1587 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1588 return -ETIMEDOUT;
1589 }
1590 ctx->initialized = 1;
1591
1592 /* Update kfifo out pointer from coda bitstream read pointer */
1593 coda_kfifo_sync_from_device(ctx);
1594
1595 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1596
1597 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1598 v4l2_err(&dev->v4l2_dev,
1599 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1600 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1601 return -EAGAIN;
1602 }
1603
1604 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1605 if (dev->devtype->product == CODA_DX6) {
1606 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1607 height = val & CODADX6_PICHEIGHT_MASK;
1608 } else {
1609 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1610 height = val & CODA7_PICHEIGHT_MASK;
1611 }
1612
1613 if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1614 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1615 width, height, q_data_dst->bytesperline,
1616 q_data_dst->height);
1617 return -EINVAL;
1618 }
1619
1620 width = round_up(width, 16);
1621 height = round_up(height, 16);
1622
1623 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1624 __func__, ctx->idx, width, height);
1625
1626 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1627 /*
1628 * If the VDOA is used, the decoder needs one additional frame,
1629 * because the frames are freed when the next frame is decoded.
1630 * Otherwise there are visible errors in the decoded frames (green
1631 * regions in displayed frames) and a broken order of frames (earlier
1632 * frames are sporadically displayed after later frames).
1633 */
1634 if (ctx->use_vdoa)
1635 ctx->num_internal_frames += 1;
1636 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1637 v4l2_err(&dev->v4l2_dev,
1638 "not enough framebuffers to decode (%d < %d)\n",
1639 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1640 return -EINVAL;
1641 }
1642
1643 if (src_fourcc == V4L2_PIX_FMT_H264) {
1644 u32 left_right;
1645 u32 top_bottom;
1646
1647 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1648 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1649
1650 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1651 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1652 q_data_dst->rect.width = width - q_data_dst->rect.left -
1653 (left_right & 0x3ff);
1654 q_data_dst->rect.height = height - q_data_dst->rect.top -
1655 (top_bottom & 0x3ff);
1656 }
1657
1658 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1659 if (ret < 0) {
1660 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1661 return ret;
1662 }
1663
1664 /* Tell the decoder how many frame buffers we allocated. */
1665 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1666 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1667
1668 if (dev->devtype->product != CODA_DX6) {
1669 /* Set secondary AXI IRAM */
1670 coda_setup_iram(ctx);
1671
1672 coda_write(dev, ctx->iram_info.buf_bit_use,
1673 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1674 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1675 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1676 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1677 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1678 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1679 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1680 coda_write(dev, ctx->iram_info.buf_ovl_use,
1681 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1682 if (dev->devtype->product == CODA_960) {
1683 coda_write(dev, ctx->iram_info.buf_btp_use,
1684 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1685
1686 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1687 coda9_set_frame_cache(ctx, dst_fourcc);
1688 }
1689 }
1690
1691 if (src_fourcc == V4L2_PIX_FMT_H264) {
1692 coda_write(dev, ctx->slicebuf.paddr,
1693 CODA_CMD_SET_FRAME_SLICE_BB_START);
1694 coda_write(dev, ctx->slicebuf.size / 1024,
1695 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1696 }
1697
1698 if (dev->devtype->product == CODA_7541) {
1699 int max_mb_x = 1920 / 16;
1700 int max_mb_y = 1088 / 16;
1701 int max_mb_num = max_mb_x * max_mb_y;
1702
1703 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1704 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1705 } else if (dev->devtype->product == CODA_960) {
1706 int max_mb_x = 1920 / 16;
1707 int max_mb_y = 1088 / 16;
1708 int max_mb_num = max_mb_x * max_mb_y;
1709
1710 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1711 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1712 }
1713
1714 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1715 v4l2_err(&ctx->dev->v4l2_dev,
1716 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1717 return -ETIMEDOUT;
1718 }
1719
1720 return 0;
1721 }
1722
1723 static int coda_start_decoding(struct coda_ctx *ctx)
1724 {
1725 struct coda_dev *dev = ctx->dev;
1726 int ret;
1727
1728 mutex_lock(&dev->coda_mutex);
1729 ret = __coda_start_decoding(ctx);
1730 mutex_unlock(&dev->coda_mutex);
1731
1732 return ret;
1733 }
1734
1735 static int coda_prepare_decode(struct coda_ctx *ctx)
1736 {
1737 struct vb2_v4l2_buffer *dst_buf;
1738 struct coda_dev *dev = ctx->dev;
1739 struct coda_q_data *q_data_dst;
1740 struct coda_buffer_meta *meta;
1741 unsigned long flags;
1742 u32 rot_mode = 0;
1743 u32 reg_addr, reg_stride;
1744
1745 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1746 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1747
1748 /* Try to copy source buffer contents into the bitstream ringbuffer */
1749 mutex_lock(&ctx->bitstream_mutex);
1750 coda_fill_bitstream(ctx, true);
1751 mutex_unlock(&ctx->bitstream_mutex);
1752
1753 if (coda_get_bitstream_payload(ctx) < 512 &&
1754 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1755 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1756 "bitstream payload: %d, skipping\n",
1757 coda_get_bitstream_payload(ctx));
1758 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1759 return -EAGAIN;
1760 }
1761
1762 /* Run coda_start_decoding (again) if not yet initialized */
1763 if (!ctx->initialized) {
1764 int ret = __coda_start_decoding(ctx);
1765
1766 if (ret < 0) {
1767 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1768 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1769 return -EAGAIN;
1770 } else {
1771 ctx->initialized = 1;
1772 }
1773 }
1774
1775 if (dev->devtype->product == CODA_960)
1776 coda_set_gdi_regs(ctx);
1777
1778 if (ctx->use_vdoa &&
1779 ctx->display_idx >= 0 &&
1780 ctx->display_idx < ctx->num_internal_frames) {
1781 vdoa_device_run(ctx->vdoa,
1782 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
1783 ctx->internal_frames[ctx->display_idx].paddr);
1784 } else {
1785 if (dev->devtype->product == CODA_960) {
1786 /*
1787 * The CODA960 seems to have an internal list of
1788 * buffers with 64 entries that includes the
1789 * registered frame buffers as well as the rotator
1790 * buffer output.
1791 *
1792 * ROT_INDEX needs to be < 0x40, but >
1793 * ctx->num_internal_frames.
1794 */
1795 coda_write(dev,
1796 CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
1797 CODA9_CMD_DEC_PIC_ROT_INDEX);
1798
1799 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1800 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1801 } else {
1802 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1803 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1804 }
1805 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1806 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1807
1808 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1809 }
1810
1811 coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
1812
1813 switch (dev->devtype->product) {
1814 case CODA_DX6:
1815 /* TBD */
1816 case CODA_7541:
1817 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1818 break;
1819 case CODA_960:
1820 /* 'hardcode to use interrupt disable mode'? */
1821 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1822 break;
1823 }
1824
1825 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1826
1827 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1828 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1829
1830 if (dev->devtype->product != CODA_DX6)
1831 coda_write(dev, ctx->iram_info.axi_sram_use,
1832 CODA7_REG_BIT_AXI_SRAM_USE);
1833
1834 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1835 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1836 struct coda_buffer_meta, list);
1837
1838 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1839
1840 /* If this is the last buffer in the bitstream, add padding */
1841 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1842 ctx->bitstream_fifo.kfifo.mask)) {
1843 static unsigned char buf[512];
1844 unsigned int pad;
1845
1846 /* Pad to multiple of 256 and then add 256 more */
1847 pad = ((0 - meta->end) & 0xff) + 256;
1848
1849 memset(buf, 0xff, sizeof(buf));
1850
1851 kfifo_in(&ctx->bitstream_fifo, buf, pad);
1852 }
1853 }
1854 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1855
1856 coda_kfifo_sync_to_device_full(ctx);
1857
1858 /* Clear decode success flag */
1859 coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
1860
1861 trace_coda_dec_pic_run(ctx, meta);
1862
1863 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1864
1865 return 0;
1866 }
1867
1868 static void coda_finish_decode(struct coda_ctx *ctx)
1869 {
1870 struct coda_dev *dev = ctx->dev;
1871 struct coda_q_data *q_data_src;
1872 struct coda_q_data *q_data_dst;
1873 struct vb2_v4l2_buffer *dst_buf;
1874 struct coda_buffer_meta *meta;
1875 unsigned long payload;
1876 unsigned long flags;
1877 int width, height;
1878 int decoded_idx;
1879 int display_idx;
1880 u32 src_fourcc;
1881 int success;
1882 u32 err_mb;
1883 int err_vdoa = 0;
1884 u32 val;
1885
1886 /* Update kfifo out pointer from coda bitstream read pointer */
1887 coda_kfifo_sync_from_device(ctx);
1888
1889 /*
1890 * in stream-end mode, the read pointer can overshoot the write pointer
1891 * by up to 512 bytes
1892 */
1893 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1894 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
1895 kfifo_init(&ctx->bitstream_fifo,
1896 ctx->bitstream.vaddr, ctx->bitstream.size);
1897 }
1898
1899 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1900 src_fourcc = q_data_src->fourcc;
1901
1902 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1903 if (val != 1)
1904 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1905
1906 success = val & 0x1;
1907 if (!success)
1908 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1909
1910 if (src_fourcc == V4L2_PIX_FMT_H264) {
1911 if (val & (1 << 3))
1912 v4l2_err(&dev->v4l2_dev,
1913 "insufficient PS buffer space (%d bytes)\n",
1914 ctx->psbuf.size);
1915 if (val & (1 << 2))
1916 v4l2_err(&dev->v4l2_dev,
1917 "insufficient slice buffer space (%d bytes)\n",
1918 ctx->slicebuf.size);
1919 }
1920
1921 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1922 width = (val >> 16) & 0xffff;
1923 height = val & 0xffff;
1924
1925 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1926
1927 /* frame crop information */
1928 if (src_fourcc == V4L2_PIX_FMT_H264) {
1929 u32 left_right;
1930 u32 top_bottom;
1931
1932 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1933 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1934
1935 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1936 /* Keep current crop information */
1937 } else {
1938 struct v4l2_rect *rect = &q_data_dst->rect;
1939
1940 rect->left = left_right >> 16 & 0xffff;
1941 rect->top = top_bottom >> 16 & 0xffff;
1942 rect->width = width - rect->left -
1943 (left_right & 0xffff);
1944 rect->height = height - rect->top -
1945 (top_bottom & 0xffff);
1946 }
1947 } else {
1948 /* no cropping */
1949 }
1950
1951 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1952 if (err_mb > 0)
1953 v4l2_err(&dev->v4l2_dev,
1954 "errors in %d macroblocks\n", err_mb);
1955
1956 if (dev->devtype->product == CODA_7541) {
1957 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1958 if (val == 0) {
1959 /* not enough bitstream data */
1960 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1961 "prescan failed: %d\n", val);
1962 ctx->hold = true;
1963 return;
1964 }
1965 }
1966
1967 /* Wait until the VDOA finished writing the previous display frame */
1968 if (ctx->use_vdoa &&
1969 ctx->display_idx >= 0 &&
1970 ctx->display_idx < ctx->num_internal_frames) {
1971 err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
1972 }
1973
1974 ctx->frm_dis_flg = coda_read(dev,
1975 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1976
1977 /* The previous display frame was copied out and can be overwritten */
1978 if (ctx->display_idx >= 0 &&
1979 ctx->display_idx < ctx->num_internal_frames) {
1980 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1981 coda_write(dev, ctx->frm_dis_flg,
1982 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1983 }
1984
1985 /*
1986 * The index of the last decoded frame, not necessarily in
1987 * display order, and the index of the next display frame.
1988 * The latter could have been decoded in a previous run.
1989 */
1990 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1991 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1992
1993 if (decoded_idx == -1) {
1994 /* no frame was decoded, but we might have a display frame */
1995 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1996 ctx->sequence_offset++;
1997 else if (ctx->display_idx < 0)
1998 ctx->hold = true;
1999 } else if (decoded_idx == -2) {
2000 /* no frame was decoded, we still return remaining buffers */
2001 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
2002 v4l2_err(&dev->v4l2_dev,
2003 "decoded frame index out of range: %d\n", decoded_idx);
2004 } else {
2005 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
2006 val -= ctx->sequence_offset;
2007 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
2008 if (!list_empty(&ctx->buffer_meta_list)) {
2009 meta = list_first_entry(&ctx->buffer_meta_list,
2010 struct coda_buffer_meta, list);
2011 list_del(&meta->list);
2012 ctx->num_metas--;
2013 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2014 /*
2015 * Clamp counters to 16 bits for comparison, as the HW
2016 * counter rolls over at this point for h.264. This
2017 * may be different for other formats, but using 16 bits
2018 * should be enough to detect most errors and saves us
2019 * from doing different things based on the format.
2020 */
2021 if ((val & 0xffff) != (meta->sequence & 0xffff)) {
2022 v4l2_err(&dev->v4l2_dev,
2023 "sequence number mismatch (%d(%d) != %d)\n",
2024 val, ctx->sequence_offset,
2025 meta->sequence);
2026 }
2027 ctx->frame_metas[decoded_idx] = *meta;
2028 kfree(meta);
2029 } else {
2030 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2031 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
2032 memset(&ctx->frame_metas[decoded_idx], 0,
2033 sizeof(struct coda_buffer_meta));
2034 ctx->frame_metas[decoded_idx].sequence = val;
2035 ctx->sequence_offset++;
2036 }
2037
2038 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2039
2040 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2041 if (val == 0)
2042 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2043 else if (val == 1)
2044 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2045 else
2046 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2047
2048 ctx->frame_errors[decoded_idx] = err_mb;
2049 }
2050
2051 if (display_idx == -1) {
2052 /*
2053 * no more frames to be decoded, but there could still
2054 * be rotator output to dequeue
2055 */
2056 ctx->hold = true;
2057 } else if (display_idx == -3) {
2058 /* possibly prescan failure */
2059 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2060 v4l2_err(&dev->v4l2_dev,
2061 "presentation frame index out of range: %d\n",
2062 display_idx);
2063 }
2064
2065 /* If a frame was copied out, return it */
2066 if (ctx->display_idx >= 0 &&
2067 ctx->display_idx < ctx->num_internal_frames) {
2068 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2069 dst_buf->sequence = ctx->osequence++;
2070
2071 dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2072 V4L2_BUF_FLAG_PFRAME |
2073 V4L2_BUF_FLAG_BFRAME);
2074 dst_buf->flags |= ctx->frame_types[ctx->display_idx];
2075 meta = &ctx->frame_metas[ctx->display_idx];
2076 dst_buf->timecode = meta->timecode;
2077 dst_buf->vb2_buf.timestamp = meta->timestamp;
2078
2079 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2080
2081 switch (q_data_dst->fourcc) {
2082 case V4L2_PIX_FMT_YUYV:
2083 payload = width * height * 2;
2084 break;
2085 case V4L2_PIX_FMT_YUV420:
2086 case V4L2_PIX_FMT_YVU420:
2087 case V4L2_PIX_FMT_NV12:
2088 default:
2089 payload = width * height * 3 / 2;
2090 break;
2091 case V4L2_PIX_FMT_YUV422P:
2092 payload = width * height * 2;
2093 break;
2094 }
2095 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
2096
2097 if (ctx->frame_errors[ctx->display_idx] || err_vdoa)
2098 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2099 else
2100 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
2101
2102 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2103 "job finished: decoding frame (%d) (%s)\n",
2104 dst_buf->sequence,
2105 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
2106 "KEYFRAME" : "PFRAME");
2107 } else {
2108 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2109 "job finished: no frame decoded\n");
2110 }
2111
2112 /* The rotator will copy the current display frame next time */
2113 ctx->display_idx = display_idx;
2114 }
2115
2116 const struct coda_context_ops coda_bit_decode_ops = {
2117 .queue_init = coda_decoder_queue_init,
2118 .reqbufs = coda_decoder_reqbufs,
2119 .start_streaming = coda_start_decoding,
2120 .prepare_run = coda_prepare_decode,
2121 .finish_run = coda_finish_decode,
2122 .seq_end_work = coda_seq_end_work,
2123 .release = coda_bit_release,
2124 };
2125
2126 irqreturn_t coda_irq_handler(int irq, void *data)
2127 {
2128 struct coda_dev *dev = data;
2129 struct coda_ctx *ctx;
2130
2131 /* read status register to attend the IRQ */
2132 coda_read(dev, CODA_REG_BIT_INT_STATUS);
2133 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2134 CODA_REG_BIT_INT_CLEAR);
2135
2136 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2137 if (ctx == NULL) {
2138 v4l2_err(&dev->v4l2_dev,
2139 "Instance released before the end of transaction\n");
2140 mutex_unlock(&dev->coda_mutex);
2141 return IRQ_HANDLED;
2142 }
2143
2144 trace_coda_bit_done(ctx);
2145
2146 if (ctx->aborting) {
2147 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2148 "task has been aborted\n");
2149 }
2150
2151 if (coda_isbusy(ctx->dev)) {
2152 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2153 "coda is still busy!!!!\n");
2154 return IRQ_NONE;
2155 }
2156
2157 complete(&ctx->completion);
2158
2159 return IRQ_HANDLED;
2160 }
Linux with added FPC-III support