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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / media / platform / pxa_camera.c
blob929006f65cc794918c7b303813d6d3ff900c5529
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/time.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/dma/pxa-dma.h>
36
37 #include <media/v4l2-async.h>
38 #include <media/v4l2-clk.h>
39 #include <media/v4l2-common.h>
40 #include <media/v4l2-device.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-of.h>
43
44 #include <media/videobuf2-dma-sg.h>
45
46 #include <linux/videodev2.h>
47
48 #include <linux/platform_data/media/camera-pxa.h>
49
50 #define PXA_CAM_VERSION "0.0.6"
51 #define PXA_CAM_DRV_NAME "pxa27x-camera"
52
53 #define DEFAULT_WIDTH 640
54 #define DEFAULT_HEIGHT 480
55
56 /* Camera Interface */
57 #define CICR0 0x0000
58 #define CICR1 0x0004
59 #define CICR2 0x0008
60 #define CICR3 0x000C
61 #define CICR4 0x0010
62 #define CISR 0x0014
63 #define CIFR 0x0018
64 #define CITOR 0x001C
65 #define CIBR0 0x0028
66 #define CIBR1 0x0030
67 #define CIBR2 0x0038
68
69 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
70 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
71 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
72 #define CICR0_ENB (1 << 28) /* Camera interface enable */
73 #define CICR0_DIS (1 << 27) /* Camera interface disable */
74 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
75 #define CICR0_TOM (1 << 9) /* Time-out mask */
76 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
77 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
78 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
79 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
80 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
81 #define CICR0_CDM (1 << 3) /* Disable-done mask */
82 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
83 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
84 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
85
86 #define CICR1_TBIT (1 << 31) /* Transparency bit */
87 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
88 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
89 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
90 #define CICR1_RGB_F (1 << 11) /* RGB format */
91 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
92 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
93 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
94 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
95 #define CICR1_DW (0x7 << 0) /* Data width mask */
96
97 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
98 wait count mask */
99 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
100 wait count mask */
101 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
102 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
103 wait count mask */
104 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
105 wait count mask */
106
107 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
108 wait count mask */
109 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
110 wait count mask */
111 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
112 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
113 wait count mask */
114 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
115
116 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
117 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
118 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
119 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
120 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
121 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
122 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
123 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
124
125 #define CISR_FTO (1 << 15) /* FIFO time-out */
126 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
127 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
128 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
129 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
130 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
131 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
132 #define CISR_EOL (1 << 8) /* End of line */
133 #define CISR_PAR_ERR (1 << 7) /* Parity error */
134 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
135 #define CISR_CDD (1 << 5) /* Camera interface disable done */
136 #define CISR_SOF (1 << 4) /* Start of frame */
137 #define CISR_EOF (1 << 3) /* End of frame */
138 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
139 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
140 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
141
142 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
143 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
144 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
145 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
146 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
147 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
148 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
149 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
150
151 #define CICR0_SIM_MP (0 << 24)
152 #define CICR0_SIM_SP (1 << 24)
153 #define CICR0_SIM_MS (2 << 24)
154 #define CICR0_SIM_EP (3 << 24)
155 #define CICR0_SIM_ES (4 << 24)
156
157 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
158 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
159 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
160 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
161 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
162
163 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
164 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
165 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
166 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
167 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
168
169 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
170 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
171 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
172 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
173
174 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
175 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
176 CICR0_EOFM | CICR0_FOM)
177
178 #define sensor_call(cam, o, f, args...) \
179 v4l2_subdev_call(cam->sensor, o, f, ##args)
180
181 /*
182 * Format handling
183 */
184
185 /**
186 * enum pxa_mbus_packing - data packing types on the media-bus
187 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
188 * sample represents one pixel
189 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
190 * possibly incomplete byte high bits are padding
191 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
192 * to 16 bits
193 */
194 enum pxa_mbus_packing {
195 PXA_MBUS_PACKING_NONE,
196 PXA_MBUS_PACKING_2X8_PADHI,
197 PXA_MBUS_PACKING_EXTEND16,
198 };
199
200 /**
201 * enum pxa_mbus_order - sample order on the media bus
202 * @PXA_MBUS_ORDER_LE: least significant sample first
203 * @PXA_MBUS_ORDER_BE: most significant sample first
204 */
205 enum pxa_mbus_order {
206 PXA_MBUS_ORDER_LE,
207 PXA_MBUS_ORDER_BE,
208 };
209
210 /**
211 * enum pxa_mbus_layout - planes layout in memory
212 * @PXA_MBUS_LAYOUT_PACKED: color components packed
213 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
214 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
215 * chroma plane (C plane is half the size
216 * of Y plane)
217 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
218 * chroma plane (C plane is the same size
219 * as Y plane)
220 */
221 enum pxa_mbus_layout {
222 PXA_MBUS_LAYOUT_PACKED = 0,
223 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
224 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
225 PXA_MBUS_LAYOUT_PLANAR_Y_C,
226 };
227
228 /**
229 * struct pxa_mbus_pixelfmt - Data format on the media bus
230 * @name: Name of the format
231 * @fourcc: Fourcc code, that will be obtained if the data is
232 * stored in memory in the following way:
233 * @packing: Type of sample-packing, that has to be used
234 * @order: Sample order when storing in memory
235 * @bits_per_sample: How many bits the bridge has to sample
236 */
237 struct pxa_mbus_pixelfmt {
238 const char *name;
239 u32 fourcc;
240 enum pxa_mbus_packing packing;
241 enum pxa_mbus_order order;
242 enum pxa_mbus_layout layout;
243 u8 bits_per_sample;
244 };
245
246 /**
247 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
248 * @code: mediabus pixel-code
249 * @fmt: pixel format description
250 */
251 struct pxa_mbus_lookup {
252 u32 code;
253 struct pxa_mbus_pixelfmt fmt;
254 };
255
256 static const struct pxa_mbus_lookup mbus_fmt[] = {
257 {
258 .code = MEDIA_BUS_FMT_YUYV8_2X8,
259 .fmt = {
260 .fourcc = V4L2_PIX_FMT_YUYV,
261 .name = "YUYV",
262 .bits_per_sample = 8,
263 .packing = PXA_MBUS_PACKING_2X8_PADHI,
264 .order = PXA_MBUS_ORDER_LE,
265 .layout = PXA_MBUS_LAYOUT_PACKED,
266 },
267 }, {
268 .code = MEDIA_BUS_FMT_YVYU8_2X8,
269 .fmt = {
270 .fourcc = V4L2_PIX_FMT_YVYU,
271 .name = "YVYU",
272 .bits_per_sample = 8,
273 .packing = PXA_MBUS_PACKING_2X8_PADHI,
274 .order = PXA_MBUS_ORDER_LE,
275 .layout = PXA_MBUS_LAYOUT_PACKED,
276 },
277 }, {
278 .code = MEDIA_BUS_FMT_UYVY8_2X8,
279 .fmt = {
280 .fourcc = V4L2_PIX_FMT_UYVY,
281 .name = "UYVY",
282 .bits_per_sample = 8,
283 .packing = PXA_MBUS_PACKING_2X8_PADHI,
284 .order = PXA_MBUS_ORDER_LE,
285 .layout = PXA_MBUS_LAYOUT_PACKED,
286 },
287 }, {
288 .code = MEDIA_BUS_FMT_VYUY8_2X8,
289 .fmt = {
290 .fourcc = V4L2_PIX_FMT_VYUY,
291 .name = "VYUY",
292 .bits_per_sample = 8,
293 .packing = PXA_MBUS_PACKING_2X8_PADHI,
294 .order = PXA_MBUS_ORDER_LE,
295 .layout = PXA_MBUS_LAYOUT_PACKED,
296 },
297 }, {
298 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
299 .fmt = {
300 .fourcc = V4L2_PIX_FMT_RGB555,
301 .name = "RGB555",
302 .bits_per_sample = 8,
303 .packing = PXA_MBUS_PACKING_2X8_PADHI,
304 .order = PXA_MBUS_ORDER_LE,
305 .layout = PXA_MBUS_LAYOUT_PACKED,
306 },
307 }, {
308 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
309 .fmt = {
310 .fourcc = V4L2_PIX_FMT_RGB555X,
311 .name = "RGB555X",
312 .bits_per_sample = 8,
313 .packing = PXA_MBUS_PACKING_2X8_PADHI,
314 .order = PXA_MBUS_ORDER_BE,
315 .layout = PXA_MBUS_LAYOUT_PACKED,
316 },
317 }, {
318 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
319 .fmt = {
320 .fourcc = V4L2_PIX_FMT_RGB565,
321 .name = "RGB565",
322 .bits_per_sample = 8,
323 .packing = PXA_MBUS_PACKING_2X8_PADHI,
324 .order = PXA_MBUS_ORDER_LE,
325 .layout = PXA_MBUS_LAYOUT_PACKED,
326 },
327 }, {
328 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
329 .fmt = {
330 .fourcc = V4L2_PIX_FMT_RGB565X,
331 .name = "RGB565X",
332 .bits_per_sample = 8,
333 .packing = PXA_MBUS_PACKING_2X8_PADHI,
334 .order = PXA_MBUS_ORDER_BE,
335 .layout = PXA_MBUS_LAYOUT_PACKED,
336 },
337 }, {
338 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
339 .fmt = {
340 .fourcc = V4L2_PIX_FMT_SBGGR8,
341 .name = "Bayer 8 BGGR",
342 .bits_per_sample = 8,
343 .packing = PXA_MBUS_PACKING_NONE,
344 .order = PXA_MBUS_ORDER_LE,
345 .layout = PXA_MBUS_LAYOUT_PACKED,
346 },
347 }, {
348 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
349 .fmt = {
350 .fourcc = V4L2_PIX_FMT_SBGGR10,
351 .name = "Bayer 10 BGGR",
352 .bits_per_sample = 10,
353 .packing = PXA_MBUS_PACKING_EXTEND16,
354 .order = PXA_MBUS_ORDER_LE,
355 .layout = PXA_MBUS_LAYOUT_PACKED,
356 },
357 }, {
358 .code = MEDIA_BUS_FMT_Y8_1X8,
359 .fmt = {
360 .fourcc = V4L2_PIX_FMT_GREY,
361 .name = "Grey",
362 .bits_per_sample = 8,
363 .packing = PXA_MBUS_PACKING_NONE,
364 .order = PXA_MBUS_ORDER_LE,
365 .layout = PXA_MBUS_LAYOUT_PACKED,
366 },
367 }, {
368 .code = MEDIA_BUS_FMT_Y10_1X10,
369 .fmt = {
370 .fourcc = V4L2_PIX_FMT_Y10,
371 .name = "Grey 10bit",
372 .bits_per_sample = 10,
373 .packing = PXA_MBUS_PACKING_EXTEND16,
374 .order = PXA_MBUS_ORDER_LE,
375 .layout = PXA_MBUS_LAYOUT_PACKED,
376 },
377 }, {
378 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
379 .fmt = {
380 .fourcc = V4L2_PIX_FMT_SBGGR10,
381 .name = "Bayer 10 BGGR",
382 .bits_per_sample = 8,
383 .packing = PXA_MBUS_PACKING_2X8_PADHI,
384 .order = PXA_MBUS_ORDER_LE,
385 .layout = PXA_MBUS_LAYOUT_PACKED,
386 },
387 }, {
388 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
389 .fmt = {
390 .fourcc = V4L2_PIX_FMT_SBGGR10,
391 .name = "Bayer 10 BGGR",
392 .bits_per_sample = 8,
393 .packing = PXA_MBUS_PACKING_2X8_PADHI,
394 .order = PXA_MBUS_ORDER_BE,
395 .layout = PXA_MBUS_LAYOUT_PACKED,
396 },
397 }, {
398 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
399 .fmt = {
400 .fourcc = V4L2_PIX_FMT_RGB444,
401 .name = "RGB444",
402 .bits_per_sample = 8,
403 .packing = PXA_MBUS_PACKING_2X8_PADHI,
404 .order = PXA_MBUS_ORDER_BE,
405 .layout = PXA_MBUS_LAYOUT_PACKED,
406 },
407 }, {
408 .code = MEDIA_BUS_FMT_UYVY8_1X16,
409 .fmt = {
410 .fourcc = V4L2_PIX_FMT_UYVY,
411 .name = "UYVY 16bit",
412 .bits_per_sample = 16,
413 .packing = PXA_MBUS_PACKING_EXTEND16,
414 .order = PXA_MBUS_ORDER_LE,
415 .layout = PXA_MBUS_LAYOUT_PACKED,
416 },
417 }, {
418 .code = MEDIA_BUS_FMT_VYUY8_1X16,
419 .fmt = {
420 .fourcc = V4L2_PIX_FMT_VYUY,
421 .name = "VYUY 16bit",
422 .bits_per_sample = 16,
423 .packing = PXA_MBUS_PACKING_EXTEND16,
424 .order = PXA_MBUS_ORDER_LE,
425 .layout = PXA_MBUS_LAYOUT_PACKED,
426 },
427 }, {
428 .code = MEDIA_BUS_FMT_YUYV8_1X16,
429 .fmt = {
430 .fourcc = V4L2_PIX_FMT_YUYV,
431 .name = "YUYV 16bit",
432 .bits_per_sample = 16,
433 .packing = PXA_MBUS_PACKING_EXTEND16,
434 .order = PXA_MBUS_ORDER_LE,
435 .layout = PXA_MBUS_LAYOUT_PACKED,
436 },
437 }, {
438 .code = MEDIA_BUS_FMT_YVYU8_1X16,
439 .fmt = {
440 .fourcc = V4L2_PIX_FMT_YVYU,
441 .name = "YVYU 16bit",
442 .bits_per_sample = 16,
443 .packing = PXA_MBUS_PACKING_EXTEND16,
444 .order = PXA_MBUS_ORDER_LE,
445 .layout = PXA_MBUS_LAYOUT_PACKED,
446 },
447 }, {
448 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
449 .fmt = {
450 .fourcc = V4L2_PIX_FMT_SGRBG8,
451 .name = "Bayer 8 GRBG",
452 .bits_per_sample = 8,
453 .packing = PXA_MBUS_PACKING_NONE,
454 .order = PXA_MBUS_ORDER_LE,
455 .layout = PXA_MBUS_LAYOUT_PACKED,
456 },
457 }, {
458 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
459 .fmt = {
460 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
461 .name = "Bayer 10 BGGR DPCM 8",
462 .bits_per_sample = 8,
463 .packing = PXA_MBUS_PACKING_NONE,
464 .order = PXA_MBUS_ORDER_LE,
465 .layout = PXA_MBUS_LAYOUT_PACKED,
466 },
467 }, {
468 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
469 .fmt = {
470 .fourcc = V4L2_PIX_FMT_SGBRG10,
471 .name = "Bayer 10 GBRG",
472 .bits_per_sample = 10,
473 .packing = PXA_MBUS_PACKING_EXTEND16,
474 .order = PXA_MBUS_ORDER_LE,
475 .layout = PXA_MBUS_LAYOUT_PACKED,
476 },
477 }, {
478 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
479 .fmt = {
480 .fourcc = V4L2_PIX_FMT_SGRBG10,
481 .name = "Bayer 10 GRBG",
482 .bits_per_sample = 10,
483 .packing = PXA_MBUS_PACKING_EXTEND16,
484 .order = PXA_MBUS_ORDER_LE,
485 .layout = PXA_MBUS_LAYOUT_PACKED,
486 },
487 }, {
488 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
489 .fmt = {
490 .fourcc = V4L2_PIX_FMT_SRGGB10,
491 .name = "Bayer 10 RGGB",
492 .bits_per_sample = 10,
493 .packing = PXA_MBUS_PACKING_EXTEND16,
494 .order = PXA_MBUS_ORDER_LE,
495 .layout = PXA_MBUS_LAYOUT_PACKED,
496 },
497 }, {
498 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
499 .fmt = {
500 .fourcc = V4L2_PIX_FMT_SBGGR12,
501 .name = "Bayer 12 BGGR",
502 .bits_per_sample = 12,
503 .packing = PXA_MBUS_PACKING_EXTEND16,
504 .order = PXA_MBUS_ORDER_LE,
505 .layout = PXA_MBUS_LAYOUT_PACKED,
506 },
507 }, {
508 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
509 .fmt = {
510 .fourcc = V4L2_PIX_FMT_SGBRG12,
511 .name = "Bayer 12 GBRG",
512 .bits_per_sample = 12,
513 .packing = PXA_MBUS_PACKING_EXTEND16,
514 .order = PXA_MBUS_ORDER_LE,
515 .layout = PXA_MBUS_LAYOUT_PACKED,
516 },
517 }, {
518 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
519 .fmt = {
520 .fourcc = V4L2_PIX_FMT_SGRBG12,
521 .name = "Bayer 12 GRBG",
522 .bits_per_sample = 12,
523 .packing = PXA_MBUS_PACKING_EXTEND16,
524 .order = PXA_MBUS_ORDER_LE,
525 .layout = PXA_MBUS_LAYOUT_PACKED,
526 },
527 }, {
528 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
529 .fmt = {
530 .fourcc = V4L2_PIX_FMT_SRGGB12,
531 .name = "Bayer 12 RGGB",
532 .bits_per_sample = 12,
533 .packing = PXA_MBUS_PACKING_EXTEND16,
534 .order = PXA_MBUS_ORDER_LE,
535 .layout = PXA_MBUS_LAYOUT_PACKED,
536 },
537 },
538 };
539
540 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
541 {
542 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
543 return width * mf->bits_per_sample / 8;
544
545 switch (mf->packing) {
546 case PXA_MBUS_PACKING_NONE:
547 return width * mf->bits_per_sample / 8;
548 case PXA_MBUS_PACKING_2X8_PADHI:
549 case PXA_MBUS_PACKING_EXTEND16:
550 return width * 2;
551 }
552 return -EINVAL;
553 }
554
555 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
556 u32 bytes_per_line, u32 height)
557 {
558 switch (mf->packing) {
559 case PXA_MBUS_PACKING_2X8_PADHI:
560 return bytes_per_line * height * 2;
561 default:
562 return -EINVAL;
563 }
564 }
565
566 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
567 u32 code,
568 const struct pxa_mbus_lookup *lookup,
569 int n)
570 {
571 int i;
572
573 for (i = 0; i < n; i++)
574 if (lookup[i].code == code)
575 return &lookup[i].fmt;
576
577 return NULL;
578 }
579
580 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
581 u32 code)
582 {
583 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
584 }
585
586 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
587 unsigned int flags)
588 {
589 unsigned long common_flags;
590 bool hsync = true, vsync = true, pclk, data, mode;
591 bool mipi_lanes, mipi_clock;
592
593 common_flags = cfg->flags & flags;
594
595 switch (cfg->type) {
596 case V4L2_MBUS_PARALLEL:
597 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
598 V4L2_MBUS_HSYNC_ACTIVE_LOW);
599 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
600 V4L2_MBUS_VSYNC_ACTIVE_LOW);
601 /* fall through */
602 case V4L2_MBUS_BT656:
603 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
604 V4L2_MBUS_PCLK_SAMPLE_FALLING);
605 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
606 V4L2_MBUS_DATA_ACTIVE_LOW);
607 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
608 return (!hsync || !vsync || !pclk || !data || !mode) ?
609 0 : common_flags;
610 case V4L2_MBUS_CSI2:
611 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
612 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
613 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
614 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
615 }
616 return 0;
617 }
618
619 /**
620 * struct soc_camera_format_xlate - match between host and sensor formats
621 * @code: code of a sensor provided format
622 * @host_fmt: host format after host translation from code
623 *
624 * Host and sensor translation structure. Used in table of host and sensor
625 * formats matchings in soc_camera_device. A host can override the generic list
626 * generation by implementing get_formats(), and use it for format checks and
627 * format setup.
628 */
629 struct soc_camera_format_xlate {
630 u32 code;
631 const struct pxa_mbus_pixelfmt *host_fmt;
632 };
633
634 /*
635 * Structures
636 */
637 enum pxa_camera_active_dma {
638 DMA_Y = 0x1,
639 DMA_U = 0x2,
640 DMA_V = 0x4,
641 };
642
643 /* buffer for one video frame */
644 struct pxa_buffer {
645 /* common v4l buffer stuff -- must be first */
646 struct vb2_v4l2_buffer vbuf;
647 struct list_head queue;
648 u32 code;
649 int nb_planes;
650 /* our descriptor lists for Y, U and V channels */
651 struct dma_async_tx_descriptor *descs[3];
652 dma_cookie_t cookie[3];
653 struct scatterlist *sg[3];
654 int sg_len[3];
655 size_t plane_sizes[3];
656 int inwork;
657 enum pxa_camera_active_dma active_dma;
658 };
659
660 struct pxa_camera_dev {
661 struct v4l2_device v4l2_dev;
662 struct video_device vdev;
663 struct v4l2_async_notifier notifier;
664 struct vb2_queue vb2_vq;
665 struct v4l2_subdev *sensor;
666 struct soc_camera_format_xlate *user_formats;
667 const struct soc_camera_format_xlate *current_fmt;
668 struct v4l2_pix_format current_pix;
669
670 struct v4l2_async_subdev asd;
671 struct v4l2_async_subdev *asds[1];
672
673 /*
674 * PXA27x is only supposed to handle one camera on its Quick Capture
675 * interface. If anyone ever builds hardware to enable more than
676 * one camera, they will have to modify this driver too
677 */
678 struct clk *clk;
679
680 unsigned int irq;
681 void __iomem *base;
682
683 int channels;
684 struct dma_chan *dma_chans[3];
685
686 struct pxacamera_platform_data *pdata;
687 struct resource *res;
688 unsigned long platform_flags;
689 unsigned long ciclk;
690 unsigned long mclk;
691 u32 mclk_divisor;
692 struct v4l2_clk *mclk_clk;
693 u16 width_flags; /* max 10 bits */
694
695 struct list_head capture;
696
697 spinlock_t lock;
698 struct mutex mlock;
699 unsigned int buf_sequence;
700
701 struct pxa_buffer *active;
702 struct tasklet_struct task_eof;
703
704 u32 save_cicr[5];
705 };
706
707 struct pxa_cam {
708 unsigned long flags;
709 };
710
711 static const char *pxa_cam_driver_description = "PXA_Camera";
712
713 /*
714 * Format translation functions
715 */
716 static const struct soc_camera_format_xlate
717 *pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
718 unsigned int fourcc)
719 {
720 unsigned int i;
721
722 for (i = 0; user_formats[i].code; i++)
723 if (user_formats[i].host_fmt->fourcc == fourcc)
724 return user_formats + i;
725 return NULL;
726 }
727
728 static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
729 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
730 int (*get_formats)(struct v4l2_device *, unsigned int,
731 struct soc_camera_format_xlate *xlate))
732 {
733 unsigned int i, fmts = 0, raw_fmts = 0;
734 int ret;
735 struct v4l2_subdev_mbus_code_enum code = {
736 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
737 };
738 struct soc_camera_format_xlate *user_formats;
739
740 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
741 raw_fmts++;
742 code.index++;
743 }
744
745 /*
746 * First pass - only count formats this host-sensor
747 * configuration can provide
748 */
749 for (i = 0; i < raw_fmts; i++) {
750 ret = get_formats(v4l2_dev, i, NULL);
751 if (ret < 0)
752 return ERR_PTR(ret);
753 fmts += ret;
754 }
755
756 if (!fmts)
757 return ERR_PTR(-ENXIO);
758
759 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
760 if (!user_formats)
761 return ERR_PTR(-ENOMEM);
762
763 /* Second pass - actually fill data formats */
764 fmts = 0;
765 for (i = 0; i < raw_fmts; i++) {
766 ret = get_formats(v4l2_dev, i, user_formats + fmts);
767 if (ret < 0)
768 goto egfmt;
769 fmts += ret;
770 }
771 user_formats[fmts].code = 0;
772
773 return user_formats;
774 egfmt:
775 kfree(user_formats);
776 return ERR_PTR(ret);
777 }
778
779 /*
780 * Videobuf operations
781 */
782 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
783 {
784 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
785
786 return container_of(vbuf, struct pxa_buffer, vbuf);
787 }
788
789 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
790 {
791 return pcdev->v4l2_dev.dev;
792 }
793
794 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
795 {
796 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
797 }
798
799 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
800 enum pxa_camera_active_dma act_dma);
801
802 static void pxa_camera_dma_irq_y(void *data)
803 {
804 struct pxa_camera_dev *pcdev = data;
805
806 pxa_camera_dma_irq(pcdev, DMA_Y);
807 }
808
809 static void pxa_camera_dma_irq_u(void *data)
810 {
811 struct pxa_camera_dev *pcdev = data;
812
813 pxa_camera_dma_irq(pcdev, DMA_U);
814 }
815
816 static void pxa_camera_dma_irq_v(void *data)
817 {
818 struct pxa_camera_dev *pcdev = data;
819
820 pxa_camera_dma_irq(pcdev, DMA_V);
821 }
822
823 /**
824 * pxa_init_dma_channel - init dma descriptors
825 * @pcdev: pxa camera device
826 * @vb: videobuffer2 buffer
827 * @dma: dma video buffer
828 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
829 * @cibr: camera Receive Buffer Register
830 *
831 * Prepares the pxa dma descriptors to transfer one camera channel.
832 *
833 * Returns 0 if success or -ENOMEM if no memory is available
834 */
835 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
836 struct pxa_buffer *buf, int channel,
837 struct scatterlist *sg, int sglen)
838 {
839 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
840 struct dma_async_tx_descriptor *tx;
841
842 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
843 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
844 if (!tx) {
845 dev_err(pcdev_to_dev(pcdev),
846 "dmaengine_prep_slave_sg failed\n");
847 goto fail;
848 }
849
850 tx->callback_param = pcdev;
851 switch (channel) {
852 case 0:
853 tx->callback = pxa_camera_dma_irq_y;
854 break;
855 case 1:
856 tx->callback = pxa_camera_dma_irq_u;
857 break;
858 case 2:
859 tx->callback = pxa_camera_dma_irq_v;
860 break;
861 }
862
863 buf->descs[channel] = tx;
864 return 0;
865 fail:
866 dev_dbg(pcdev_to_dev(pcdev),
867 "%s (vb=%p) dma_tx=%p\n",
868 __func__, buf, tx);
869
870 return -ENOMEM;
871 }
872
873 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
874 struct pxa_buffer *buf)
875 {
876 buf->active_dma = DMA_Y;
877 if (buf->nb_planes == 3)
878 buf->active_dma |= DMA_U | DMA_V;
879 }
880
881 /**
882 * pxa_dma_start_channels - start DMA channel for active buffer
883 * @pcdev: pxa camera device
884 *
885 * Initialize DMA channels to the beginning of the active video buffer, and
886 * start these channels.
887 */
888 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
889 {
890 int i;
891
892 for (i = 0; i < pcdev->channels; i++) {
893 dev_dbg(pcdev_to_dev(pcdev),
894 "%s (channel=%d)\n", __func__, i);
895 dma_async_issue_pending(pcdev->dma_chans[i]);
896 }
897 }
898
899 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
900 {
901 int i;
902
903 for (i = 0; i < pcdev->channels; i++) {
904 dev_dbg(pcdev_to_dev(pcdev),
905 "%s (channel=%d)\n", __func__, i);
906 dmaengine_terminate_all(pcdev->dma_chans[i]);
907 }
908 }
909
910 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
911 struct pxa_buffer *buf)
912 {
913 int i;
914
915 for (i = 0; i < pcdev->channels; i++) {
916 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
917 dev_dbg(pcdev_to_dev(pcdev),
918 "%s (channel=%d) : submit vb=%p cookie=%d\n",
919 __func__, i, buf, buf->descs[i]->cookie);
920 }
921 }
922
923 /**
924 * pxa_camera_start_capture - start video capturing
925 * @pcdev: camera device
926 *
927 * Launch capturing. DMA channels should not be active yet. They should get
928 * activated at the end of frame interrupt, to capture only whole frames, and
929 * never begin the capture of a partial frame.
930 */
931 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
932 {
933 unsigned long cicr0;
934
935 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
936 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
937 /* Enable End-Of-Frame Interrupt */
938 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
939 cicr0 &= ~CICR0_EOFM;
940 __raw_writel(cicr0, pcdev->base + CICR0);
941 }
942
943 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
944 {
945 unsigned long cicr0;
946
947 pxa_dma_stop_channels(pcdev);
948
949 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
950 __raw_writel(cicr0, pcdev->base + CICR0);
951
952 pcdev->active = NULL;
953 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
954 }
955
956 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
957 struct pxa_buffer *buf,
958 enum vb2_buffer_state state)
959 {
960 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
961 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
962
963 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
964 list_del_init(&buf->queue);
965 vb->timestamp = ktime_get_ns();
966 vbuf->sequence = pcdev->buf_sequence++;
967 vbuf->field = V4L2_FIELD_NONE;
968 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
969 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
970 __func__, buf);
971
972 if (list_empty(&pcdev->capture)) {
973 pxa_camera_stop_capture(pcdev);
974 return;
975 }
976
977 pcdev->active = list_entry(pcdev->capture.next,
978 struct pxa_buffer, queue);
979 }
980
981 /**
982 * pxa_camera_check_link_miss - check missed DMA linking
983 * @pcdev: camera device
984 *
985 * The DMA chaining is done with DMA running. This means a tiny temporal window
986 * remains, where a buffer is queued on the chain, while the chain is already
987 * stopped. This means the tailed buffer would never be transferred by DMA.
988 * This function restarts the capture for this corner case, where :
989 * - DADR() == DADDR_STOP
990 * - a videobuffer is queued on the pcdev->capture list
991 *
992 * Please check the "DMA hot chaining timeslice issue" in
993 * Documentation/video4linux/pxa_camera.txt
994 *
995 * Context: should only be called within the dma irq handler
996 */
997 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
998 dma_cookie_t last_submitted,
999 dma_cookie_t last_issued)
1000 {
1001 bool is_dma_stopped = last_submitted != last_issued;
1002
1003 dev_dbg(pcdev_to_dev(pcdev),
1004 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1005 __func__, pcdev->active, is_dma_stopped);
1006
1007 if (pcdev->active && is_dma_stopped)
1008 pxa_camera_start_capture(pcdev);
1009 }
1010
1011 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1012 enum pxa_camera_active_dma act_dma)
1013 {
1014 struct pxa_buffer *buf, *last_buf;
1015 unsigned long flags;
1016 u32 camera_status, overrun;
1017 int chan;
1018 enum dma_status last_status;
1019 dma_cookie_t last_issued;
1020
1021 spin_lock_irqsave(&pcdev->lock, flags);
1022
1023 camera_status = __raw_readl(pcdev->base + CISR);
1024 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1025 camera_status, act_dma);
1026 overrun = CISR_IFO_0;
1027 if (pcdev->channels == 3)
1028 overrun |= CISR_IFO_1 | CISR_IFO_2;
1029
1030 /*
1031 * pcdev->active should not be NULL in DMA irq handler.
1032 *
1033 * But there is one corner case : if capture was stopped due to an
1034 * overrun of channel 1, and at that same channel 2 was completed.
1035 *
1036 * When handling the overrun in DMA irq for channel 1, we'll stop the
1037 * capture and restart it (and thus set pcdev->active to NULL). But the
1038 * DMA irq handler will already be pending for channel 2. So on entering
1039 * the DMA irq handler for channel 2 there will be no active buffer, yet
1040 * that is normal.
1041 */
1042 if (!pcdev->active)
1043 goto out;
1044
1045 buf = pcdev->active;
1046 WARN_ON(buf->inwork || list_empty(&buf->queue));
1047
1048 /*
1049 * It's normal if the last frame creates an overrun, as there
1050 * are no more DMA descriptors to fetch from QCI fifos
1051 */
1052 switch (act_dma) {
1053 case DMA_U:
1054 chan = 1;
1055 break;
1056 case DMA_V:
1057 chan = 2;
1058 break;
1059 default:
1060 chan = 0;
1061 break;
1062 }
1063 last_buf = list_entry(pcdev->capture.prev,
1064 struct pxa_buffer, queue);
1065 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1066 last_buf->cookie[chan],
1067 NULL, &last_issued);
1068 if (camera_status & overrun &&
1069 last_status != DMA_COMPLETE) {
1070 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1071 camera_status);
1072 pxa_camera_stop_capture(pcdev);
1073 list_for_each_entry(buf, &pcdev->capture, queue)
1074 pxa_dma_add_tail_buf(pcdev, buf);
1075 pxa_camera_start_capture(pcdev);
1076 goto out;
1077 }
1078 buf->active_dma &= ~act_dma;
1079 if (!buf->active_dma) {
1080 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1081 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1082 last_issued);
1083 }
1084
1085 out:
1086 spin_unlock_irqrestore(&pcdev->lock, flags);
1087 }
1088
1089 static u32 mclk_get_divisor(struct platform_device *pdev,
1090 struct pxa_camera_dev *pcdev)
1091 {
1092 unsigned long mclk = pcdev->mclk;
1093 u32 div;
1094 unsigned long lcdclk;
1095
1096 lcdclk = clk_get_rate(pcdev->clk);
1097 pcdev->ciclk = lcdclk;
1098
1099 /* mclk <= ciclk / 4 (27.4.2) */
1100 if (mclk > lcdclk / 4) {
1101 mclk = lcdclk / 4;
1102 dev_warn(pcdev_to_dev(pcdev),
1103 "Limiting master clock to %lu\n", mclk);
1104 }
1105
1106 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1107 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1108
1109 /* If we're not supplying MCLK, leave it at 0 */
1110 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1111 pcdev->mclk = lcdclk / (2 * (div + 1));
1112
1113 dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n",
1114 lcdclk, mclk, div);
1115
1116 return div;
1117 }
1118
1119 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1120 unsigned long pclk)
1121 {
1122 /* We want a timeout > 1 pixel time, not ">=" */
1123 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1124
1125 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1126 }
1127
1128 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1129 {
1130 u32 cicr4 = 0;
1131
1132 /* disable all interrupts */
1133 __raw_writel(0x3ff, pcdev->base + CICR0);
1134
1135 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1136 cicr4 |= CICR4_PCLK_EN;
1137 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1138 cicr4 |= CICR4_MCLK_EN;
1139 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1140 cicr4 |= CICR4_PCP;
1141 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1142 cicr4 |= CICR4_HSP;
1143 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1144 cicr4 |= CICR4_VSP;
1145
1146 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1147
1148 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1149 /* Initialise the timeout under the assumption pclk = mclk */
1150 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1151 else
1152 /* "Safe default" - 13MHz */
1153 recalculate_fifo_timeout(pcdev, 13000000);
1154
1155 clk_prepare_enable(pcdev->clk);
1156 }
1157
1158 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1159 {
1160 clk_disable_unprepare(pcdev->clk);
1161 }
1162
1163 static void pxa_camera_eof(unsigned long arg)
1164 {
1165 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1166 unsigned long cifr;
1167 struct pxa_buffer *buf;
1168
1169 dev_dbg(pcdev_to_dev(pcdev),
1170 "Camera interrupt status 0x%x\n",
1171 __raw_readl(pcdev->base + CISR));
1172
1173 /* Reset the FIFOs */
1174 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1175 __raw_writel(cifr, pcdev->base + CIFR);
1176
1177 pcdev->active = list_first_entry(&pcdev->capture,
1178 struct pxa_buffer, queue);
1179 buf = pcdev->active;
1180 pxa_videobuf_set_actdma(pcdev, buf);
1181
1182 pxa_dma_start_channels(pcdev);
1183 }
1184
1185 static irqreturn_t pxa_camera_irq(int irq, void *data)
1186 {
1187 struct pxa_camera_dev *pcdev = data;
1188 unsigned long status, cicr0;
1189
1190 status = __raw_readl(pcdev->base + CISR);
1191 dev_dbg(pcdev_to_dev(pcdev),
1192 "Camera interrupt status 0x%lx\n", status);
1193
1194 if (!status)
1195 return IRQ_NONE;
1196
1197 __raw_writel(status, pcdev->base + CISR);
1198
1199 if (status & CISR_EOF) {
1200 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1201 __raw_writel(cicr0, pcdev->base + CICR0);
1202 tasklet_schedule(&pcdev->task_eof);
1203 }
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static int test_platform_param(struct pxa_camera_dev *pcdev,
1209 unsigned char buswidth, unsigned long *flags)
1210 {
1211 /*
1212 * Platform specified synchronization and pixel clock polarities are
1213 * only a recommendation and are only used during probing. The PXA270
1214 * quick capture interface supports both.
1215 */
1216 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1217 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1218 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1219 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1220 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1221 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1222 V4L2_MBUS_DATA_ACTIVE_HIGH |
1223 V4L2_MBUS_PCLK_SAMPLE_RISING |
1224 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1225
1226 /* If requested data width is supported by the platform, use it */
1227 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1228 return 0;
1229
1230 return -EINVAL;
1231 }
1232
1233 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1234 unsigned long flags, __u32 pixfmt)
1235 {
1236 unsigned long dw, bpp;
1237 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1238 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1239
1240 if (ret < 0)
1241 y_skip_top = 0;
1242
1243 /*
1244 * Datawidth is now guaranteed to be equal to one of the three values.
1245 * We fix bit-per-pixel equal to data-width...
1246 */
1247 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1248 case 10:
1249 dw = 4;
1250 bpp = 0x40;
1251 break;
1252 case 9:
1253 dw = 3;
1254 bpp = 0x20;
1255 break;
1256 default:
1257 /*
1258 * Actually it can only be 8 now,
1259 * default is just to silence compiler warnings
1260 */
1261 case 8:
1262 dw = 2;
1263 bpp = 0;
1264 }
1265
1266 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1267 cicr4 |= CICR4_PCLK_EN;
1268 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1269 cicr4 |= CICR4_MCLK_EN;
1270 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1271 cicr4 |= CICR4_PCP;
1272 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1273 cicr4 |= CICR4_HSP;
1274 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1275 cicr4 |= CICR4_VSP;
1276
1277 cicr0 = __raw_readl(pcdev->base + CICR0);
1278 if (cicr0 & CICR0_ENB)
1279 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1280
1281 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1282
1283 switch (pixfmt) {
1284 case V4L2_PIX_FMT_YUV422P:
1285 pcdev->channels = 3;
1286 cicr1 |= CICR1_YCBCR_F;
1287 /*
1288 * Normally, pxa bus wants as input UYVY format. We allow all
1289 * reorderings of the YUV422 format, as no processing is done,
1290 * and the YUV stream is just passed through without any
1291 * transformation. Note that UYVY is the only format that
1292 * should be used if pxa framebuffer Overlay2 is used.
1293 */
1294 case V4L2_PIX_FMT_UYVY:
1295 case V4L2_PIX_FMT_VYUY:
1296 case V4L2_PIX_FMT_YUYV:
1297 case V4L2_PIX_FMT_YVYU:
1298 cicr1 |= CICR1_COLOR_SP_VAL(2);
1299 break;
1300 case V4L2_PIX_FMT_RGB555:
1301 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1302 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1303 break;
1304 case V4L2_PIX_FMT_RGB565:
1305 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1306 break;
1307 }
1308
1309 cicr2 = 0;
1310 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1311 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1312 cicr4 |= pcdev->mclk_divisor;
1313
1314 __raw_writel(cicr1, pcdev->base + CICR1);
1315 __raw_writel(cicr2, pcdev->base + CICR2);
1316 __raw_writel(cicr3, pcdev->base + CICR3);
1317 __raw_writel(cicr4, pcdev->base + CICR4);
1318
1319 /* CIF interrupts are not used, only DMA */
1320 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1321 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1322 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1323 __raw_writel(cicr0, pcdev->base + CICR0);
1324 }
1325
1326 /*
1327 * Videobuf2 section
1328 */
1329 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1330 {
1331 int i;
1332
1333 for (i = 0; i < 3 && buf->descs[i]; i++) {
1334 dmaengine_desc_free(buf->descs[i]);
1335 kfree(buf->sg[i]);
1336 buf->descs[i] = NULL;
1337 buf->sg[i] = NULL;
1338 buf->sg_len[i] = 0;
1339 buf->plane_sizes[i] = 0;
1340 }
1341 buf->nb_planes = 0;
1342 }
1343
1344 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1345 struct pxa_buffer *buf)
1346 {
1347 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1348 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1349 int nb_channels = pcdev->channels;
1350 int i, ret = 0;
1351 unsigned long size = vb2_plane_size(vb, 0);
1352
1353 switch (nb_channels) {
1354 case 1:
1355 buf->plane_sizes[0] = size;
1356 break;
1357 case 3:
1358 buf->plane_sizes[0] = size / 2;
1359 buf->plane_sizes[1] = size / 4;
1360 buf->plane_sizes[2] = size / 4;
1361 break;
1362 default:
1363 return -EINVAL;
1364 };
1365 buf->nb_planes = nb_channels;
1366
1367 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1368 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1369 if (ret < 0) {
1370 dev_err(pcdev_to_dev(pcdev),
1371 "sg_split failed: %d\n", ret);
1372 return ret;
1373 }
1374 for (i = 0; i < nb_channels; i++) {
1375 ret = pxa_init_dma_channel(pcdev, buf, i,
1376 buf->sg[i], buf->sg_len[i]);
1377 if (ret) {
1378 pxa_buffer_cleanup(buf);
1379 return ret;
1380 }
1381 }
1382 INIT_LIST_HEAD(&buf->queue);
1383
1384 return ret;
1385 }
1386
1387 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1388 {
1389 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1390 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1391
1392 dev_dbg(pcdev_to_dev(pcdev),
1393 "%s(vb=%p)\n", __func__, vb);
1394 pxa_buffer_cleanup(buf);
1395 }
1396
1397 static void pxac_vb2_queue(struct vb2_buffer *vb)
1398 {
1399 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1400 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1401
1402 dev_dbg(pcdev_to_dev(pcdev),
1403 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1404 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1405 pcdev->active);
1406
1407 list_add_tail(&buf->queue, &pcdev->capture);
1408
1409 pxa_dma_add_tail_buf(pcdev, buf);
1410 }
1411
1412 /*
1413 * Please check the DMA prepared buffer structure in :
1414 * Documentation/video4linux/pxa_camera.txt
1415 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1416 * modification while DMA chain is running will work anyway.
1417 */
1418 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1419 {
1420 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1421 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1422 int ret = 0;
1423
1424 switch (pcdev->channels) {
1425 case 1:
1426 case 3:
1427 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1428 break;
1429 default:
1430 return -EINVAL;
1431 }
1432
1433 dev_dbg(pcdev_to_dev(pcdev),
1434 "%s (vb=%p) nb_channels=%d size=%lu\n",
1435 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1436
1437 WARN_ON(!pcdev->current_fmt);
1438
1439 #ifdef DEBUG
1440 /*
1441 * This can be useful if you want to see if we actually fill
1442 * the buffer with something
1443 */
1444 for (i = 0; i < vb->num_planes; i++)
1445 memset((void *)vb2_plane_vaddr(vb, i),
1446 0xaa, vb2_get_plane_payload(vb, i));
1447 #endif
1448
1449 /*
1450 * I think, in buf_prepare you only have to protect global data,
1451 * the actual buffer is yours
1452 */
1453 buf->inwork = 0;
1454 pxa_videobuf_set_actdma(pcdev, buf);
1455
1456 return ret;
1457 }
1458
1459 static int pxac_vb2_init(struct vb2_buffer *vb)
1460 {
1461 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1462 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1463
1464 dev_dbg(pcdev_to_dev(pcdev),
1465 "%s(nb_channels=%d)\n",
1466 __func__, pcdev->channels);
1467
1468 return pxa_buffer_init(pcdev, buf);
1469 }
1470
1471 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1472 unsigned int *nbufs,
1473 unsigned int *num_planes, unsigned int sizes[],
1474 struct device *alloc_devs[])
1475 {
1476 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1477 int size = pcdev->current_pix.sizeimage;
1478
1479 dev_dbg(pcdev_to_dev(pcdev),
1480 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1481 __func__, vq, *nbufs, *num_planes, size);
1482 /*
1483 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1484 * format, even if there are 3 planes Y, U and V, we reply there is only
1485 * one plane, containing Y, U and V data, one after the other.
1486 */
1487 if (*num_planes)
1488 return sizes[0] < size ? -EINVAL : 0;
1489
1490 *num_planes = 1;
1491 switch (pcdev->channels) {
1492 case 1:
1493 case 3:
1494 sizes[0] = size;
1495 break;
1496 default:
1497 return -EINVAL;
1498 }
1499
1500 if (!*nbufs)
1501 *nbufs = 1;
1502
1503 return 0;
1504 }
1505
1506 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1507 {
1508 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1509
1510 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1511 __func__, count, pcdev->active);
1512
1513 pcdev->buf_sequence = 0;
1514 if (!pcdev->active)
1515 pxa_camera_start_capture(pcdev);
1516
1517 return 0;
1518 }
1519
1520 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1521 {
1522 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1523 struct pxa_buffer *buf, *tmp;
1524
1525 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1526 __func__, pcdev->active);
1527 pxa_camera_stop_capture(pcdev);
1528
1529 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1530 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1531 }
1532
1533 static struct vb2_ops pxac_vb2_ops = {
1534 .queue_setup = pxac_vb2_queue_setup,
1535 .buf_init = pxac_vb2_init,
1536 .buf_prepare = pxac_vb2_prepare,
1537 .buf_queue = pxac_vb2_queue,
1538 .buf_cleanup = pxac_vb2_cleanup,
1539 .start_streaming = pxac_vb2_start_streaming,
1540 .stop_streaming = pxac_vb2_stop_streaming,
1541 .wait_prepare = vb2_ops_wait_prepare,
1542 .wait_finish = vb2_ops_wait_finish,
1543 };
1544
1545 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1546 {
1547 int ret;
1548 struct vb2_queue *vq = &pcdev->vb2_vq;
1549
1550 memset(vq, 0, sizeof(*vq));
1551 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1552 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1553 vq->drv_priv = pcdev;
1554 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1555 vq->buf_struct_size = sizeof(struct pxa_buffer);
1556 vq->dev = pcdev->v4l2_dev.dev;
1557
1558 vq->ops = &pxac_vb2_ops;
1559 vq->mem_ops = &vb2_dma_sg_memops;
1560 vq->lock = &pcdev->mlock;
1561
1562 ret = vb2_queue_init(vq);
1563 dev_dbg(pcdev_to_dev(pcdev),
1564 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1565
1566 return ret;
1567 }
1568
1569 /*
1570 * Video ioctls section
1571 */
1572 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1573 {
1574 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1575 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1576 unsigned long bus_flags, common_flags;
1577 int ret;
1578
1579 ret = test_platform_param(pcdev,
1580 pcdev->current_fmt->host_fmt->bits_per_sample,
1581 &bus_flags);
1582 if (ret < 0)
1583 return ret;
1584
1585 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1586 if (!ret) {
1587 common_flags = pxa_mbus_config_compatible(&cfg,
1588 bus_flags);
1589 if (!common_flags) {
1590 dev_warn(pcdev_to_dev(pcdev),
1591 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1592 cfg.flags, bus_flags);
1593 return -EINVAL;
1594 }
1595 } else if (ret != -ENOIOCTLCMD) {
1596 return ret;
1597 } else {
1598 common_flags = bus_flags;
1599 }
1600
1601 pcdev->channels = 1;
1602
1603 /* Make choises, based on platform preferences */
1604 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1605 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1606 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1607 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1608 else
1609 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1610 }
1611
1612 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1613 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1614 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1615 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1616 else
1617 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1618 }
1619
1620 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1621 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1622 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1623 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1624 else
1625 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1626 }
1627
1628 cfg.flags = common_flags;
1629 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1630 if (ret < 0 && ret != -ENOIOCTLCMD) {
1631 dev_dbg(pcdev_to_dev(pcdev),
1632 "camera s_mbus_config(0x%lx) returned %d\n",
1633 common_flags, ret);
1634 return ret;
1635 }
1636
1637 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1638
1639 return 0;
1640 }
1641
1642 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1643 unsigned char buswidth)
1644 {
1645 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1646 unsigned long bus_flags, common_flags;
1647 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1648
1649 if (ret < 0)
1650 return ret;
1651
1652 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1653 if (!ret) {
1654 common_flags = pxa_mbus_config_compatible(&cfg,
1655 bus_flags);
1656 if (!common_flags) {
1657 dev_warn(pcdev_to_dev(pcdev),
1658 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1659 cfg.flags, bus_flags);
1660 return -EINVAL;
1661 }
1662 } else if (ret == -ENOIOCTLCMD) {
1663 ret = 0;
1664 }
1665
1666 return ret;
1667 }
1668
1669 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1670 {
1671 .fourcc = V4L2_PIX_FMT_YUV422P,
1672 .name = "Planar YUV422 16 bit",
1673 .bits_per_sample = 8,
1674 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1675 .order = PXA_MBUS_ORDER_LE,
1676 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1677 },
1678 };
1679
1680 /* This will be corrected as we get more formats */
1681 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1682 {
1683 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1684 (fmt->bits_per_sample == 8 &&
1685 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1686 (fmt->bits_per_sample > 8 &&
1687 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1688 }
1689
1690 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1691 unsigned int idx,
1692 struct soc_camera_format_xlate *xlate)
1693 {
1694 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1695 int formats = 0, ret;
1696 struct v4l2_subdev_mbus_code_enum code = {
1697 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1698 .index = idx,
1699 };
1700 const struct pxa_mbus_pixelfmt *fmt;
1701
1702 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1703 if (ret < 0)
1704 /* No more formats */
1705 return 0;
1706
1707 fmt = pxa_mbus_get_fmtdesc(code.code);
1708 if (!fmt) {
1709 dev_err(pcdev_to_dev(pcdev),
1710 "Invalid format code #%u: %d\n", idx, code.code);
1711 return 0;
1712 }
1713
1714 /* This also checks support for the requested bits-per-sample */
1715 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1716 if (ret < 0)
1717 return 0;
1718
1719 switch (code.code) {
1720 case MEDIA_BUS_FMT_UYVY8_2X8:
1721 formats++;
1722 if (xlate) {
1723 xlate->host_fmt = &pxa_camera_formats[0];
1724 xlate->code = code.code;
1725 xlate++;
1726 dev_dbg(pcdev_to_dev(pcdev),
1727 "Providing format %s using code %d\n",
1728 pxa_camera_formats[0].name, code.code);
1729 }
1730 /* fall through */
1731 case MEDIA_BUS_FMT_VYUY8_2X8:
1732 case MEDIA_BUS_FMT_YUYV8_2X8:
1733 case MEDIA_BUS_FMT_YVYU8_2X8:
1734 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1735 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1736 if (xlate)
1737 dev_dbg(pcdev_to_dev(pcdev),
1738 "Providing format %s packed\n",
1739 fmt->name);
1740 break;
1741 default:
1742 if (!pxa_camera_packing_supported(fmt))
1743 return 0;
1744 if (xlate)
1745 dev_dbg(pcdev_to_dev(pcdev),
1746 "Providing format %s in pass-through mode\n",
1747 fmt->name);
1748 break;
1749 }
1750
1751 /* Generic pass-through */
1752 formats++;
1753 if (xlate) {
1754 xlate->host_fmt = fmt;
1755 xlate->code = code.code;
1756 xlate++;
1757 }
1758
1759 return formats;
1760 }
1761
1762 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1763 {
1764 struct soc_camera_format_xlate *xlate;
1765
1766 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1767 pxa_camera_get_formats);
1768 if (IS_ERR(xlate))
1769 return PTR_ERR(xlate);
1770
1771 pcdev->user_formats = xlate;
1772 return 0;
1773 }
1774
1775 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1776 {
1777 kfree(pcdev->user_formats);
1778 }
1779
1780 static int pxa_camera_check_frame(u32 width, u32 height)
1781 {
1782 /* limit to pxa hardware capabilities */
1783 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1784 (width & 0x01);
1785 }
1786
1787 #ifdef CONFIG_VIDEO_ADV_DEBUG
1788 static int pxac_vidioc_g_register(struct file *file, void *priv,
1789 struct v4l2_dbg_register *reg)
1790 {
1791 struct pxa_camera_dev *pcdev = video_drvdata(file);
1792
1793 if (reg->reg > CIBR2)
1794 return -ERANGE;
1795
1796 reg->val = __raw_readl(pcdev->base + reg->reg);
1797 reg->size = sizeof(__u32);
1798 return 0;
1799 }
1800
1801 static int pxac_vidioc_s_register(struct file *file, void *priv,
1802 const struct v4l2_dbg_register *reg)
1803 {
1804 struct pxa_camera_dev *pcdev = video_drvdata(file);
1805
1806 if (reg->reg > CIBR2)
1807 return -ERANGE;
1808 if (reg->size != sizeof(__u32))
1809 return -EINVAL;
1810 __raw_writel(reg->val, pcdev->base + reg->reg);
1811 return 0;
1812 }
1813 #endif
1814
1815 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1816 struct v4l2_fmtdesc *f)
1817 {
1818 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1819 const struct pxa_mbus_pixelfmt *format;
1820 unsigned int idx;
1821
1822 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1823 if (f->index >= idx)
1824 return -EINVAL;
1825
1826 format = pcdev->user_formats[f->index].host_fmt;
1827 f->pixelformat = format->fourcc;
1828 return 0;
1829 }
1830
1831 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1832 struct v4l2_format *f)
1833 {
1834 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1835 struct v4l2_pix_format *pix = &f->fmt.pix;
1836
1837 pix->width = pcdev->current_pix.width;
1838 pix->height = pcdev->current_pix.height;
1839 pix->bytesperline = pcdev->current_pix.bytesperline;
1840 pix->sizeimage = pcdev->current_pix.sizeimage;
1841 pix->field = pcdev->current_pix.field;
1842 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1843 pix->colorspace = pcdev->current_pix.colorspace;
1844 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1845 pcdev->current_fmt->host_fmt->fourcc);
1846 return 0;
1847 }
1848
1849 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1850 struct v4l2_format *f)
1851 {
1852 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1853 const struct soc_camera_format_xlate *xlate;
1854 struct v4l2_pix_format *pix = &f->fmt.pix;
1855 struct v4l2_subdev_pad_config pad_cfg;
1856 struct v4l2_subdev_format format = {
1857 .which = V4L2_SUBDEV_FORMAT_TRY,
1858 };
1859 struct v4l2_mbus_framefmt *mf = &format.format;
1860 __u32 pixfmt = pix->pixelformat;
1861 int ret;
1862
1863 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1864 if (!xlate) {
1865 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1866 return -EINVAL;
1867 }
1868
1869 /*
1870 * Limit to pxa hardware capabilities. YUV422P planar format requires
1871 * images size to be a multiple of 16 bytes. If not, zeros will be
1872 * inserted between Y and U planes, and U and V planes, which violates
1873 * the YUV422P standard.
1874 */
1875 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1876 &pix->height, 32, 2048, 0,
1877 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1878
1879 v4l2_fill_mbus_format(mf, pix, xlate->code);
1880 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1881 if (ret < 0)
1882 return ret;
1883
1884 v4l2_fill_pix_format(pix, mf);
1885
1886 /* Only progressive video supported so far */
1887 switch (mf->field) {
1888 case V4L2_FIELD_ANY:
1889 case V4L2_FIELD_NONE:
1890 pix->field = V4L2_FIELD_NONE;
1891 break;
1892 default:
1893 /* TODO: support interlaced at least in pass-through mode */
1894 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1895 mf->field);
1896 return -EINVAL;
1897 }
1898
1899 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1900 if (ret < 0)
1901 return ret;
1902
1903 pix->bytesperline = ret;
1904 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1905 pix->height);
1906 if (ret < 0)
1907 return ret;
1908
1909 pix->sizeimage = ret;
1910 return 0;
1911 }
1912
1913 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1914 struct v4l2_format *f)
1915 {
1916 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1917 const struct soc_camera_format_xlate *xlate;
1918 struct v4l2_pix_format *pix = &f->fmt.pix;
1919 struct v4l2_subdev_format format = {
1920 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1921 };
1922 unsigned long flags;
1923 int ret, is_busy;
1924
1925 dev_dbg(pcdev_to_dev(pcdev),
1926 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1927 pix->width, pix->height, pix->pixelformat);
1928
1929 spin_lock_irqsave(&pcdev->lock, flags);
1930 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1931 spin_unlock_irqrestore(&pcdev->lock, flags);
1932
1933 if (is_busy)
1934 return -EBUSY;
1935
1936 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1937 if (ret)
1938 return ret;
1939
1940 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1941 pix->pixelformat);
1942 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1943 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1944 if (ret < 0) {
1945 dev_warn(pcdev_to_dev(pcdev),
1946 "Failed to configure for format %x\n",
1947 pix->pixelformat);
1948 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1949 dev_warn(pcdev_to_dev(pcdev),
1950 "Camera driver produced an unsupported frame %dx%d\n",
1951 pix->width, pix->height);
1952 return -EINVAL;
1953 }
1954
1955 pcdev->current_fmt = xlate;
1956 pcdev->current_pix = *pix;
1957
1958 ret = pxa_camera_set_bus_param(pcdev);
1959 return ret;
1960 }
1961
1962 static int pxac_vidioc_querycap(struct file *file, void *priv,
1963 struct v4l2_capability *cap)
1964 {
1965 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1966 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1967 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1968 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1969 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1970
1971 return 0;
1972 }
1973
1974 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1975 struct v4l2_input *i)
1976 {
1977 if (i->index > 0)
1978 return -EINVAL;
1979
1980 i->type = V4L2_INPUT_TYPE_CAMERA;
1981 strlcpy(i->name, "Camera", sizeof(i->name));
1982
1983 return 0;
1984 }
1985
1986 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1987 {
1988 *i = 0;
1989
1990 return 0;
1991 }
1992
1993 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1994 {
1995 if (i > 0)
1996 return -EINVAL;
1997
1998 return 0;
1999 }
2000
2001 static int pxac_fops_camera_open(struct file *filp)
2002 {
2003 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2004 int ret;
2005
2006 mutex_lock(&pcdev->mlock);
2007 ret = v4l2_fh_open(filp);
2008 if (ret < 0)
2009 goto out;
2010
2011 ret = sensor_call(pcdev, core, s_power, 1);
2012 if (ret)
2013 v4l2_fh_release(filp);
2014 out:
2015 mutex_unlock(&pcdev->mlock);
2016 return ret;
2017 }
2018
2019 static int pxac_fops_camera_release(struct file *filp)
2020 {
2021 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2022 int ret;
2023
2024 ret = vb2_fop_release(filp);
2025 if (ret < 0)
2026 return ret;
2027
2028 mutex_lock(&pcdev->mlock);
2029 ret = sensor_call(pcdev, core, s_power, 0);
2030 mutex_unlock(&pcdev->mlock);
2031
2032 return ret;
2033 }
2034
2035 static const struct v4l2_file_operations pxa_camera_fops = {
2036 .owner = THIS_MODULE,
2037 .open = pxac_fops_camera_open,
2038 .release = pxac_fops_camera_release,
2039 .read = vb2_fop_read,
2040 .poll = vb2_fop_poll,
2041 .mmap = vb2_fop_mmap,
2042 .unlocked_ioctl = video_ioctl2,
2043 };
2044
2045 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2046 .vidioc_querycap = pxac_vidioc_querycap,
2047
2048 .vidioc_enum_input = pxac_vidioc_enum_input,
2049 .vidioc_g_input = pxac_vidioc_g_input,
2050 .vidioc_s_input = pxac_vidioc_s_input,
2051
2052 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2053 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2054 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2055 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2056
2057 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2058 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2059 .vidioc_querybuf = vb2_ioctl_querybuf,
2060 .vidioc_qbuf = vb2_ioctl_qbuf,
2061 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2062 .vidioc_expbuf = vb2_ioctl_expbuf,
2063 .vidioc_streamon = vb2_ioctl_streamon,
2064 .vidioc_streamoff = vb2_ioctl_streamoff,
2065 #ifdef CONFIG_VIDEO_ADV_DEBUG
2066 .vidioc_g_register = pxac_vidioc_g_register,
2067 .vidioc_s_register = pxac_vidioc_s_register,
2068 #endif
2069 };
2070
2071 static struct v4l2_clk_ops pxa_camera_mclk_ops = {
2072 };
2073
2074 static const struct video_device pxa_camera_videodev_template = {
2075 .name = "pxa-camera",
2076 .minor = -1,
2077 .fops = &pxa_camera_fops,
2078 .ioctl_ops = &pxa_camera_ioctl_ops,
2079 .release = video_device_release_empty,
2080 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2081 };
2082
2083 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2084 struct v4l2_subdev *subdev,
2085 struct v4l2_async_subdev *asd)
2086 {
2087 int err;
2088 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2089 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2090 struct video_device *vdev = &pcdev->vdev;
2091 struct v4l2_pix_format *pix = &pcdev->current_pix;
2092 struct v4l2_subdev_format format = {
2093 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2094 };
2095 struct v4l2_mbus_framefmt *mf = &format.format;
2096
2097 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2098 __func__);
2099 mutex_lock(&pcdev->mlock);
2100 *vdev = pxa_camera_videodev_template;
2101 vdev->v4l2_dev = v4l2_dev;
2102 vdev->lock = &pcdev->mlock;
2103 pcdev->sensor = subdev;
2104 pcdev->vdev.queue = &pcdev->vb2_vq;
2105 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2106 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2107 video_set_drvdata(&pcdev->vdev, pcdev);
2108
2109 err = pxa_camera_build_formats(pcdev);
2110 if (err) {
2111 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2112 err);
2113 goto out;
2114 }
2115
2116 pcdev->current_fmt = pcdev->user_formats;
2117 pix->field = V4L2_FIELD_NONE;
2118 pix->width = DEFAULT_WIDTH;
2119 pix->height = DEFAULT_HEIGHT;
2120 pix->bytesperline =
2121 pxa_mbus_bytes_per_line(pix->width,
2122 pcdev->current_fmt->host_fmt);
2123 pix->sizeimage =
2124 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2125 pix->bytesperline, pix->height);
2126 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2127 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2128
2129 err = sensor_call(pcdev, core, s_power, 1);
2130 if (err)
2131 goto out;
2132
2133 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2134 if (err)
2135 goto out_sensor_poweroff;
2136
2137 v4l2_fill_pix_format(pix, mf);
2138 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2139 __func__, pix->colorspace, pix->pixelformat);
2140
2141 err = pxa_camera_init_videobuf2(pcdev);
2142 if (err)
2143 goto out_sensor_poweroff;
2144
2145 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2146 if (err) {
2147 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2148 pcdev->sensor = NULL;
2149 } else {
2150 dev_info(pcdev_to_dev(pcdev),
2151 "PXA Camera driver attached to camera %s\n",
2152 subdev->name);
2153 }
2154
2155 out_sensor_poweroff:
2156 err = sensor_call(pcdev, core, s_power, 0);
2157 out:
2158 mutex_unlock(&pcdev->mlock);
2159 return err;
2160 }
2161
2162 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2163 struct v4l2_subdev *subdev,
2164 struct v4l2_async_subdev *asd)
2165 {
2166 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2167
2168 mutex_lock(&pcdev->mlock);
2169 dev_info(pcdev_to_dev(pcdev),
2170 "PXA Camera driver detached from camera %s\n",
2171 subdev->name);
2172
2173 /* disable capture, disable interrupts */
2174 __raw_writel(0x3ff, pcdev->base + CICR0);
2175
2176 /* Stop DMA engine */
2177 pxa_dma_stop_channels(pcdev);
2178
2179 pxa_camera_destroy_formats(pcdev);
2180 video_unregister_device(&pcdev->vdev);
2181 pcdev->sensor = NULL;
2182
2183 mutex_unlock(&pcdev->mlock);
2184 }
2185
2186 /*
2187 * Driver probe, remove, suspend and resume operations
2188 */
2189 static int pxa_camera_suspend(struct device *dev)
2190 {
2191 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2192 int i = 0, ret = 0;
2193
2194 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2195 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2196 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2197 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2198 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2199
2200 if (pcdev->sensor) {
2201 ret = sensor_call(pcdev, core, s_power, 0);
2202 if (ret == -ENOIOCTLCMD)
2203 ret = 0;
2204 }
2205
2206 return ret;
2207 }
2208
2209 static int pxa_camera_resume(struct device *dev)
2210 {
2211 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2212 int i = 0, ret = 0;
2213
2214 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2215 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2216 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2217 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2218 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2219
2220 if (pcdev->sensor) {
2221 ret = sensor_call(pcdev, core, s_power, 1);
2222 if (ret == -ENOIOCTLCMD)
2223 ret = 0;
2224 }
2225
2226 /* Restart frame capture if active buffer exists */
2227 if (!ret && pcdev->active)
2228 pxa_camera_start_capture(pcdev);
2229
2230 return ret;
2231 }
2232
2233 static int pxa_camera_pdata_from_dt(struct device *dev,
2234 struct pxa_camera_dev *pcdev,
2235 struct v4l2_async_subdev *asd)
2236 {
2237 u32 mclk_rate;
2238 struct device_node *remote, *np = dev->of_node;
2239 struct v4l2_of_endpoint ep;
2240 int err = of_property_read_u32(np, "clock-frequency",
2241 &mclk_rate);
2242 if (!err) {
2243 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2244 pcdev->mclk = mclk_rate;
2245 }
2246
2247 np = of_graph_get_next_endpoint(np, NULL);
2248 if (!np) {
2249 dev_err(dev, "could not find endpoint\n");
2250 return -EINVAL;
2251 }
2252
2253 err = v4l2_of_parse_endpoint(np, &ep);
2254 if (err) {
2255 dev_err(dev, "could not parse endpoint\n");
2256 goto out;
2257 }
2258
2259 switch (ep.bus.parallel.bus_width) {
2260 case 4:
2261 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2262 break;
2263 case 5:
2264 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2265 break;
2266 case 8:
2267 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2268 break;
2269 case 9:
2270 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2271 break;
2272 case 10:
2273 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2274 break;
2275 default:
2276 break;
2277 }
2278
2279 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2280 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2281 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2282 pcdev->platform_flags |= PXA_CAMERA_HSP;
2283 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2284 pcdev->platform_flags |= PXA_CAMERA_VSP;
2285 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2286 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2287 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2288 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2289
2290 asd->match_type = V4L2_ASYNC_MATCH_OF;
2291 remote = of_graph_get_remote_port(np);
2292 if (remote) {
2293 asd->match.of.node = remote;
2294 of_node_put(remote);
2295 } else {
2296 dev_notice(dev, "no remote for %s\n", of_node_full_name(np));
2297 }
2298
2299 out:
2300 of_node_put(np);
2301
2302 return err;
2303 }
2304
2305 static int pxa_camera_probe(struct platform_device *pdev)
2306 {
2307 struct pxa_camera_dev *pcdev;
2308 struct resource *res;
2309 void __iomem *base;
2310 struct dma_slave_config config = {
2311 .src_addr_width = 0,
2312 .src_maxburst = 8,
2313 .direction = DMA_DEV_TO_MEM,
2314 };
2315 dma_cap_mask_t mask;
2316 struct pxad_param params;
2317 char clk_name[V4L2_CLK_NAME_SIZE];
2318 int irq;
2319 int err = 0, i;
2320
2321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2322 irq = platform_get_irq(pdev, 0);
2323 if (!res || irq < 0)
2324 return -ENODEV;
2325
2326 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2327 if (!pcdev) {
2328 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2329 return -ENOMEM;
2330 }
2331
2332 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2333 if (IS_ERR(pcdev->clk))
2334 return PTR_ERR(pcdev->clk);
2335
2336 pcdev->res = res;
2337
2338 pcdev->pdata = pdev->dev.platform_data;
2339 if (&pdev->dev.of_node && !pcdev->pdata) {
2340 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2341 } else {
2342 pcdev->platform_flags = pcdev->pdata->flags;
2343 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2344 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2345 pcdev->asd.match.i2c.adapter_id =
2346 pcdev->pdata->sensor_i2c_adapter_id;
2347 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2348 }
2349 if (err < 0)
2350 return err;
2351
2352 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2353 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2354 /*
2355 * Platform hasn't set available data widths. This is bad.
2356 * Warn and use a default.
2357 */
2358 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2359 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2360 }
2361 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2362 pcdev->width_flags = 1 << 7;
2363 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2364 pcdev->width_flags |= 1 << 8;
2365 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2366 pcdev->width_flags |= 1 << 9;
2367 if (!pcdev->mclk) {
2368 dev_warn(&pdev->dev,
2369 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2370 pcdev->mclk = 20000000;
2371 }
2372
2373 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2374
2375 INIT_LIST_HEAD(&pcdev->capture);
2376 spin_lock_init(&pcdev->lock);
2377 mutex_init(&pcdev->mlock);
2378
2379 /*
2380 * Request the regions.
2381 */
2382 base = devm_ioremap_resource(&pdev->dev, res);
2383 if (IS_ERR(base))
2384 return PTR_ERR(base);
2385
2386 pcdev->irq = irq;
2387 pcdev->base = base;
2388
2389 /* request dma */
2390 dma_cap_zero(mask);
2391 dma_cap_set(DMA_SLAVE, mask);
2392 dma_cap_set(DMA_PRIVATE, mask);
2393
2394 params.prio = 0;
2395 params.drcmr = 68;
2396 pcdev->dma_chans[0] =
2397 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2398 &params, &pdev->dev, "CI_Y");
2399 if (!pcdev->dma_chans[0]) {
2400 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2401 return -ENODEV;
2402 }
2403
2404 params.drcmr = 69;
2405 pcdev->dma_chans[1] =
2406 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2407 &params, &pdev->dev, "CI_U");
2408 if (!pcdev->dma_chans[1]) {
2409 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2410 err = -ENODEV;
2411 goto exit_free_dma_y;
2412 }
2413
2414 params.drcmr = 70;
2415 pcdev->dma_chans[2] =
2416 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2417 &params, &pdev->dev, "CI_V");
2418 if (!pcdev->dma_chans[2]) {
2419 dev_err(&pdev->dev, "Can't request DMA for V\n");
2420 err = -ENODEV;
2421 goto exit_free_dma_u;
2422 }
2423
2424 for (i = 0; i < 3; i++) {
2425 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2426 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2427 if (err < 0) {
2428 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2429 err);
2430 goto exit_free_dma;
2431 }
2432 }
2433
2434 /* request irq */
2435 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2436 PXA_CAM_DRV_NAME, pcdev);
2437 if (err) {
2438 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2439 goto exit_free_dma;
2440 }
2441
2442 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2443
2444 pxa_camera_activate(pcdev);
2445
2446 dev_set_drvdata(&pdev->dev, pcdev);
2447 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2448 if (err)
2449 goto exit_free_dma;
2450
2451 pcdev->asds[0] = &pcdev->asd;
2452 pcdev->notifier.subdevs = pcdev->asds;
2453 pcdev->notifier.num_subdevs = 1;
2454 pcdev->notifier.bound = pxa_camera_sensor_bound;
2455 pcdev->notifier.unbind = pxa_camera_sensor_unbind;
2456
2457 if (!of_have_populated_dt())
2458 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2459
2460 err = pxa_camera_init_videobuf2(pcdev);
2461 if (err)
2462 goto exit_free_v4l2dev;
2463
2464 if (pcdev->mclk) {
2465 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2466 pcdev->asd.match.i2c.adapter_id,
2467 pcdev->asd.match.i2c.address);
2468
2469 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2470 clk_name, NULL);
2471 if (IS_ERR(pcdev->mclk_clk)) {
2472 err = PTR_ERR(pcdev->mclk_clk);
2473 goto exit_free_v4l2dev;
2474 }
2475 }
2476
2477 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2478 if (err)
2479 goto exit_free_clk;
2480
2481 return 0;
2482 exit_free_clk:
2483 v4l2_clk_unregister(pcdev->mclk_clk);
2484 exit_free_v4l2dev:
2485 v4l2_device_unregister(&pcdev->v4l2_dev);
2486 exit_free_dma:
2487 dma_release_channel(pcdev->dma_chans[2]);
2488 exit_free_dma_u:
2489 dma_release_channel(pcdev->dma_chans[1]);
2490 exit_free_dma_y:
2491 dma_release_channel(pcdev->dma_chans[0]);
2492 return err;
2493 }
2494
2495 static int pxa_camera_remove(struct platform_device *pdev)
2496 {
2497 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2498
2499 pxa_camera_deactivate(pcdev);
2500 dma_release_channel(pcdev->dma_chans[0]);
2501 dma_release_channel(pcdev->dma_chans[1]);
2502 dma_release_channel(pcdev->dma_chans[2]);
2503
2504 v4l2_clk_unregister(pcdev->mclk_clk);
2505 v4l2_device_unregister(&pcdev->v4l2_dev);
2506
2507 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2508
2509 return 0;
2510 }
2511
2512 static const struct dev_pm_ops pxa_camera_pm = {
2513 .suspend = pxa_camera_suspend,
2514 .resume = pxa_camera_resume,
2515 };
2516
2517 static const struct of_device_id pxa_camera_of_match[] = {
2518 { .compatible = "marvell,pxa270-qci", },
2519 {},
2520 };
2521 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2522
2523 static struct platform_driver pxa_camera_driver = {
2524 .driver = {
2525 .name = PXA_CAM_DRV_NAME,
2526 .pm = &pxa_camera_pm,
2527 .of_match_table = of_match_ptr(pxa_camera_of_match),
2528 },
2529 .probe = pxa_camera_probe,
2530 .remove = pxa_camera_remove,
2531 };
2532
2533 module_platform_driver(pxa_camera_driver);
2534
2535 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2536 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2537 MODULE_LICENSE("GPL");
2538 MODULE_VERSION(PXA_CAM_VERSION);
2539 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux with added FPC-III support