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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blob6152a05877236d8728aece77c1dd293d0825f365
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
37
38 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40
41 int mfc_debug_level;
42 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44
45 /* Helper functions for interrupt processing */
46
47 /* Remove from hw execution round robin */
48 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 {
50 struct s5p_mfc_dev *dev = ctx->dev;
51
52 spin_lock(&dev->condlock);
53 __clear_bit(ctx->num, &dev->ctx_work_bits);
54 spin_unlock(&dev->condlock);
55 }
56
57 /* Add to hw execution round robin */
58 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 {
60 struct s5p_mfc_dev *dev = ctx->dev;
61
62 spin_lock(&dev->condlock);
63 __set_bit(ctx->num, &dev->ctx_work_bits);
64 spin_unlock(&dev->condlock);
65 }
66
67 /* Remove from hw execution round robin */
68 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 {
70 struct s5p_mfc_dev *dev = ctx->dev;
71 unsigned long flags;
72
73 spin_lock_irqsave(&dev->condlock, flags);
74 __clear_bit(ctx->num, &dev->ctx_work_bits);
75 spin_unlock_irqrestore(&dev->condlock, flags);
76 }
77
78 /* Add to hw execution round robin */
79 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 {
81 struct s5p_mfc_dev *dev = ctx->dev;
82 unsigned long flags;
83
84 spin_lock_irqsave(&dev->condlock, flags);
85 __set_bit(ctx->num, &dev->ctx_work_bits);
86 spin_unlock_irqrestore(&dev->condlock, flags);
87 }
88
89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
90 {
91 unsigned long flags;
92 int ctx;
93
94 spin_lock_irqsave(&dev->condlock, flags);
95 ctx = dev->curr_ctx;
96 do {
97 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
98 if (ctx == dev->curr_ctx) {
99 if (!test_bit(ctx, &dev->ctx_work_bits))
100 ctx = -EAGAIN;
101 break;
102 }
103 } while (!test_bit(ctx, &dev->ctx_work_bits));
104 spin_unlock_irqrestore(&dev->condlock, flags);
105
106 return ctx;
107 }
108
109 /* Wake up context wait_queue */
110 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
111 unsigned int err)
112 {
113 ctx->int_cond = 1;
114 ctx->int_type = reason;
115 ctx->int_err = err;
116 wake_up(&ctx->queue);
117 }
118
119 /* Wake up device wait_queue */
120 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
121 unsigned int err)
122 {
123 dev->int_cond = 1;
124 dev->int_type = reason;
125 dev->int_err = err;
126 wake_up(&dev->queue);
127 }
128
129 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
130 {
131 struct s5p_mfc_buf *b;
132 int i;
133
134 while (!list_empty(lh)) {
135 b = list_entry(lh->next, struct s5p_mfc_buf, list);
136 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
137 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
138 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
139 list_del(&b->list);
140 }
141 }
142
143 static void s5p_mfc_watchdog(unsigned long arg)
144 {
145 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
146
147 if (test_bit(0, &dev->hw_lock))
148 atomic_inc(&dev->watchdog_cnt);
149 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
150 /* This means that hw is busy and no interrupts were
151 * generated by hw for the Nth time of running this
152 * watchdog timer. This usually means a serious hw
153 * error. Now it is time to kill all instances and
154 * reset the MFC. */
155 mfc_err("Time out during waiting for HW\n");
156 schedule_work(&dev->watchdog_work);
157 }
158 dev->watchdog_timer.expires = jiffies +
159 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
160 add_timer(&dev->watchdog_timer);
161 }
162
163 static void s5p_mfc_watchdog_worker(struct work_struct *work)
164 {
165 struct s5p_mfc_dev *dev;
166 struct s5p_mfc_ctx *ctx;
167 unsigned long flags;
168 int mutex_locked;
169 int i, ret;
170
171 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
172
173 mfc_err("Driver timeout error handling\n");
174 /* Lock the mutex that protects open and release.
175 * This is necessary as they may load and unload firmware. */
176 mutex_locked = mutex_trylock(&dev->mfc_mutex);
177 if (!mutex_locked)
178 mfc_err("Error: some instance may be closing/opening\n");
179 spin_lock_irqsave(&dev->irqlock, flags);
180
181 s5p_mfc_clock_off();
182
183 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
184 ctx = dev->ctx[i];
185 if (!ctx)
186 continue;
187 ctx->state = MFCINST_ERROR;
188 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
189 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
190 clear_work_bit(ctx);
191 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
192 }
193 clear_bit(0, &dev->hw_lock);
194 spin_unlock_irqrestore(&dev->irqlock, flags);
195
196 /* De-init MFC */
197 s5p_mfc_deinit_hw(dev);
198
199 /* Double check if there is at least one instance running.
200 * If no instance is in memory than no firmware should be present */
201 if (dev->num_inst > 0) {
202 ret = s5p_mfc_load_firmware(dev);
203 if (ret) {
204 mfc_err("Failed to reload FW\n");
205 goto unlock;
206 }
207 s5p_mfc_clock_on();
208 ret = s5p_mfc_init_hw(dev);
209 s5p_mfc_clock_off();
210 if (ret)
211 mfc_err("Failed to reinit FW\n");
212 }
213 unlock:
214 if (mutex_locked)
215 mutex_unlock(&dev->mfc_mutex);
216 }
217
218 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
219 {
220 struct s5p_mfc_buf *dst_buf;
221 struct s5p_mfc_dev *dev = ctx->dev;
222
223 ctx->state = MFCINST_FINISHED;
224 ctx->sequence++;
225 while (!list_empty(&ctx->dst_queue)) {
226 dst_buf = list_entry(ctx->dst_queue.next,
227 struct s5p_mfc_buf, list);
228 mfc_debug(2, "Cleaning up buffer: %d\n",
229 dst_buf->b->vb2_buf.index);
230 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
231 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
232 list_del(&dst_buf->list);
233 dst_buf->flags |= MFC_BUF_FLAG_EOS;
234 ctx->dst_queue_cnt--;
235 dst_buf->b->sequence = (ctx->sequence++);
236
237 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
238 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
239 dst_buf->b->field = V4L2_FIELD_NONE;
240 else
241 dst_buf->b->field = V4L2_FIELD_INTERLACED;
242 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
243
244 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
245 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
246 }
247 }
248
249 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
250 {
251 struct s5p_mfc_dev *dev = ctx->dev;
252 struct s5p_mfc_buf *dst_buf, *src_buf;
253 size_t dec_y_addr;
254 unsigned int frame_type;
255
256 /* Make sure we actually have a new frame before continuing. */
257 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
258 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
259 return;
260 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
261
262 /* Copy timestamp / timecode from decoded src to dst and set
263 appropriate flags. */
264 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
265 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
266 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
267 == dec_y_addr) {
268 dst_buf->b->timecode =
269 src_buf->b->timecode;
270 dst_buf->b->vb2_buf.timestamp =
271 src_buf->b->vb2_buf.timestamp;
272 dst_buf->b->flags &=
273 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
274 dst_buf->b->flags |=
275 src_buf->b->flags
276 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
277 switch (frame_type) {
278 case S5P_FIMV_DECODE_FRAME_I_FRAME:
279 dst_buf->b->flags |=
280 V4L2_BUF_FLAG_KEYFRAME;
281 break;
282 case S5P_FIMV_DECODE_FRAME_P_FRAME:
283 dst_buf->b->flags |=
284 V4L2_BUF_FLAG_PFRAME;
285 break;
286 case S5P_FIMV_DECODE_FRAME_B_FRAME:
287 dst_buf->b->flags |=
288 V4L2_BUF_FLAG_BFRAME;
289 break;
290 default:
291 /* Don't know how to handle
292 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
293 mfc_debug(2, "Unexpected frame type: %d\n",
294 frame_type);
295 }
296 break;
297 }
298 }
299 }
300
301 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
302 {
303 struct s5p_mfc_dev *dev = ctx->dev;
304 struct s5p_mfc_buf *dst_buf;
305 size_t dspl_y_addr;
306 unsigned int frame_type;
307
308 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
309 if (IS_MFCV6_PLUS(dev))
310 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
311 get_disp_frame_type, ctx);
312 else
313 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
314 get_dec_frame_type, dev);
315
316 /* If frame is same as previous then skip and do not dequeue */
317 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
318 if (!ctx->after_packed_pb)
319 ctx->sequence++;
320 ctx->after_packed_pb = 0;
321 return;
322 }
323 ctx->sequence++;
324 /* The MFC returns address of the buffer, now we have to
325 * check which videobuf does it correspond to */
326 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
327 /* Check if this is the buffer we're looking for */
328 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
329 == dspl_y_addr) {
330 list_del(&dst_buf->list);
331 ctx->dst_queue_cnt--;
332 dst_buf->b->sequence = ctx->sequence;
333 if (s5p_mfc_hw_call(dev->mfc_ops,
334 get_pic_type_top, ctx) ==
335 s5p_mfc_hw_call(dev->mfc_ops,
336 get_pic_type_bot, ctx))
337 dst_buf->b->field = V4L2_FIELD_NONE;
338 else
339 dst_buf->b->field =
340 V4L2_FIELD_INTERLACED;
341 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
342 ctx->luma_size);
343 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
344 ctx->chroma_size);
345 clear_bit(dst_buf->b->vb2_buf.index,
346 &ctx->dec_dst_flag);
347
348 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
349 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
350
351 break;
352 }
353 }
354 }
355
356 /* Handle frame decoding interrupt */
357 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
358 unsigned int reason, unsigned int err)
359 {
360 struct s5p_mfc_dev *dev = ctx->dev;
361 unsigned int dst_frame_status;
362 unsigned int dec_frame_status;
363 struct s5p_mfc_buf *src_buf;
364 unsigned int res_change;
365
366 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
367 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
368 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
369 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
370 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
371 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
372 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
373 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
374 if (ctx->state == MFCINST_RES_CHANGE_INIT)
375 ctx->state = MFCINST_RES_CHANGE_FLUSH;
376 if (res_change == S5P_FIMV_RES_INCREASE ||
377 res_change == S5P_FIMV_RES_DECREASE) {
378 ctx->state = MFCINST_RES_CHANGE_INIT;
379 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
380 wake_up_ctx(ctx, reason, err);
381 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
382 s5p_mfc_clock_off();
383 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
384 return;
385 }
386 if (ctx->dpb_flush_flag)
387 ctx->dpb_flush_flag = 0;
388
389 /* All frames remaining in the buffer have been extracted */
390 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
391 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
392 static const struct v4l2_event ev_src_ch = {
393 .type = V4L2_EVENT_SOURCE_CHANGE,
394 .u.src_change.changes =
395 V4L2_EVENT_SRC_CH_RESOLUTION,
396 };
397
398 s5p_mfc_handle_frame_all_extracted(ctx);
399 ctx->state = MFCINST_RES_CHANGE_END;
400 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
401
402 goto leave_handle_frame;
403 } else {
404 s5p_mfc_handle_frame_all_extracted(ctx);
405 }
406 }
407
408 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
409 s5p_mfc_handle_frame_copy_time(ctx);
410
411 /* A frame has been decoded and is in the buffer */
412 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
413 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
414 s5p_mfc_handle_frame_new(ctx, err);
415 } else {
416 mfc_debug(2, "No frame decode\n");
417 }
418 /* Mark source buffer as complete */
419 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
420 && !list_empty(&ctx->src_queue)) {
421 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
422 list);
423 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
424 get_consumed_stream, dev);
425 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
426 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
427 ctx->consumed_stream + STUFF_BYTE <
428 src_buf->b->vb2_buf.planes[0].bytesused) {
429 /* Run MFC again on the same buffer */
430 mfc_debug(2, "Running again the same buffer\n");
431 ctx->after_packed_pb = 1;
432 } else {
433 mfc_debug(2, "MFC needs next buffer\n");
434 ctx->consumed_stream = 0;
435 if (src_buf->flags & MFC_BUF_FLAG_EOS)
436 ctx->state = MFCINST_FINISHING;
437 list_del(&src_buf->list);
438 ctx->src_queue_cnt--;
439 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
440 vb2_buffer_done(&src_buf->b->vb2_buf,
441 VB2_BUF_STATE_ERROR);
442 else
443 vb2_buffer_done(&src_buf->b->vb2_buf,
444 VB2_BUF_STATE_DONE);
445 }
446 }
447 leave_handle_frame:
448 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
449 || ctx->dst_queue_cnt < ctx->pb_count)
450 clear_work_bit(ctx);
451 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
452 wake_up_ctx(ctx, reason, err);
453 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
454 s5p_mfc_clock_off();
455 /* if suspending, wake up device and do not try_run again*/
456 if (test_bit(0, &dev->enter_suspend))
457 wake_up_dev(dev, reason, err);
458 else
459 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
460 }
461
462 /* Error handling for interrupt */
463 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
464 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
465 {
466 mfc_err("Interrupt Error: %08x\n", err);
467
468 if (ctx != NULL) {
469 /* Error recovery is dependent on the state of context */
470 switch (ctx->state) {
471 case MFCINST_RES_CHANGE_INIT:
472 case MFCINST_RES_CHANGE_FLUSH:
473 case MFCINST_RES_CHANGE_END:
474 case MFCINST_FINISHING:
475 case MFCINST_FINISHED:
476 case MFCINST_RUNNING:
477 /* It is highly probable that an error occurred
478 * while decoding a frame */
479 clear_work_bit(ctx);
480 ctx->state = MFCINST_ERROR;
481 /* Mark all dst buffers as having an error */
482 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
483 /* Mark all src buffers as having an error */
484 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
485 wake_up_ctx(ctx, reason, err);
486 break;
487 default:
488 clear_work_bit(ctx);
489 ctx->state = MFCINST_ERROR;
490 wake_up_ctx(ctx, reason, err);
491 break;
492 }
493 }
494 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
495 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
496 s5p_mfc_clock_off();
497 wake_up_dev(dev, reason, err);
498 }
499
500 /* Header parsing interrupt handling */
501 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
502 unsigned int reason, unsigned int err)
503 {
504 struct s5p_mfc_dev *dev;
505
506 if (ctx == NULL)
507 return;
508 dev = ctx->dev;
509 if (ctx->c_ops->post_seq_start) {
510 if (ctx->c_ops->post_seq_start(ctx))
511 mfc_err("post_seq_start() failed\n");
512 } else {
513 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
514 dev);
515 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
516 dev);
517
518 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
519
520 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
521 dev);
522 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
523 dev);
524 if (ctx->img_width == 0 || ctx->img_height == 0)
525 ctx->state = MFCINST_ERROR;
526 else
527 ctx->state = MFCINST_HEAD_PARSED;
528
529 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
530 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
531 !list_empty(&ctx->src_queue)) {
532 struct s5p_mfc_buf *src_buf;
533 src_buf = list_entry(ctx->src_queue.next,
534 struct s5p_mfc_buf, list);
535 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
536 dev) <
537 src_buf->b->vb2_buf.planes[0].bytesused)
538 ctx->head_processed = 0;
539 else
540 ctx->head_processed = 1;
541 } else {
542 ctx->head_processed = 1;
543 }
544 }
545 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
546 clear_work_bit(ctx);
547 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
548 s5p_mfc_clock_off();
549 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
550 wake_up_ctx(ctx, reason, err);
551 }
552
553 /* Header parsing interrupt handling */
554 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
555 unsigned int reason, unsigned int err)
556 {
557 struct s5p_mfc_buf *src_buf;
558 struct s5p_mfc_dev *dev;
559
560 if (ctx == NULL)
561 return;
562 dev = ctx->dev;
563 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
564 ctx->int_type = reason;
565 ctx->int_err = err;
566 ctx->int_cond = 1;
567 clear_work_bit(ctx);
568 if (err == 0) {
569 ctx->state = MFCINST_RUNNING;
570 if (!ctx->dpb_flush_flag && ctx->head_processed) {
571 if (!list_empty(&ctx->src_queue)) {
572 src_buf = list_entry(ctx->src_queue.next,
573 struct s5p_mfc_buf, list);
574 list_del(&src_buf->list);
575 ctx->src_queue_cnt--;
576 vb2_buffer_done(&src_buf->b->vb2_buf,
577 VB2_BUF_STATE_DONE);
578 }
579 } else {
580 ctx->dpb_flush_flag = 0;
581 }
582 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
583
584 s5p_mfc_clock_off();
585
586 wake_up(&ctx->queue);
587 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
588 } else {
589 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
590
591 s5p_mfc_clock_off();
592
593 wake_up(&ctx->queue);
594 }
595 }
596
597 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
598 {
599 struct s5p_mfc_dev *dev = ctx->dev;
600 struct s5p_mfc_buf *mb_entry;
601
602 mfc_debug(2, "Stream completed\n");
603
604 ctx->state = MFCINST_FINISHED;
605
606 if (!list_empty(&ctx->dst_queue)) {
607 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
608 list);
609 list_del(&mb_entry->list);
610 ctx->dst_queue_cnt--;
611 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
612 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
613 }
614
615 clear_work_bit(ctx);
616
617 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
618
619 s5p_mfc_clock_off();
620 wake_up(&ctx->queue);
621 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
622 }
623
624 /* Interrupt processing */
625 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
626 {
627 struct s5p_mfc_dev *dev = priv;
628 struct s5p_mfc_ctx *ctx;
629 unsigned int reason;
630 unsigned int err;
631
632 mfc_debug_enter();
633 /* Reset the timeout watchdog */
634 atomic_set(&dev->watchdog_cnt, 0);
635 spin_lock(&dev->irqlock);
636 ctx = dev->ctx[dev->curr_ctx];
637 /* Get the reason of interrupt and the error code */
638 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
639 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
640 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
641 switch (reason) {
642 case S5P_MFC_R2H_CMD_ERR_RET:
643 /* An error has occurred */
644 if (ctx->state == MFCINST_RUNNING &&
645 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
646 dev->warn_start ||
647 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
648 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
649 err == S5P_FIMV_ERR_TIMEOUT))
650 s5p_mfc_handle_frame(ctx, reason, err);
651 else
652 s5p_mfc_handle_error(dev, ctx, reason, err);
653 clear_bit(0, &dev->enter_suspend);
654 break;
655
656 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
657 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
658 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
659 if (ctx->c_ops->post_frame_start) {
660 if (ctx->c_ops->post_frame_start(ctx))
661 mfc_err("post_frame_start() failed\n");
662
663 if (ctx->state == MFCINST_FINISHING &&
664 list_empty(&ctx->ref_queue)) {
665 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
666 s5p_mfc_handle_stream_complete(ctx);
667 break;
668 }
669 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
670 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
671 s5p_mfc_clock_off();
672 wake_up_ctx(ctx, reason, err);
673 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
674 } else {
675 s5p_mfc_handle_frame(ctx, reason, err);
676 }
677 break;
678
679 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
680 s5p_mfc_handle_seq_done(ctx, reason, err);
681 break;
682
683 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
684 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
685 ctx->state = MFCINST_GOT_INST;
686 goto irq_cleanup_hw;
687
688 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
689 ctx->inst_no = MFC_NO_INSTANCE_SET;
690 ctx->state = MFCINST_FREE;
691 goto irq_cleanup_hw;
692
693 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
694 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
695 case S5P_MFC_R2H_CMD_SLEEP_RET:
696 case S5P_MFC_R2H_CMD_WAKEUP_RET:
697 if (ctx)
698 clear_work_bit(ctx);
699 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
700 clear_bit(0, &dev->hw_lock);
701 clear_bit(0, &dev->enter_suspend);
702 wake_up_dev(dev, reason, err);
703 break;
704
705 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
706 s5p_mfc_handle_init_buffers(ctx, reason, err);
707 break;
708
709 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
710 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
711 ctx->int_type = reason;
712 ctx->int_err = err;
713 s5p_mfc_handle_stream_complete(ctx);
714 break;
715
716 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
717 ctx->state = MFCINST_RUNNING;
718 goto irq_cleanup_hw;
719
720 default:
721 mfc_debug(2, "Unknown int reason\n");
722 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
723 }
724 spin_unlock(&dev->irqlock);
725 mfc_debug_leave();
726 return IRQ_HANDLED;
727 irq_cleanup_hw:
728 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
729 ctx->int_type = reason;
730 ctx->int_err = err;
731 ctx->int_cond = 1;
732 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
733 mfc_err("Failed to unlock hw\n");
734
735 s5p_mfc_clock_off();
736 clear_work_bit(ctx);
737 wake_up(&ctx->queue);
738
739 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
740 spin_unlock(&dev->irqlock);
741 mfc_debug(2, "Exit via irq_cleanup_hw\n");
742 return IRQ_HANDLED;
743 }
744
745 /* Open an MFC node */
746 static int s5p_mfc_open(struct file *file)
747 {
748 struct video_device *vdev = video_devdata(file);
749 struct s5p_mfc_dev *dev = video_drvdata(file);
750 struct s5p_mfc_ctx *ctx = NULL;
751 struct vb2_queue *q;
752 int ret = 0;
753
754 mfc_debug_enter();
755 if (mutex_lock_interruptible(&dev->mfc_mutex))
756 return -ERESTARTSYS;
757 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
758 /* Allocate memory for context */
759 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
760 if (!ctx) {
761 ret = -ENOMEM;
762 goto err_alloc;
763 }
764 v4l2_fh_init(&ctx->fh, vdev);
765 file->private_data = &ctx->fh;
766 v4l2_fh_add(&ctx->fh);
767 ctx->dev = dev;
768 INIT_LIST_HEAD(&ctx->src_queue);
769 INIT_LIST_HEAD(&ctx->dst_queue);
770 ctx->src_queue_cnt = 0;
771 ctx->dst_queue_cnt = 0;
772 /* Get context number */
773 ctx->num = 0;
774 while (dev->ctx[ctx->num]) {
775 ctx->num++;
776 if (ctx->num >= MFC_NUM_CONTEXTS) {
777 mfc_debug(2, "Too many open contexts\n");
778 ret = -EBUSY;
779 goto err_no_ctx;
780 }
781 }
782 /* Mark context as idle */
783 clear_work_bit_irqsave(ctx);
784 dev->ctx[ctx->num] = ctx;
785 if (vdev == dev->vfd_dec) {
786 ctx->type = MFCINST_DECODER;
787 ctx->c_ops = get_dec_codec_ops();
788 s5p_mfc_dec_init(ctx);
789 /* Setup ctrl handler */
790 ret = s5p_mfc_dec_ctrls_setup(ctx);
791 if (ret) {
792 mfc_err("Failed to setup mfc controls\n");
793 goto err_ctrls_setup;
794 }
795 } else if (vdev == dev->vfd_enc) {
796 ctx->type = MFCINST_ENCODER;
797 ctx->c_ops = get_enc_codec_ops();
798 /* only for encoder */
799 INIT_LIST_HEAD(&ctx->ref_queue);
800 ctx->ref_queue_cnt = 0;
801 s5p_mfc_enc_init(ctx);
802 /* Setup ctrl handler */
803 ret = s5p_mfc_enc_ctrls_setup(ctx);
804 if (ret) {
805 mfc_err("Failed to setup mfc controls\n");
806 goto err_ctrls_setup;
807 }
808 } else {
809 ret = -ENOENT;
810 goto err_bad_node;
811 }
812 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
813 ctx->inst_no = MFC_NO_INSTANCE_SET;
814 /* Load firmware if this is the first instance */
815 if (dev->num_inst == 1) {
816 dev->watchdog_timer.expires = jiffies +
817 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
818 add_timer(&dev->watchdog_timer);
819 ret = s5p_mfc_power_on();
820 if (ret < 0) {
821 mfc_err("power on failed\n");
822 goto err_pwr_enable;
823 }
824 s5p_mfc_clock_on();
825 ret = s5p_mfc_load_firmware(dev);
826 if (ret) {
827 s5p_mfc_clock_off();
828 goto err_load_fw;
829 }
830 /* Init the FW */
831 ret = s5p_mfc_init_hw(dev);
832 s5p_mfc_clock_off();
833 if (ret)
834 goto err_init_hw;
835 }
836 /* Init videobuf2 queue for CAPTURE */
837 q = &ctx->vq_dst;
838 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
839 q->drv_priv = &ctx->fh;
840 q->lock = &dev->mfc_mutex;
841 if (vdev == dev->vfd_dec) {
842 q->io_modes = VB2_MMAP;
843 q->ops = get_dec_queue_ops();
844 } else if (vdev == dev->vfd_enc) {
845 q->io_modes = VB2_MMAP | VB2_USERPTR;
846 q->ops = get_enc_queue_ops();
847 } else {
848 ret = -ENOENT;
849 goto err_queue_init;
850 }
851 /*
852 * We'll do mostly sequential access, so sacrifice TLB efficiency for
853 * faster allocation.
854 */
855 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
856 q->mem_ops = &vb2_dma_contig_memops;
857 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
858 ret = vb2_queue_init(q);
859 if (ret) {
860 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
861 goto err_queue_init;
862 }
863 /* Init videobuf2 queue for OUTPUT */
864 q = &ctx->vq_src;
865 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
866 q->io_modes = VB2_MMAP;
867 q->drv_priv = &ctx->fh;
868 q->lock = &dev->mfc_mutex;
869 if (vdev == dev->vfd_dec) {
870 q->io_modes = VB2_MMAP;
871 q->ops = get_dec_queue_ops();
872 } else if (vdev == dev->vfd_enc) {
873 q->io_modes = VB2_MMAP | VB2_USERPTR;
874 q->ops = get_enc_queue_ops();
875 } else {
876 ret = -ENOENT;
877 goto err_queue_init;
878 }
879 /* One way to indicate end-of-stream for MFC is to set the
880 * bytesused == 0. However by default videobuf2 handles bytesused
881 * equal to 0 as a special case and changes its value to the size
882 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
883 * will keep the value of bytesused intact.
884 */
885 q->allow_zero_bytesused = 1;
886
887 /*
888 * We'll do mostly sequential access, so sacrifice TLB efficiency for
889 * faster allocation.
890 */
891 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
892 q->mem_ops = &vb2_dma_contig_memops;
893 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
894 ret = vb2_queue_init(q);
895 if (ret) {
896 mfc_err("Failed to initialize videobuf2 queue(output)\n");
897 goto err_queue_init;
898 }
899 init_waitqueue_head(&ctx->queue);
900 mutex_unlock(&dev->mfc_mutex);
901 mfc_debug_leave();
902 return ret;
903 /* Deinit when failure occurred */
904 err_queue_init:
905 if (dev->num_inst == 1)
906 s5p_mfc_deinit_hw(dev);
907 err_init_hw:
908 err_load_fw:
909 err_pwr_enable:
910 if (dev->num_inst == 1) {
911 if (s5p_mfc_power_off() < 0)
912 mfc_err("power off failed\n");
913 del_timer_sync(&dev->watchdog_timer);
914 }
915 err_ctrls_setup:
916 s5p_mfc_dec_ctrls_delete(ctx);
917 err_bad_node:
918 dev->ctx[ctx->num] = NULL;
919 err_no_ctx:
920 v4l2_fh_del(&ctx->fh);
921 v4l2_fh_exit(&ctx->fh);
922 kfree(ctx);
923 err_alloc:
924 dev->num_inst--;
925 mutex_unlock(&dev->mfc_mutex);
926 mfc_debug_leave();
927 return ret;
928 }
929
930 /* Release MFC context */
931 static int s5p_mfc_release(struct file *file)
932 {
933 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
934 struct s5p_mfc_dev *dev = ctx->dev;
935
936 /* if dev is null, do cleanup that doesn't need dev */
937 mfc_debug_enter();
938 if (dev)
939 mutex_lock(&dev->mfc_mutex);
940 vb2_queue_release(&ctx->vq_src);
941 vb2_queue_release(&ctx->vq_dst);
942 if (dev) {
943 s5p_mfc_clock_on();
944
945 /* Mark context as idle */
946 clear_work_bit_irqsave(ctx);
947 /*
948 * If instance was initialised and not yet freed,
949 * return instance and free resources
950 */
951 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
952 mfc_debug(2, "Has to free instance\n");
953 s5p_mfc_close_mfc_inst(dev, ctx);
954 }
955 /* hardware locking scheme */
956 if (dev->curr_ctx == ctx->num)
957 clear_bit(0, &dev->hw_lock);
958 dev->num_inst--;
959 if (dev->num_inst == 0) {
960 mfc_debug(2, "Last instance\n");
961 s5p_mfc_deinit_hw(dev);
962 del_timer_sync(&dev->watchdog_timer);
963 s5p_mfc_clock_off();
964 if (s5p_mfc_power_off() < 0)
965 mfc_err("Power off failed\n");
966 } else {
967 mfc_debug(2, "Shutting down clock\n");
968 s5p_mfc_clock_off();
969 }
970 }
971 if (dev)
972 dev->ctx[ctx->num] = NULL;
973 s5p_mfc_dec_ctrls_delete(ctx);
974 v4l2_fh_del(&ctx->fh);
975 /* vdev is gone if dev is null */
976 if (dev)
977 v4l2_fh_exit(&ctx->fh);
978 kfree(ctx);
979 mfc_debug_leave();
980 if (dev)
981 mutex_unlock(&dev->mfc_mutex);
982
983 return 0;
984 }
985
986 /* Poll */
987 static unsigned int s5p_mfc_poll(struct file *file,
988 struct poll_table_struct *wait)
989 {
990 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
991 struct s5p_mfc_dev *dev = ctx->dev;
992 struct vb2_queue *src_q, *dst_q;
993 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
994 unsigned int rc = 0;
995 unsigned long flags;
996
997 mutex_lock(&dev->mfc_mutex);
998 src_q = &ctx->vq_src;
999 dst_q = &ctx->vq_dst;
1000 /*
1001 * There has to be at least one buffer queued on each queued_list, which
1002 * means either in driver already or waiting for driver to claim it
1003 * and start processing.
1004 */
1005 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1006 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1007 rc = POLLERR;
1008 goto end;
1009 }
1010 mutex_unlock(&dev->mfc_mutex);
1011 poll_wait(file, &ctx->fh.wait, wait);
1012 poll_wait(file, &src_q->done_wq, wait);
1013 poll_wait(file, &dst_q->done_wq, wait);
1014 mutex_lock(&dev->mfc_mutex);
1015 if (v4l2_event_pending(&ctx->fh))
1016 rc |= POLLPRI;
1017 spin_lock_irqsave(&src_q->done_lock, flags);
1018 if (!list_empty(&src_q->done_list))
1019 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1020 done_entry);
1021 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1022 || src_vb->state == VB2_BUF_STATE_ERROR))
1023 rc |= POLLOUT | POLLWRNORM;
1024 spin_unlock_irqrestore(&src_q->done_lock, flags);
1025 spin_lock_irqsave(&dst_q->done_lock, flags);
1026 if (!list_empty(&dst_q->done_list))
1027 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1028 done_entry);
1029 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1030 || dst_vb->state == VB2_BUF_STATE_ERROR))
1031 rc |= POLLIN | POLLRDNORM;
1032 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1033 end:
1034 mutex_unlock(&dev->mfc_mutex);
1035 return rc;
1036 }
1037
1038 /* Mmap */
1039 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1040 {
1041 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1042 struct s5p_mfc_dev *dev = ctx->dev;
1043 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1044 int ret;
1045
1046 if (mutex_lock_interruptible(&dev->mfc_mutex))
1047 return -ERESTARTSYS;
1048 if (offset < DST_QUEUE_OFF_BASE) {
1049 mfc_debug(2, "mmaping source\n");
1050 ret = vb2_mmap(&ctx->vq_src, vma);
1051 } else { /* capture */
1052 mfc_debug(2, "mmaping destination\n");
1053 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1054 ret = vb2_mmap(&ctx->vq_dst, vma);
1055 }
1056 mutex_unlock(&dev->mfc_mutex);
1057 return ret;
1058 }
1059
1060 /* v4l2 ops */
1061 static const struct v4l2_file_operations s5p_mfc_fops = {
1062 .owner = THIS_MODULE,
1063 .open = s5p_mfc_open,
1064 .release = s5p_mfc_release,
1065 .poll = s5p_mfc_poll,
1066 .unlocked_ioctl = video_ioctl2,
1067 .mmap = s5p_mfc_mmap,
1068 };
1069
1070 /* DMA memory related helper functions */
1071 static void s5p_mfc_memdev_release(struct device *dev)
1072 {
1073 of_reserved_mem_device_release(dev);
1074 }
1075
1076 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1077 const char *name, unsigned int idx)
1078 {
1079 struct device *child;
1080 int ret;
1081
1082 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1083 if (!child)
1084 return NULL;
1085
1086 device_initialize(child);
1087 dev_set_name(child, "%s:%s", dev_name(dev), name);
1088 child->parent = dev;
1089 child->bus = dev->bus;
1090 child->coherent_dma_mask = dev->coherent_dma_mask;
1091 child->dma_mask = dev->dma_mask;
1092 child->release = s5p_mfc_memdev_release;
1093
1094 if (device_add(child) == 0) {
1095 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1096 idx);
1097 if (ret == 0)
1098 return child;
1099 device_del(child);
1100 }
1101
1102 put_device(child);
1103 return NULL;
1104 }
1105
1106 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1107 {
1108 struct device *dev = &mfc_dev->plat_dev->dev;
1109
1110 /*
1111 * When IOMMU is available, we cannot use the default configuration,
1112 * because of MFC firmware requirements: address space limited to
1113 * 256M and non-zero default start address.
1114 * This is still simplified, not optimal configuration, but for now
1115 * IOMMU core doesn't allow to configure device's IOMMUs channel
1116 * separately.
1117 */
1118 if (exynos_is_iommu_available(dev)) {
1119 int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1120 S5P_MFC_IOMMU_DMA_SIZE);
1121 if (ret == 0)
1122 mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1123 return ret;
1124 }
1125
1126 /*
1127 * Create and initialize virtual devices for accessing
1128 * reserved memory regions.
1129 */
1130 mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1131 MFC_BANK1_ALLOC_CTX);
1132 if (!mfc_dev->mem_dev_l)
1133 return -ENODEV;
1134 mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1135 MFC_BANK2_ALLOC_CTX);
1136 if (!mfc_dev->mem_dev_r) {
1137 device_unregister(mfc_dev->mem_dev_l);
1138 return -ENODEV;
1139 }
1140
1141 return 0;
1142 }
1143
1144 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1145 {
1146 struct device *dev = &mfc_dev->plat_dev->dev;
1147
1148 if (exynos_is_iommu_available(dev)) {
1149 exynos_unconfigure_iommu(dev);
1150 return;
1151 }
1152
1153 device_unregister(mfc_dev->mem_dev_l);
1154 device_unregister(mfc_dev->mem_dev_r);
1155 }
1156
1157 static void *mfc_get_drv_data(struct platform_device *pdev);
1158
1159 /* MFC probe function */
1160 static int s5p_mfc_probe(struct platform_device *pdev)
1161 {
1162 struct s5p_mfc_dev *dev;
1163 struct video_device *vfd;
1164 struct resource *res;
1165 int ret;
1166
1167 pr_debug("%s++\n", __func__);
1168 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1169 if (!dev) {
1170 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1171 return -ENOMEM;
1172 }
1173
1174 spin_lock_init(&dev->irqlock);
1175 spin_lock_init(&dev->condlock);
1176 dev->plat_dev = pdev;
1177 if (!dev->plat_dev) {
1178 dev_err(&pdev->dev, "No platform data specified\n");
1179 return -ENODEV;
1180 }
1181
1182 dev->variant = mfc_get_drv_data(pdev);
1183
1184 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1185 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1186 if (IS_ERR(dev->regs_base))
1187 return PTR_ERR(dev->regs_base);
1188
1189 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1190 if (res == NULL) {
1191 dev_err(&pdev->dev, "failed to get irq resource\n");
1192 return -ENOENT;
1193 }
1194 dev->irq = res->start;
1195 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1196 0, pdev->name, dev);
1197 if (ret) {
1198 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1199 return ret;
1200 }
1201
1202 ret = s5p_mfc_configure_dma_memory(dev);
1203 if (ret < 0) {
1204 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1205 return ret;
1206 }
1207
1208 ret = s5p_mfc_init_pm(dev);
1209 if (ret < 0) {
1210 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1211 goto err_dma;
1212 }
1213
1214 vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1215 vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1216
1217 mutex_init(&dev->mfc_mutex);
1218
1219 ret = s5p_mfc_alloc_firmware(dev);
1220 if (ret)
1221 goto err_res;
1222
1223 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1224 if (ret)
1225 goto err_v4l2_dev_reg;
1226 init_waitqueue_head(&dev->queue);
1227
1228 /* decoder */
1229 vfd = video_device_alloc();
1230 if (!vfd) {
1231 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1232 ret = -ENOMEM;
1233 goto err_dec_alloc;
1234 }
1235 vfd->fops = &s5p_mfc_fops;
1236 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1237 vfd->release = video_device_release;
1238 vfd->lock = &dev->mfc_mutex;
1239 vfd->v4l2_dev = &dev->v4l2_dev;
1240 vfd->vfl_dir = VFL_DIR_M2M;
1241 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1242 dev->vfd_dec = vfd;
1243 video_set_drvdata(vfd, dev);
1244
1245 /* encoder */
1246 vfd = video_device_alloc();
1247 if (!vfd) {
1248 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1249 ret = -ENOMEM;
1250 goto err_enc_alloc;
1251 }
1252 vfd->fops = &s5p_mfc_fops;
1253 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1254 vfd->release = video_device_release;
1255 vfd->lock = &dev->mfc_mutex;
1256 vfd->v4l2_dev = &dev->v4l2_dev;
1257 vfd->vfl_dir = VFL_DIR_M2M;
1258 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1259 dev->vfd_enc = vfd;
1260 video_set_drvdata(vfd, dev);
1261 platform_set_drvdata(pdev, dev);
1262
1263 dev->hw_lock = 0;
1264 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1265 atomic_set(&dev->watchdog_cnt, 0);
1266 init_timer(&dev->watchdog_timer);
1267 dev->watchdog_timer.data = (unsigned long)dev;
1268 dev->watchdog_timer.function = s5p_mfc_watchdog;
1269
1270 /* Initialize HW ops and commands based on MFC version */
1271 s5p_mfc_init_hw_ops(dev);
1272 s5p_mfc_init_hw_cmds(dev);
1273 s5p_mfc_init_regs(dev);
1274
1275 /* Register decoder and encoder */
1276 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1277 if (ret) {
1278 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1279 goto err_dec_reg;
1280 }
1281 v4l2_info(&dev->v4l2_dev,
1282 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1283
1284 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1285 if (ret) {
1286 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1287 goto err_enc_reg;
1288 }
1289 v4l2_info(&dev->v4l2_dev,
1290 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1291
1292 pr_debug("%s--\n", __func__);
1293 return 0;
1294
1295 /* Deinit MFC if probe had failed */
1296 err_enc_reg:
1297 video_unregister_device(dev->vfd_dec);
1298 err_dec_reg:
1299 video_device_release(dev->vfd_enc);
1300 err_enc_alloc:
1301 video_device_release(dev->vfd_dec);
1302 err_dec_alloc:
1303 v4l2_device_unregister(&dev->v4l2_dev);
1304 err_v4l2_dev_reg:
1305 s5p_mfc_release_firmware(dev);
1306 err_res:
1307 s5p_mfc_final_pm(dev);
1308 err_dma:
1309 s5p_mfc_unconfigure_dma_memory(dev);
1310
1311 pr_debug("%s-- with error\n", __func__);
1312 return ret;
1313
1314 }
1315
1316 /* Remove the driver */
1317 static int s5p_mfc_remove(struct platform_device *pdev)
1318 {
1319 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1320 struct s5p_mfc_ctx *ctx;
1321 int i;
1322
1323 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1324
1325 /*
1326 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1327 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1328 * after s5p_mfc_remove() is run during unbind.
1329 */
1330 mutex_lock(&dev->mfc_mutex);
1331 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1332 ctx = dev->ctx[i];
1333 if (!ctx)
1334 continue;
1335 /* clear ctx->dev */
1336 ctx->dev = NULL;
1337 }
1338 mutex_unlock(&dev->mfc_mutex);
1339
1340 del_timer_sync(&dev->watchdog_timer);
1341 flush_work(&dev->watchdog_work);
1342
1343 video_unregister_device(dev->vfd_enc);
1344 video_unregister_device(dev->vfd_dec);
1345 video_device_release(dev->vfd_enc);
1346 video_device_release(dev->vfd_dec);
1347 v4l2_device_unregister(&dev->v4l2_dev);
1348 s5p_mfc_release_firmware(dev);
1349 s5p_mfc_unconfigure_dma_memory(dev);
1350 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1351 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1352
1353 s5p_mfc_final_pm(dev);
1354 return 0;
1355 }
1356
1357 #ifdef CONFIG_PM_SLEEP
1358
1359 static int s5p_mfc_suspend(struct device *dev)
1360 {
1361 struct platform_device *pdev = to_platform_device(dev);
1362 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1363 int ret;
1364
1365 if (m_dev->num_inst == 0)
1366 return 0;
1367
1368 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1369 mfc_err("Error: going to suspend for a second time\n");
1370 return -EIO;
1371 }
1372
1373 /* Check if we're processing then wait if it necessary. */
1374 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1375 /* Try and lock the HW */
1376 /* Wait on the interrupt waitqueue */
1377 ret = wait_event_interruptible_timeout(m_dev->queue,
1378 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1379 if (ret == 0) {
1380 mfc_err("Waiting for hardware to finish timed out\n");
1381 clear_bit(0, &m_dev->enter_suspend);
1382 return -EIO;
1383 }
1384 }
1385
1386 ret = s5p_mfc_sleep(m_dev);
1387 if (ret) {
1388 clear_bit(0, &m_dev->enter_suspend);
1389 clear_bit(0, &m_dev->hw_lock);
1390 }
1391 return ret;
1392 }
1393
1394 static int s5p_mfc_resume(struct device *dev)
1395 {
1396 struct platform_device *pdev = to_platform_device(dev);
1397 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1398
1399 if (m_dev->num_inst == 0)
1400 return 0;
1401 return s5p_mfc_wakeup(m_dev);
1402 }
1403 #endif
1404
1405 /* Power management */
1406 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1407 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1408 };
1409
1410 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1411 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1412 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1413 .dsc = DESC_BUF_SIZE,
1414 .shm = SHARED_BUF_SIZE,
1415 };
1416
1417 static struct s5p_mfc_buf_size buf_size_v5 = {
1418 .fw = MAX_FW_SIZE,
1419 .cpb = MAX_CPB_SIZE,
1420 .priv = &mfc_buf_size_v5,
1421 };
1422
1423 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1424 .base = MFC_BASE_ALIGN_ORDER,
1425 };
1426
1427 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1428 .version = MFC_VERSION,
1429 .version_bit = MFC_V5_BIT,
1430 .port_num = MFC_NUM_PORTS,
1431 .buf_size = &buf_size_v5,
1432 .buf_align = &mfc_buf_align_v5,
1433 .fw_name[0] = "s5p-mfc.fw",
1434 .clk_names = {"mfc", "sclk_mfc"},
1435 .num_clocks = 2,
1436 .use_clock_gating = true,
1437 };
1438
1439 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1440 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1441 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1442 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1443 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1444 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1445 };
1446
1447 static struct s5p_mfc_buf_size buf_size_v6 = {
1448 .fw = MAX_FW_SIZE_V6,
1449 .cpb = MAX_CPB_SIZE_V6,
1450 .priv = &mfc_buf_size_v6,
1451 };
1452
1453 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1454 .base = 0,
1455 };
1456
1457 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1458 .version = MFC_VERSION_V6,
1459 .version_bit = MFC_V6_BIT,
1460 .port_num = MFC_NUM_PORTS_V6,
1461 .buf_size = &buf_size_v6,
1462 .buf_align = &mfc_buf_align_v6,
1463 .fw_name[0] = "s5p-mfc-v6.fw",
1464 /*
1465 * v6-v2 firmware contains bug fixes and interface change
1466 * for init buffer command
1467 */
1468 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1469 .clk_names = {"mfc"},
1470 .num_clocks = 1,
1471 };
1472
1473 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1474 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1475 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1476 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1477 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1478 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1479 };
1480
1481 static struct s5p_mfc_buf_size buf_size_v7 = {
1482 .fw = MAX_FW_SIZE_V7,
1483 .cpb = MAX_CPB_SIZE_V7,
1484 .priv = &mfc_buf_size_v7,
1485 };
1486
1487 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1488 .base = 0,
1489 };
1490
1491 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1492 .version = MFC_VERSION_V7,
1493 .version_bit = MFC_V7_BIT,
1494 .port_num = MFC_NUM_PORTS_V7,
1495 .buf_size = &buf_size_v7,
1496 .buf_align = &mfc_buf_align_v7,
1497 .fw_name[0] = "s5p-mfc-v7.fw",
1498 .clk_names = {"mfc", "sclk_mfc"},
1499 .num_clocks = 2,
1500 };
1501
1502 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1503 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1504 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1505 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1506 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1507 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1508 };
1509
1510 static struct s5p_mfc_buf_size buf_size_v8 = {
1511 .fw = MAX_FW_SIZE_V8,
1512 .cpb = MAX_CPB_SIZE_V8,
1513 .priv = &mfc_buf_size_v8,
1514 };
1515
1516 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1517 .base = 0,
1518 };
1519
1520 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1521 .version = MFC_VERSION_V8,
1522 .version_bit = MFC_V8_BIT,
1523 .port_num = MFC_NUM_PORTS_V8,
1524 .buf_size = &buf_size_v8,
1525 .buf_align = &mfc_buf_align_v8,
1526 .fw_name[0] = "s5p-mfc-v8.fw",
1527 .clk_names = {"mfc"},
1528 .num_clocks = 1,
1529 };
1530
1531 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1532 .version = MFC_VERSION_V8,
1533 .version_bit = MFC_V8_BIT,
1534 .port_num = MFC_NUM_PORTS_V8,
1535 .buf_size = &buf_size_v8,
1536 .buf_align = &mfc_buf_align_v8,
1537 .fw_name[0] = "s5p-mfc-v8.fw",
1538 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1539 .num_clocks = 3,
1540 };
1541
1542 static const struct of_device_id exynos_mfc_match[] = {
1543 {
1544 .compatible = "samsung,mfc-v5",
1545 .data = &mfc_drvdata_v5,
1546 }, {
1547 .compatible = "samsung,mfc-v6",
1548 .data = &mfc_drvdata_v6,
1549 }, {
1550 .compatible = "samsung,mfc-v7",
1551 .data = &mfc_drvdata_v7,
1552 }, {
1553 .compatible = "samsung,mfc-v8",
1554 .data = &mfc_drvdata_v8,
1555 }, {
1556 .compatible = "samsung,exynos5433-mfc",
1557 .data = &mfc_drvdata_v8_5433,
1558 },
1559 {},
1560 };
1561 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1562
1563 static void *mfc_get_drv_data(struct platform_device *pdev)
1564 {
1565 struct s5p_mfc_variant *driver_data = NULL;
1566 const struct of_device_id *match;
1567
1568 match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1569 if (match)
1570 driver_data = (struct s5p_mfc_variant *)match->data;
1571
1572 return driver_data;
1573 }
1574
1575 static struct platform_driver s5p_mfc_driver = {
1576 .probe = s5p_mfc_probe,
1577 .remove = s5p_mfc_remove,
1578 .driver = {
1579 .name = S5P_MFC_NAME,
1580 .pm = &s5p_mfc_pm_ops,
1581 .of_match_table = exynos_mfc_match,
1582 },
1583 };
1584
1585 module_platform_driver(s5p_mfc_driver);
1586
1587 MODULE_LICENSE("GPL");
1588 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1589 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1590
Linux with added FPC-III support