drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h

   1 /*
   2  * c8sectpfe-core.h - C8SECTPFE STi DVB driver
   3  *
   4  * Copyright (c) STMicroelectronics 2015
   5  *
   6  *   Author:Peter Bennett <peter.bennett@st.com>
   7  *          Peter Griffin <peter.griffin@linaro.org>
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License as
  11  *      published by the Free Software Foundation; either version 2 of
  12  *      the License, or (at your option) any later version.
  13  */
  14 #ifndef _C8SECTPFE_CORE_H_
  15 #define _C8SECTPFE_CORE_H_
  16
  17 #define C8SECTPFEI_MAXCHANNEL 16
  18 #define C8SECTPFEI_MAXADAPTER 3
  19
  20 #define C8SECTPFE_MAX_TSIN_CHAN 8
  21
  22 struct channel_info {
  23
  24         int tsin_id;
  25         bool invert_ts_clk;
  26         bool serial_not_parallel;
  27         bool async_not_sync;
  28         int i2c;
  29         int dvb_card;
  30
  31         int rst_gpio;
  32
  33         struct i2c_adapter  *i2c_adapter;
  34         struct i2c_adapter  *tuner_i2c;
  35         struct i2c_adapter  *lnb_i2c;
  36         struct i2c_client   *i2c_client;
  37         struct dvb_frontend *frontend;
  38
  39         struct pinctrl_state *pstate;
  40
  41         int demux_mapping;
  42         int active;
  43
  44         void *back_buffer_start;
  45         void *back_buffer_aligned;
  46         dma_addr_t back_buffer_busaddr;
  47
  48         void *pid_buffer_start;
  49         void *pid_buffer_aligned;
  50         dma_addr_t pid_buffer_busaddr;
  51
  52         unsigned long  fifo;
  53
  54         struct completion idle_completion;
  55         struct tasklet_struct tsklet;
  56
  57         struct c8sectpfei *fei;
  58         void __iomem *irec;
  59
  60 };
  61
  62 struct c8sectpfe_hw {
  63         int num_ib;
  64         int num_mib;
  65         int num_swts;
  66         int num_tsout;
  67         int num_ccsc;
  68         int num_ram;
  69         int num_tp;
  70 };
  71
  72 struct c8sectpfei {
  73
  74         struct device *dev;
  75         struct pinctrl *pinctrl;
  76
  77         struct dentry *root;
  78         struct debugfs_regset32 *regset;
  79         struct completion fw_ack;
  80         atomic_t fw_loaded;
  81
  82         int tsin_count;
  83
  84         struct c8sectpfe_hw hw_stats;
  85
  86         struct c8sectpfe *c8sectpfe[C8SECTPFEI_MAXADAPTER];
  87
  88         int mapping[C8SECTPFEI_MAXCHANNEL];
  89
  90         struct mutex lock;
  91
  92         struct timer_list timer;        /* timer interrupts for outputs */
  93
  94         void __iomem *io;
  95         void __iomem *sram;
  96
  97         unsigned long sram_size;
  98
  99         struct channel_info *channel_data[C8SECTPFE_MAX_TSIN_CHAN];
 100
 101         struct clk *c8sectpfeclk;
 102         int nima_rst_gpio;
 103         int nimb_rst_gpio;
 104
 105         int idle_irq;
 106         int error_irq;
 107
 108         int global_feed_count;
 109 };
 110
 111 /* C8SECTPFE SYS Regs list */
 112
 113 #define SYS_INPUT_ERR_STATUS    0x0
 114 #define SYS_OTHER_ERR_STATUS    0x8
 115 #define SYS_INPUT_ERR_MASK      0x10
 116 #define SYS_OTHER_ERR_MASK      0x18
 117 #define SYS_DMA_ROUTE           0x20
 118 #define SYS_INPUT_CLKEN         0x30
 119 #define IBENABLE_MASK                   0x7F
 120
 121 #define SYS_OTHER_CLKEN         0x38
 122 #define TSDMAENABLE                     BIT(1)
 123 #define MEMDMAENABLE                    BIT(0)
 124
 125 #define SYS_CFG_NUM_IB          0x200
 126 #define SYS_CFG_NUM_MIB         0x204
 127 #define SYS_CFG_NUM_SWTS        0x208
 128 #define SYS_CFG_NUM_TSOUT       0x20C
 129 #define SYS_CFG_NUM_CCSC        0x210
 130 #define SYS_CFG_NUM_RAM         0x214
 131 #define SYS_CFG_NUM_TP          0x218
 132
 133 /* Input Block Regs */
 134
 135 #define C8SECTPFE_INPUTBLK_OFFSET       0x1000
 136 #define C8SECTPFE_CHANNEL_OFFSET(x)     ((x*0x40) + C8SECTPFE_INPUTBLK_OFFSET)
 137
 138 #define C8SECTPFE_IB_IP_FMT_CFG(x)      (C8SECTPFE_CHANNEL_OFFSET(x) + 0x00)
 139 #define C8SECTPFE_IGNORE_ERR_AT_SOP     BIT(7)
 140 #define C8SECTPFE_IGNORE_ERR_IN_PKT     BIT(6)
 141 #define C8SECTPFE_IGNORE_ERR_IN_BYTE    BIT(5)
 142 #define C8SECTPFE_INVERT_TSCLK          BIT(4)
 143 #define C8SECTPFE_ALIGN_BYTE_SOP        BIT(3)
 144 #define C8SECTPFE_ASYNC_NOT_SYNC        BIT(2)
 145 #define C8SECTPFE_BYTE_ENDIANNESS_MSB    BIT(1)
 146 #define C8SECTPFE_SERIAL_NOT_PARALLEL   BIT(0)
 147
 148 #define C8SECTPFE_IB_SYNCLCKDRP_CFG(x)   (C8SECTPFE_CHANNEL_OFFSET(x) + 0x04)
 149 #define C8SECTPFE_SYNC(x)                (x & 0xf)
 150 #define C8SECTPFE_DROP(x)                ((x<<4) & 0xf)
 151 #define C8SECTPFE_TOKEN(x)               ((x<<8) & 0xff00)
 152 #define C8SECTPFE_SLDENDIANNESS          BIT(16)
 153
 154 #define C8SECTPFE_IB_TAGBYTES_CFG(x)     (C8SECTPFE_CHANNEL_OFFSET(x) + 0x08)
 155 #define C8SECTPFE_TAG_HEADER(x)          (x << 16)
 156 #define C8SECTPFE_TAG_COUNTER(x)         ((x<<1) & 0x7fff)
 157 #define C8SECTPFE_TAG_ENABLE             BIT(0)
 158
 159 #define C8SECTPFE_IB_PID_SET(x)          (C8SECTPFE_CHANNEL_OFFSET(x) + 0x0C)
 160 #define C8SECTPFE_PID_OFFSET(x)          (x & 0x3f)
 161 #define C8SECTPFE_PID_NUMBITS(x)         ((x << 6) & 0xfff)
 162 #define C8SECTPFE_PID_ENABLE             BIT(31)
 163
 164 #define C8SECTPFE_IB_PKT_LEN(x)          (C8SECTPFE_CHANNEL_OFFSET(x) + 0x10)
 165
 166 #define C8SECTPFE_IB_BUFF_STRT(x)        (C8SECTPFE_CHANNEL_OFFSET(x) + 0x14)
 167 #define C8SECTPFE_IB_BUFF_END(x)         (C8SECTPFE_CHANNEL_OFFSET(x) + 0x18)
 168 #define C8SECTPFE_IB_READ_PNT(x)         (C8SECTPFE_CHANNEL_OFFSET(x) + 0x1C)
 169 #define C8SECTPFE_IB_WRT_PNT(x)          (C8SECTPFE_CHANNEL_OFFSET(x) + 0x20)
 170
 171 #define C8SECTPFE_IB_PRI_THRLD(x)        (C8SECTPFE_CHANNEL_OFFSET(x) + 0x24)
 172 #define C8SECTPFE_PRI_VALUE(x)           (x & 0x7fffff)
 173 #define C8SECTPFE_PRI_LOWPRI(x)          ((x & 0xf) << 24)
 174 #define C8SECTPFE_PRI_HIGHPRI(x)         ((x & 0xf) << 28)
 175
 176 #define C8SECTPFE_IB_STAT(x)             (C8SECTPFE_CHANNEL_OFFSET(x) + 0x28)
 177 #define C8SECTPFE_STAT_FIFO_OVERFLOW(x)  (x & 0x1)
 178 #define C8SECTPFE_STAT_BUFFER_OVERFLOW(x) (x & 0x2)
 179 #define C8SECTPFE_STAT_OUTOFORDERRP(x)   (x & 0x4)
 180 #define C8SECTPFE_STAT_PID_OVERFLOW(x)   (x & 0x8)
 181 #define C8SECTPFE_STAT_PKT_OVERFLOW(x)   (x & 0x10)
 182 #define C8SECTPFE_STAT_ERROR_PACKETS(x)  ((x >> 8) & 0xf)
 183 #define C8SECTPFE_STAT_SHORT_PACKETS(x)  ((x >> 12) & 0xf)
 184
 185 #define C8SECTPFE_IB_MASK(x)             (C8SECTPFE_CHANNEL_OFFSET(x) + 0x2C)
 186 #define C8SECTPFE_MASK_FIFO_OVERFLOW     BIT(0)
 187 #define C8SECTPFE_MASK_BUFFER_OVERFLOW   BIT(1)
 188 #define C8SECTPFE_MASK_OUTOFORDERRP(x)   BIT(2)
 189 #define C8SECTPFE_MASK_PID_OVERFLOW(x)   BIT(3)
 190 #define C8SECTPFE_MASK_PKT_OVERFLOW(x)   BIT(4)
 191 #define C8SECTPFE_MASK_ERROR_PACKETS(x)  ((x & 0xf) << 8)
 192 #define C8SECTPFE_MASK_SHORT_PACKETS(x)  ((x & 0xf) >> 12)
 193
 194 #define C8SECTPFE_IB_SYS(x)              (C8SECTPFE_CHANNEL_OFFSET(x) + 0x30)
 195 #define C8SECTPFE_SYS_RESET              BIT(1)
 196 #define C8SECTPFE_SYS_ENABLE             BIT(0)
 197
 198 /*
 199  * Ponter record data structure required for each input block
 200  * see Table 82 on page 167 of functional specification.
 201  */
 202
 203 #define DMA_PRDS_MEMBASE        0x0 /* Internal sram base address */
 204 #define DMA_PRDS_MEMTOP         0x4 /* Internal sram top address */
 205
 206 /*
 207  * TS packet size, including tag bytes added by input block,
 208  * rounded up to the next multiple of 8 bytes. The packet size,
 209  * including any tagging bytes and rounded up to the nearest
 210  * multiple of 8 bytes must be less than 255 bytes.
 211  */
 212 #define DMA_PRDS_PKTSIZE        0x8
 213 #define DMA_PRDS_TPENABLE       0xc
 214
 215 #define TP0_OFFSET              0x10
 216 #define DMA_PRDS_BUSBASE_TP(x)  ((0x10*x) + TP0_OFFSET)
 217 #define DMA_PRDS_BUSTOP_TP(x)   ((0x10*x) + TP0_OFFSET + 0x4)
 218 #define DMA_PRDS_BUSWP_TP(x)    ((0x10*x) + TP0_OFFSET + 0x8)
 219 #define DMA_PRDS_BUSRP_TP(x)    ((0x10*x) + TP0_OFFSET + 0xc)
 220
 221 #define DMA_PRDS_SIZE           (0x20)
 222
 223 #define DMA_MEMDMA_OFFSET       0x4000
 224 #define DMA_IMEM_OFFSET         0x0
 225 #define DMA_DMEM_OFFSET         0x4000
 226 #define DMA_CPU                 0x8000
 227 #define DMA_PER_OFFSET          0xb000
 228
 229 #define DMA_MEMDMA_DMEM (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET)
 230 #define DMA_MEMDMA_IMEM (DMA_MEMDMA_OFFSET + DMA_IMEM_OFFSET)
 231
 232 /* XP70 Slim core regs */
 233 #define DMA_CPU_ID      (DMA_MEMDMA_OFFSET + DMA_CPU + 0x0)
 234 #define DMA_CPU_VCR     (DMA_MEMDMA_OFFSET + DMA_CPU + 0x4)
 235 #define DMA_CPU_RUN     (DMA_MEMDMA_OFFSET + DMA_CPU + 0x8)
 236 #define DMA_CPU_CLOCKGATE       (DMA_MEMDMA_OFFSET + DMA_CPU + 0xc)
 237 #define DMA_CPU_PC      (DMA_MEMDMA_OFFSET + DMA_CPU + 0x20)
 238
 239 /* Enable Interrupt for a IB */
 240 #define DMA_PER_TPn_DREQ_MASK   (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd00)
 241 /* Ack interrupt by setting corresponding bit */
 242 #define DMA_PER_TPn_DACK_SET    (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd80)
 243 #define DMA_PER_TPn_DREQ        (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe00)
 244 #define DMA_PER_TPn_DACK        (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe80)
 245 #define DMA_PER_DREQ_MODE       (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf80)
 246 #define DMA_PER_STBUS_SYNC      (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf88)
 247 #define DMA_PER_STBUS_ACCESS    (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf8c)
 248 #define DMA_PER_STBUS_ADDRESS   (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf90)
 249 #define DMA_PER_IDLE_INT        (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfa8)
 250 #define DMA_PER_PRIORITY        (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfac)
 251 #define DMA_PER_MAX_OPCODE      (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb0)
 252 #define DMA_PER_MAX_CHUNK       (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb4)
 253 #define DMA_PER_PAGE_SIZE       (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfbc)
 254 #define DMA_PER_MBOX_STATUS     (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc0)
 255 #define DMA_PER_MBOX_SET        (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc8)
 256 #define DMA_PER_MBOX_CLEAR      (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd0)
 257 #define DMA_PER_MBOX_MASK       (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd8)
 258 #define DMA_PER_INJECT_PKT_SRC  (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe0)
 259 #define DMA_PER_INJECT_PKT_DEST (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe4)
 260 #define DMA_PER_INJECT_PKT_ADDR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe8)
 261 #define DMA_PER_INJECT_PKT      (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfec)
 262 #define DMA_PER_PAT_PTR_INIT    (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff0)
 263 #define DMA_PER_PAT_PTR         (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff4)
 264 #define DMA_PER_SLEEP_MASK      (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff8)
 265 #define DMA_PER_SLEEP_COUNTER   (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xffc)
 266 /* #define DMA_RF_CPUREGn       DMA_RFBASEADDR n=0 to 15) slim regsa */
 267
 268 /* The following are from DMA_DMEM_BaseAddress */
 269 #define DMA_FIRMWARE_VERSION    (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x0)
 270 #define DMA_PTRREC_BASE         (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x4)
 271 #define DMA_PTRREC_INPUT_OFFSET (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x8)
 272 #define DMA_ERRREC_BASE         (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0xc)
 273 #define DMA_ERROR_RECORD(n)     ((n*4) + DMA_ERRREC_BASE + 0x4)
 274 #define DMA_IDLE_REQ            (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x10)
 275 #define IDLEREQ                 BIT(31)
 276
 277 #define DMA_FIRMWARE_CONFIG     (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x14)
 278
 279 /* Regs for PID Filter */
 280
 281 #define PIDF_OFFSET             0x2800
 282 #define PIDF_BASE(n)            ((n*4) + PIDF_OFFSET)
 283 #define PIDF_LEAK_ENABLE        (PIDF_OFFSET + 0x100)
 284 #define PIDF_LEAK_STATUS        (PIDF_OFFSET + 0x108)
 285 #define PIDF_LEAK_COUNT_RESET   (PIDF_OFFSET + 0x110)
 286 #define PIDF_LEAK_COUNTER       (PIDF_OFFSET + 0x114)
 287
 288 #endif /* _C8SECTPFE_CORE_H_ */