drivers/media/rc/mtk-cir.c

   1 /*
   2  * Driver for Mediatek IR Receiver Controller
   3  *
   4  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/reset.h>
  22 #include <media/rc-core.h>
  23
  24 #define MTK_IR_DEV KBUILD_MODNAME
  25
  26 /* Register to enable PWM and IR */
  27 #define MTK_CONFIG_HIGH_REG       0x0c
  28 /* Enable IR pulse width detection */
  29 #define MTK_PWM_EN                BIT(13)
  30 /* Enable IR hardware function */
  31 #define MTK_IR_EN                 BIT(0)
  32
  33 /* Register to setting sample period */
  34 #define MTK_CONFIG_LOW_REG        0x10
  35 /* Field to set sample period */
  36 #define CHK_PERIOD                DIV_ROUND_CLOSEST(MTK_IR_SAMPLE,  \
  37                                                     MTK_IR_CLK_PERIOD)
  38 #define MTK_CHK_PERIOD            (((CHK_PERIOD) << 8) & (GENMASK(20, 8)))
  39 #define MTK_CHK_PERIOD_MASK       (GENMASK(20, 8))
  40
  41 /* Register to clear state of state machine */
  42 #define MTK_IRCLR_REG             0x20
  43 /* Bit to restart IR receiving */
  44 #define MTK_IRCLR                 BIT(0)
  45
  46 /* Register containing pulse width data */
  47 #define MTK_CHKDATA_REG(i)        (0x88 + 4 * (i))
  48 #define MTK_WIDTH_MASK            (GENMASK(7, 0))
  49
  50 /* Register to enable IR interrupt */
  51 #define MTK_IRINT_EN_REG          0xcc
  52 /* Bit to enable interrupt */
  53 #define MTK_IRINT_EN              BIT(0)
  54
  55 /* Register to ack IR interrupt */
  56 #define MTK_IRINT_CLR_REG         0xd0
  57 /* Bit to clear interrupt status */
  58 #define MTK_IRINT_CLR             BIT(0)
  59
  60 /* Maximum count of samples */
  61 #define MTK_MAX_SAMPLES           0xff
  62 /* Indicate the end of IR message */
  63 #define MTK_IR_END(v, p)          ((v) == MTK_MAX_SAMPLES && (p) == 0)
  64 /* Number of registers to record the pulse width */
  65 #define MTK_CHKDATA_SZ            17
  66 /* Source clock frequency */
  67 #define MTK_IR_BASE_CLK           273000000
  68 /* Frequency after IR internal divider */
  69 #define MTK_IR_CLK_FREQ           (MTK_IR_BASE_CLK / 4)
  70 /* Period for MTK_IR_CLK in ns*/
  71 #define MTK_IR_CLK_PERIOD         DIV_ROUND_CLOSEST(1000000000ul,  \
  72                                                     MTK_IR_CLK_FREQ)
  73 /* Sample period in ns */
  74 #define MTK_IR_SAMPLE             (MTK_IR_CLK_PERIOD * 0xc00)
  75
  76 /*
  77  * struct mtk_ir -      This is the main datasructure for holding the state
  78  *                      of the driver
  79  * @dev:                The device pointer
  80  * @rc:                 The rc instrance
  81  * @irq:                The IRQ that we are using
  82  * @base:               The mapped register i/o base
  83  * @clk:                The clock that we are using
  84  */
  85 struct mtk_ir {
  86         struct device   *dev;
  87         struct rc_dev   *rc;
  88         void __iomem    *base;
  89         int             irq;
  90         struct clk      *clk;
  91 };
  92
  93 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
  94 {
  95         u32 tmp;
  96
  97         tmp = __raw_readl(ir->base + reg);
  98         tmp = (tmp & ~mask) | val;
  99         __raw_writel(tmp, ir->base + reg);
 100 }
 101
 102 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
 103 {
 104         __raw_writel(val, ir->base + reg);
 105 }
 106
 107 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
 108 {
 109         return __raw_readl(ir->base + reg);
 110 }
 111
 112 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
 113 {
 114         u32 val;
 115
 116         val = mtk_r32(ir, MTK_IRINT_EN_REG);
 117         mtk_w32(ir, val & ~mask, MTK_IRINT_EN_REG);
 118 }
 119
 120 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
 121 {
 122         u32 val;
 123
 124         val = mtk_r32(ir, MTK_IRINT_EN_REG);
 125         mtk_w32(ir, val | mask, MTK_IRINT_EN_REG);
 126 }
 127
 128 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
 129 {
 130         struct mtk_ir *ir = dev_id;
 131         u8  wid = 0;
 132         u32 i, j, val;
 133         DEFINE_IR_RAW_EVENT(rawir);
 134
 135         /*
 136          * Reset decoder state machine explicitly is required
 137          * because 1) the longest duration for space MTK IR hardware
 138          * could record is not safely long. e.g  12ms if rx resolution
 139          * is 46us by default. There is still the risk to satisfying
 140          * every decoder to reset themselves through long enough
 141          * trailing spaces and 2) the IRQ handler guarantees that
 142          * start of IR message is always contained in and starting
 143          * from register MTK_CHKDATA_REG(0).
 144          */
 145         ir_raw_event_reset(ir->rc);
 146
 147         /* First message must be pulse */
 148         rawir.pulse = false;
 149
 150         /* Handle all pulse and space IR controller captures */
 151         for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
 152                 val = mtk_r32(ir, MTK_CHKDATA_REG(i));
 153                 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
 154
 155                 for (j = 0 ; j < 4 ; j++) {
 156                         wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
 157                         rawir.pulse = !rawir.pulse;
 158                         rawir.duration = wid * (MTK_IR_SAMPLE + 1);
 159                         ir_raw_event_store_with_filter(ir->rc, &rawir);
 160                 }
 161         }
 162
 163         /*
 164          * The maximum number of edges the IR controller can
 165          * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
 166          * is over the limit, the last incomplete IR message would
 167          * be appended trailing space and still would be sent into
 168          * ir-rc-raw to decode. That helps it is possible that it
 169          * has enough information to decode a scancode even if the
 170          * trailing end of the message is missing.
 171          */
 172         if (!MTK_IR_END(wid, rawir.pulse)) {
 173                 rawir.pulse = false;
 174                 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
 175                 ir_raw_event_store_with_filter(ir->rc, &rawir);
 176         }
 177
 178         ir_raw_event_handle(ir->rc);
 179
 180         /*
 181          * Restart controller for the next receive that would
 182          * clear up all CHKDATA registers
 183          */
 184         mtk_w32_mask(ir, 0x1, MTK_IRCLR, MTK_IRCLR_REG);
 185
 186         /* Clear interrupt status */
 187         mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, MTK_IRINT_CLR_REG);
 188
 189         return IRQ_HANDLED;
 190 }
 191
 192 static int mtk_ir_probe(struct platform_device *pdev)
 193 {
 194         struct device *dev = &pdev->dev;
 195         struct device_node *dn = dev->of_node;
 196         struct resource *res;
 197         struct mtk_ir *ir;
 198         u32 val;
 199         int ret = 0;
 200         const char *map_name;
 201
 202         ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
 203         if (!ir)
 204                 return -ENOMEM;
 205
 206         ir->dev = dev;
 207
 208         if (!of_device_is_compatible(dn, "mediatek,mt7623-cir"))
 209                 return -ENODEV;
 210
 211         ir->clk = devm_clk_get(dev, "clk");
 212         if (IS_ERR(ir->clk)) {
 213                 dev_err(dev, "failed to get a ir clock.\n");
 214                 return PTR_ERR(ir->clk);
 215         }
 216
 217         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 218         ir->base = devm_ioremap_resource(dev, res);
 219         if (IS_ERR(ir->base)) {
 220                 dev_err(dev, "failed to map registers\n");
 221                 return PTR_ERR(ir->base);
 222         }
 223
 224         ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
 225         if (!ir->rc) {
 226                 dev_err(dev, "failed to allocate device\n");
 227                 return -ENOMEM;
 228         }
 229
 230         ir->rc->priv = ir;
 231         ir->rc->input_name = MTK_IR_DEV;
 232         ir->rc->input_phys = MTK_IR_DEV "/input0";
 233         ir->rc->input_id.bustype = BUS_HOST;
 234         ir->rc->input_id.vendor = 0x0001;
 235         ir->rc->input_id.product = 0x0001;
 236         ir->rc->input_id.version = 0x0001;
 237         map_name = of_get_property(dn, "linux,rc-map-name", NULL);
 238         ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
 239         ir->rc->dev.parent = dev;
 240         ir->rc->driver_name = MTK_IR_DEV;
 241         ir->rc->allowed_protocols = RC_BIT_ALL;
 242         ir->rc->rx_resolution = MTK_IR_SAMPLE;
 243         ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
 244
 245         ret = devm_rc_register_device(dev, ir->rc);
 246         if (ret) {
 247                 dev_err(dev, "failed to register rc device\n");
 248                 return ret;
 249         }
 250
 251         platform_set_drvdata(pdev, ir);
 252
 253         ir->irq = platform_get_irq(pdev, 0);
 254         if (ir->irq < 0) {
 255                 dev_err(dev, "no irq resource\n");
 256                 return -ENODEV;
 257         }
 258
 259         /*
 260          * Enable interrupt after proper hardware
 261          * setup and IRQ handler registration
 262          */
 263         if (clk_prepare_enable(ir->clk)) {
 264                 dev_err(dev, "try to enable ir_clk failed\n");
 265                 ret = -EINVAL;
 266                 goto exit_clkdisable_clk;
 267         }
 268
 269         mtk_irq_disable(ir, MTK_IRINT_EN);
 270
 271         ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
 272         if (ret) {
 273                 dev_err(dev, "failed request irq\n");
 274                 goto exit_clkdisable_clk;
 275         }
 276
 277         /* Enable IR and PWM */
 278         val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
 279         val |= MTK_PWM_EN | MTK_IR_EN;
 280         mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
 281
 282         /* Setting sample period */
 283         mtk_w32_mask(ir, MTK_CHK_PERIOD, MTK_CHK_PERIOD_MASK,
 284                      MTK_CONFIG_LOW_REG);
 285
 286         mtk_irq_enable(ir, MTK_IRINT_EN);
 287
 288         dev_info(dev, "Initialized MT7623 IR driver, sample period = %luus\n",
 289                  DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
 290
 291         return 0;
 292
 293 exit_clkdisable_clk:
 294         clk_disable_unprepare(ir->clk);
 295
 296         return ret;
 297 }
 298
 299 static int mtk_ir_remove(struct platform_device *pdev)
 300 {
 301         struct mtk_ir *ir = platform_get_drvdata(pdev);
 302
 303         /*
 304          * Avoid contention between remove handler and
 305          * IRQ handler so that disabling IR interrupt and
 306          * waiting for pending IRQ handler to complete
 307          */
 308         mtk_irq_disable(ir, MTK_IRINT_EN);
 309         synchronize_irq(ir->irq);
 310
 311         clk_disable_unprepare(ir->clk);
 312
 313         return 0;
 314 }
 315
 316 static const struct of_device_id mtk_ir_match[] = {
 317         { .compatible = "mediatek,mt7623-cir" },
 318         {},
 319 };
 320 MODULE_DEVICE_TABLE(of, mtk_ir_match);
 321
 322 static struct platform_driver mtk_ir_driver = {
 323         .probe          = mtk_ir_probe,
 324         .remove         = mtk_ir_remove,
 325         .driver = {
 326                 .name = MTK_IR_DEV,
 327                 .of_match_table = mtk_ir_match,
 328         },
 329 };
 330
 331 module_platform_driver(mtk_ir_driver);
 332
 333 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
 334 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
 335 MODULE_LICENSE("GPL");