x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / memory / samsung / exynos-srom.h
blob34660c6a57a94f09f352fc6d735e91c50a359e48
1 /*
2 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Exynos SROMC register definitions
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef __EXYNOS_SROM_H
13 #define __EXYNOS_SROM_H __FILE__
15 #define EXYNOS_SROMREG(x) (x)
17 #define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0)
18 #define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4)
19 #define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8)
20 #define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc)
21 #define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10)
22 #define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14)
23 #define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18)
25 /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
27 #define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0
28 #define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1
29 #define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2
30 #define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3
32 #define EXYNOS_SROM_BW__CS_MASK 0xf
34 #define EXYNOS_SROM_BW__NCS0__SHIFT 0
35 #define EXYNOS_SROM_BW__NCS1__SHIFT 4
36 #define EXYNOS_SROM_BW__NCS2__SHIFT 8
37 #define EXYNOS_SROM_BW__NCS3__SHIFT 12
38 #define EXYNOS_SROM_BW__NCS4__SHIFT 16
39 #define EXYNOS_SROM_BW__NCS5__SHIFT 20
41 /* applies to same to BCS0 - BCS3 */
43 #define EXYNOS_SROM_BCX__PMC__SHIFT 0
44 #define EXYNOS_SROM_BCX__TACP__SHIFT 4
45 #define EXYNOS_SROM_BCX__TCAH__SHIFT 8
46 #define EXYNOS_SROM_BCX__TCOH__SHIFT 12
47 #define EXYNOS_SROM_BCX__TACC__SHIFT 16
48 #define EXYNOS_SROM_BCX__TCOS__SHIFT 24
49 #define EXYNOS_SROM_BCX__TACS__SHIFT 28
51 #endif /* __EXYNOS_SROM_H */