x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pltfm.h
blob957839d0fe376611443ed29d34c4d0c56ec5981a
1 /*
2 * Copyright 2010 MontaVista Software, LLC.
4 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
12 #define _DRIVERS_MMC_SDHCI_PLTFM_H
14 #include <linux/clk.h>
15 #include <linux/platform_device.h>
16 #include "sdhci.h"
18 struct sdhci_pltfm_data {
19 const struct sdhci_ops *ops;
20 unsigned int quirks;
21 unsigned int quirks2;
24 struct sdhci_pltfm_host {
25 struct clk *clk;
27 /* migrate from sdhci_of_host */
28 unsigned int clock;
29 u16 xfer_mode_shadow;
31 unsigned long private[0] ____cacheline_aligned;
34 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
36 * These accessors are designed for big endian hosts doing I/O to
37 * little endian controllers incorporating a 32-bit hardware byte swapper.
39 static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
41 return in_be32(host->ioaddr + reg);
44 static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
46 return in_be16(host->ioaddr + (reg ^ 0x2));
49 static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
51 return in_8(host->ioaddr + (reg ^ 0x3));
54 static inline void sdhci_be32bs_writel(struct sdhci_host *host,
55 u32 val, int reg)
57 out_be32(host->ioaddr + reg, val);
60 static inline void sdhci_be32bs_writew(struct sdhci_host *host,
61 u16 val, int reg)
63 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
64 int base = reg & ~0x3;
65 int shift = (reg & 0x2) * 8;
67 switch (reg) {
68 case SDHCI_TRANSFER_MODE:
70 * Postpone this write, we must do it together with a
71 * command write that is down below.
73 pltfm_host->xfer_mode_shadow = val;
74 return;
75 case SDHCI_COMMAND:
76 sdhci_be32bs_writel(host,
77 val << 16 | pltfm_host->xfer_mode_shadow,
78 SDHCI_TRANSFER_MODE);
79 return;
81 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
84 static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
86 int base = reg & ~0x3;
87 int shift = (reg & 0x3) * 8;
89 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
91 #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
93 extern void sdhci_get_of_property(struct platform_device *pdev);
95 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
96 const struct sdhci_pltfm_data *pdata,
97 size_t priv_size);
98 extern void sdhci_pltfm_free(struct platform_device *pdev);
100 extern int sdhci_pltfm_register(struct platform_device *pdev,
101 const struct sdhci_pltfm_data *pdata,
102 size_t priv_size);
103 extern int sdhci_pltfm_unregister(struct platform_device *pdev);
105 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
107 static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
109 return host->private;
112 extern const struct dev_pm_ops sdhci_pltfm_pmops;
114 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */