drivers/mtd/maps/physmap_of_gemini.c

   1 /*
   2  * Cortina Systems Gemini OF physmap add-on
   3  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   4  *
   5  * This SoC has an elaborate flash control register, so we need to
   6  * detect and set it up when booting on this platform.
   7  */
   8 #include <linux/export.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/mtd/map.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/regmap.h>
  14 #include <linux/bitops.h>
  15 #include "physmap_of_gemini.h"
  16
  17 /*
  18  * The Flash-relevant parts of the global status register
  19  * These would also be relevant for a NAND driver.
  20  */
  21 #define GLOBAL_STATUS                   0x04
  22 #define FLASH_TYPE_MASK                 (0x3 << 24)
  23 #define FLASH_TYPE_NAND_2K              (0x3 << 24)
  24 #define FLASH_TYPE_NAND_512             (0x2 << 24)
  25 #define FLASH_TYPE_PARALLEL             (0x1 << 24)
  26 #define FLASH_TYPE_SERIAL               (0x0 << 24)
  27 /* if parallel */
  28 #define FLASH_WIDTH_16BIT               (1 << 23)       /* else 8 bit */
  29 /* if serial */
  30 #define FLASH_ATMEL                     (1 << 23)       /* else STM */
  31
  32 #define FLASH_SIZE_MASK                 (0x3 << 21)
  33 #define NAND_256M                       (0x3 << 21)     /* and more */
  34 #define NAND_128M                       (0x2 << 21)
  35 #define NAND_64M                        (0x1 << 21)
  36 #define NAND_32M                        (0x0 << 21)
  37 #define ATMEL_16M                       (0x3 << 21)     /* and more */
  38 #define ATMEL_8M                        (0x2 << 21)
  39 #define ATMEL_4M_2M                     (0x1 << 21)
  40 #define ATMEL_1M                        (0x0 << 21)     /* and less */
  41 #define STM_32M                         (1 << 22)       /* and more */
  42 #define STM_16M                         (0 << 22)       /* and less */
  43
  44 #define FLASH_PARALLEL_HIGH_PIN_CNT     (1 << 20)       /* else low pin cnt */
  45
  46 /* Miscellaneous Control Register */
  47 #define GLOBAL_MISC_CTRL                0x30
  48 #define FLASH_PADS_MASK                 0x07
  49 #define NAND_PADS_DISABLE               BIT(2)
  50 #define PFLASH_PADS_DISABLE             BIT(1)
  51 #define SFLASH_PADS_DISABLE             BIT(0)
  52
  53 static const struct of_device_id syscon_match[] = {
  54         { .compatible = "cortina,gemini-syscon" },
  55         { },
  56 };
  57
  58 int of_flash_probe_gemini(struct platform_device *pdev,
  59                           struct device_node *np,
  60                           struct map_info *map)
  61 {
  62         static struct regmap *rmap;
  63         struct device *dev = &pdev->dev;
  64         u32 val;
  65         int ret;
  66
  67         /* Multiplatform guard */
  68         if (!of_device_is_compatible(np, "cortina,gemini-flash"))
  69                 return 0;
  70
  71         rmap = syscon_regmap_lookup_by_phandle(np, "syscon");
  72         if (IS_ERR(rmap)) {
  73                 dev_err(dev, "no syscon\n");
  74                 return PTR_ERR(rmap);
  75         }
  76
  77         ret = regmap_read(rmap, GLOBAL_STATUS, &val);
  78         if (ret) {
  79                 dev_err(dev, "failed to read global status register\n");
  80                 return -ENODEV;
  81         }
  82         dev_dbg(dev, "global status reg: %08x\n", val);
  83
  84         /*
  85          * It would be contradictory if a physmap flash was NOT parallel.
  86          */
  87         if ((val & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL) {
  88                 dev_err(dev, "flash is not parallel\n");
  89                 return -ENODEV;
  90         }
  91
  92         /*
  93          * Complain if DT data and hardware definition is different.
  94          */
  95         if (val & FLASH_WIDTH_16BIT) {
  96                 if (map->bankwidth != 2)
  97                         dev_warn(dev, "flash hardware say flash is 16 bit wide but DT says it is %d bits wide\n",
  98                                  map->bankwidth * 8);
  99         } else {
 100                 if (map->bankwidth != 1)
 101                         dev_warn(dev, "flash hardware say flash is 8 bit wide but DT says it is %d bits wide\n",
 102                                  map->bankwidth * 8);
 103         }
 104
 105         /* Activate parallel (NOR flash) mode */
 106         ret = regmap_update_bits(rmap, GLOBAL_MISC_CTRL,
 107                                  FLASH_PADS_MASK,
 108                                  SFLASH_PADS_DISABLE | NAND_PADS_DISABLE);
 109         if (ret) {
 110                 dev_err(dev, "unable to set up physmap pads\n");
 111                 return -ENODEV;
 112         }
 113
 114         dev_info(&pdev->dev, "initialized Gemini-specific physmap control\n");
 115
 116         return 0;
 117 }