drivers/mtd/nand/mtk_ecc.c

   1 /*
   2  * MTK ECC controller driver.
   3  * Copyright (C) 2016  MediaTek Inc.
   4  * Authors:     Xiaolei Li              <xiaolei.li@mediatek.com>
   5  *              Jorge Ramirez-Ortiz     <jorge.ramirez-ortiz@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/module.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/of.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/mutex.h>
  26
  27 #include "mtk_ecc.h"
  28
  29 #define ECC_IDLE_MASK           BIT(0)
  30 #define ECC_IRQ_EN              BIT(0)
  31 #define ECC_OP_ENABLE           (1)
  32 #define ECC_OP_DISABLE          (0)
  33
  34 #define ECC_ENCCON              (0x00)
  35 #define ECC_ENCCNFG             (0x04)
  36 #define         ECC_CNFG_4BIT           (0)
  37 #define         ECC_CNFG_6BIT           (1)
  38 #define         ECC_CNFG_8BIT           (2)
  39 #define         ECC_CNFG_10BIT          (3)
  40 #define         ECC_CNFG_12BIT          (4)
  41 #define         ECC_CNFG_14BIT          (5)
  42 #define         ECC_CNFG_16BIT          (6)
  43 #define         ECC_CNFG_18BIT          (7)
  44 #define         ECC_CNFG_20BIT          (8)
  45 #define         ECC_CNFG_22BIT          (9)
  46 #define         ECC_CNFG_24BIT          (0xa)
  47 #define         ECC_CNFG_28BIT          (0xb)
  48 #define         ECC_CNFG_32BIT          (0xc)
  49 #define         ECC_CNFG_36BIT          (0xd)
  50 #define         ECC_CNFG_40BIT          (0xe)
  51 #define         ECC_CNFG_44BIT          (0xf)
  52 #define         ECC_CNFG_48BIT          (0x10)
  53 #define         ECC_CNFG_52BIT          (0x11)
  54 #define         ECC_CNFG_56BIT          (0x12)
  55 #define         ECC_CNFG_60BIT          (0x13)
  56 #define         ECC_MODE_SHIFT          (5)
  57 #define         ECC_MS_SHIFT            (16)
  58 #define ECC_ENCDIADDR           (0x08)
  59 #define ECC_ENCIDLE             (0x0C)
  60 #define ECC_ENCPAR(x)           (0x10 + (x) * sizeof(u32))
  61 #define ECC_ENCIRQ_EN           (0x80)
  62 #define ECC_ENCIRQ_STA          (0x84)
  63 #define ECC_DECCON              (0x100)
  64 #define ECC_DECCNFG             (0x104)
  65 #define         DEC_EMPTY_EN            BIT(31)
  66 #define         DEC_CNFG_CORRECT        (0x3 << 12)
  67 #define ECC_DECIDLE             (0x10C)
  68 #define ECC_DECENUM0            (0x114)
  69 #define         ERR_MASK                (0x3f)
  70 #define ECC_DECDONE             (0x124)
  71 #define ECC_DECIRQ_EN           (0x200)
  72 #define ECC_DECIRQ_STA          (0x204)
  73
  74 #define ECC_TIMEOUT             (500000)
  75
  76 #define ECC_IDLE_REG(op)        ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
  77 #define ECC_CTL_REG(op)         ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
  78 #define ECC_IRQ_REG(op)         ((op) == ECC_ENCODE ? \
  79                                         ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
  80
  81 struct mtk_ecc {
  82         struct device *dev;
  83         void __iomem *regs;
  84         struct clk *clk;
  85
  86         struct completion done;
  87         struct mutex lock;
  88         u32 sectors;
  89
  90         u8 eccdata[112];
  91 };
  92
  93 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
  94                                      enum mtk_ecc_operation op)
  95 {
  96         struct device *dev = ecc->dev;
  97         u32 val;
  98         int ret;
  99
 100         ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
 101                                         val & ECC_IDLE_MASK,
 102                                         10, ECC_TIMEOUT);
 103         if (ret)
 104                 dev_warn(dev, "%s NOT idle\n",
 105                          op == ECC_ENCODE ? "encoder" : "decoder");
 106 }
 107
 108 static irqreturn_t mtk_ecc_irq(int irq, void *id)
 109 {
 110         struct mtk_ecc *ecc = id;
 111         enum mtk_ecc_operation op;
 112         u32 dec, enc;
 113
 114         dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
 115         if (dec) {
 116                 op = ECC_DECODE;
 117                 dec = readw(ecc->regs + ECC_DECDONE);
 118                 if (dec & ecc->sectors) {
 119                         ecc->sectors = 0;
 120                         complete(&ecc->done);
 121                 } else {
 122                         return IRQ_HANDLED;
 123                 }
 124         } else {
 125                 enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
 126                 if (enc) {
 127                         op = ECC_ENCODE;
 128                         complete(&ecc->done);
 129                 } else {
 130                         return IRQ_NONE;
 131                 }
 132         }
 133
 134         writel(0, ecc->regs + ECC_IRQ_REG(op));
 135
 136         return IRQ_HANDLED;
 137 }
 138
 139 static void mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
 140 {
 141         u32 ecc_bit = ECC_CNFG_4BIT, dec_sz, enc_sz;
 142         u32 reg;
 143
 144         switch (config->strength) {
 145         case 4:
 146                 ecc_bit = ECC_CNFG_4BIT;
 147                 break;
 148         case 6:
 149                 ecc_bit = ECC_CNFG_6BIT;
 150                 break;
 151         case 8:
 152                 ecc_bit = ECC_CNFG_8BIT;
 153                 break;
 154         case 10:
 155                 ecc_bit = ECC_CNFG_10BIT;
 156                 break;
 157         case 12:
 158                 ecc_bit = ECC_CNFG_12BIT;
 159                 break;
 160         case 14:
 161                 ecc_bit = ECC_CNFG_14BIT;
 162                 break;
 163         case 16:
 164                 ecc_bit = ECC_CNFG_16BIT;
 165                 break;
 166         case 18:
 167                 ecc_bit = ECC_CNFG_18BIT;
 168                 break;
 169         case 20:
 170                 ecc_bit = ECC_CNFG_20BIT;
 171                 break;
 172         case 22:
 173                 ecc_bit = ECC_CNFG_22BIT;
 174                 break;
 175         case 24:
 176                 ecc_bit = ECC_CNFG_24BIT;
 177                 break;
 178         case 28:
 179                 ecc_bit = ECC_CNFG_28BIT;
 180                 break;
 181         case 32:
 182                 ecc_bit = ECC_CNFG_32BIT;
 183                 break;
 184         case 36:
 185                 ecc_bit = ECC_CNFG_36BIT;
 186                 break;
 187         case 40:
 188                 ecc_bit = ECC_CNFG_40BIT;
 189                 break;
 190         case 44:
 191                 ecc_bit = ECC_CNFG_44BIT;
 192                 break;
 193         case 48:
 194                 ecc_bit = ECC_CNFG_48BIT;
 195                 break;
 196         case 52:
 197                 ecc_bit = ECC_CNFG_52BIT;
 198                 break;
 199         case 56:
 200                 ecc_bit = ECC_CNFG_56BIT;
 201                 break;
 202         case 60:
 203                 ecc_bit = ECC_CNFG_60BIT;
 204                 break;
 205         default:
 206                 dev_err(ecc->dev, "invalid strength %d, default to 4 bits\n",
 207                         config->strength);
 208         }
 209
 210         if (config->op == ECC_ENCODE) {
 211                 /* configure ECC encoder (in bits) */
 212                 enc_sz = config->len << 3;
 213
 214                 reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
 215                 reg |= (enc_sz << ECC_MS_SHIFT);
 216                 writel(reg, ecc->regs + ECC_ENCCNFG);
 217
 218                 if (config->mode != ECC_NFI_MODE)
 219                         writel(lower_32_bits(config->addr),
 220                                ecc->regs + ECC_ENCDIADDR);
 221
 222         } else {
 223                 /* configure ECC decoder (in bits) */
 224                 dec_sz = (config->len << 3) +
 225                                         config->strength * ECC_PARITY_BITS;
 226
 227                 reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
 228                 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
 229                 reg |= DEC_EMPTY_EN;
 230                 writel(reg, ecc->regs + ECC_DECCNFG);
 231
 232                 if (config->sectors)
 233                         ecc->sectors = 1 << (config->sectors - 1);
 234         }
 235 }
 236
 237 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
 238                        int sectors)
 239 {
 240         u32 offset, i, err;
 241         u32 bitflips = 0;
 242
 243         stats->corrected = 0;
 244         stats->failed = 0;
 245
 246         for (i = 0; i < sectors; i++) {
 247                 offset = (i >> 2) << 2;
 248                 err = readl(ecc->regs + ECC_DECENUM0 + offset);
 249                 err = err >> ((i % 4) * 8);
 250                 err &= ERR_MASK;
 251                 if (err == ERR_MASK) {
 252                         /* uncorrectable errors */
 253                         stats->failed++;
 254                         continue;
 255                 }
 256
 257                 stats->corrected += err;
 258                 bitflips = max_t(u32, bitflips, err);
 259         }
 260
 261         stats->bitflips = bitflips;
 262 }
 263 EXPORT_SYMBOL(mtk_ecc_get_stats);
 264
 265 void mtk_ecc_release(struct mtk_ecc *ecc)
 266 {
 267         clk_disable_unprepare(ecc->clk);
 268         put_device(ecc->dev);
 269 }
 270 EXPORT_SYMBOL(mtk_ecc_release);
 271
 272 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
 273 {
 274         mtk_ecc_wait_idle(ecc, ECC_ENCODE);
 275         writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
 276
 277         mtk_ecc_wait_idle(ecc, ECC_DECODE);
 278         writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
 279 }
 280
 281 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
 282 {
 283         struct platform_device *pdev;
 284         struct mtk_ecc *ecc;
 285
 286         pdev = of_find_device_by_node(np);
 287         if (!pdev || !platform_get_drvdata(pdev))
 288                 return ERR_PTR(-EPROBE_DEFER);
 289
 290         get_device(&pdev->dev);
 291         ecc = platform_get_drvdata(pdev);
 292         clk_prepare_enable(ecc->clk);
 293         mtk_ecc_hw_init(ecc);
 294
 295         return ecc;
 296 }
 297
 298 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
 299 {
 300         struct mtk_ecc *ecc = NULL;
 301         struct device_node *np;
 302
 303         np = of_parse_phandle(of_node, "ecc-engine", 0);
 304         if (np) {
 305                 ecc = mtk_ecc_get(np);
 306                 of_node_put(np);
 307         }
 308
 309         return ecc;
 310 }
 311 EXPORT_SYMBOL(of_mtk_ecc_get);
 312
 313 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
 314 {
 315         enum mtk_ecc_operation op = config->op;
 316         int ret;
 317
 318         ret = mutex_lock_interruptible(&ecc->lock);
 319         if (ret) {
 320                 dev_err(ecc->dev, "interrupted when attempting to lock\n");
 321                 return ret;
 322         }
 323
 324         mtk_ecc_wait_idle(ecc, op);
 325         mtk_ecc_config(ecc, config);
 326         writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
 327
 328         init_completion(&ecc->done);
 329         writew(ECC_IRQ_EN, ecc->regs + ECC_IRQ_REG(op));
 330
 331         return 0;
 332 }
 333 EXPORT_SYMBOL(mtk_ecc_enable);
 334
 335 void mtk_ecc_disable(struct mtk_ecc *ecc)
 336 {
 337         enum mtk_ecc_operation op = ECC_ENCODE;
 338
 339         /* find out the running operation */
 340         if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
 341                 op = ECC_DECODE;
 342
 343         /* disable it */
 344         mtk_ecc_wait_idle(ecc, op);
 345         writew(0, ecc->regs + ECC_IRQ_REG(op));
 346         writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
 347
 348         mutex_unlock(&ecc->lock);
 349 }
 350 EXPORT_SYMBOL(mtk_ecc_disable);
 351
 352 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
 353 {
 354         int ret;
 355
 356         ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
 357         if (!ret) {
 358                 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
 359                         (op == ECC_ENCODE) ? "encoder" : "decoder");
 360                 return -ETIMEDOUT;
 361         }
 362
 363         return 0;
 364 }
 365 EXPORT_SYMBOL(mtk_ecc_wait_done);
 366
 367 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
 368                    u8 *data, u32 bytes)
 369 {
 370         dma_addr_t addr;
 371         u32 len;
 372         int ret;
 373
 374         addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
 375         ret = dma_mapping_error(ecc->dev, addr);
 376         if (ret) {
 377                 dev_err(ecc->dev, "dma mapping error\n");
 378                 return -EINVAL;
 379         }
 380
 381         config->op = ECC_ENCODE;
 382         config->addr = addr;
 383         ret = mtk_ecc_enable(ecc, config);
 384         if (ret) {
 385                 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
 386                 return ret;
 387         }
 388
 389         ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
 390         if (ret)
 391                 goto timeout;
 392
 393         mtk_ecc_wait_idle(ecc, ECC_ENCODE);
 394
 395         /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
 396         len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
 397
 398         /* write the parity bytes generated by the ECC back to temp buffer */
 399         __ioread32_copy(ecc->eccdata, ecc->regs + ECC_ENCPAR(0), round_up(len, 4));
 400
 401         /* copy into possibly unaligned OOB region with actual length */
 402         memcpy(data + bytes, ecc->eccdata, len);
 403 timeout:
 404
 405         dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
 406         mtk_ecc_disable(ecc);
 407
 408         return ret;
 409 }
 410 EXPORT_SYMBOL(mtk_ecc_encode);
 411
 412 void mtk_ecc_adjust_strength(u32 *p)
 413 {
 414         u32 ecc[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
 415                         40, 44, 48, 52, 56, 60};
 416         int i;
 417
 418         for (i = 0; i < ARRAY_SIZE(ecc); i++) {
 419                 if (*p <= ecc[i]) {
 420                         if (!i)
 421                                 *p = ecc[i];
 422                         else if (*p != ecc[i])
 423                                 *p = ecc[i - 1];
 424                         return;
 425                 }
 426         }
 427
 428         *p = ecc[ARRAY_SIZE(ecc) - 1];
 429 }
 430 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
 431
 432 static int mtk_ecc_probe(struct platform_device *pdev)
 433 {
 434         struct device *dev = &pdev->dev;
 435         struct mtk_ecc *ecc;
 436         struct resource *res;
 437         int irq, ret;
 438
 439         ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
 440         if (!ecc)
 441                 return -ENOMEM;
 442
 443         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 444         ecc->regs = devm_ioremap_resource(dev, res);
 445         if (IS_ERR(ecc->regs)) {
 446                 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
 447                 return PTR_ERR(ecc->regs);
 448         }
 449
 450         ecc->clk = devm_clk_get(dev, NULL);
 451         if (IS_ERR(ecc->clk)) {
 452                 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
 453                 return PTR_ERR(ecc->clk);
 454         }
 455
 456         irq = platform_get_irq(pdev, 0);
 457         if (irq < 0) {
 458                 dev_err(dev, "failed to get irq\n");
 459                 return -EINVAL;
 460         }
 461
 462         ret = dma_set_mask(dev, DMA_BIT_MASK(32));
 463         if (ret) {
 464                 dev_err(dev, "failed to set DMA mask\n");
 465                 return ret;
 466         }
 467
 468         ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
 469         if (ret) {
 470                 dev_err(dev, "failed to request irq\n");
 471                 return -EINVAL;
 472         }
 473
 474         ecc->dev = dev;
 475         mutex_init(&ecc->lock);
 476         platform_set_drvdata(pdev, ecc);
 477         dev_info(dev, "probed\n");
 478
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_PM_SLEEP
 483 static int mtk_ecc_suspend(struct device *dev)
 484 {
 485         struct mtk_ecc *ecc = dev_get_drvdata(dev);
 486
 487         clk_disable_unprepare(ecc->clk);
 488
 489         return 0;
 490 }
 491
 492 static int mtk_ecc_resume(struct device *dev)
 493 {
 494         struct mtk_ecc *ecc = dev_get_drvdata(dev);
 495         int ret;
 496
 497         ret = clk_prepare_enable(ecc->clk);
 498         if (ret) {
 499                 dev_err(dev, "failed to enable clk\n");
 500                 return ret;
 501         }
 502
 503         mtk_ecc_hw_init(ecc);
 504
 505         return 0;
 506 }
 507
 508 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
 509 #endif
 510
 511 static const struct of_device_id mtk_ecc_dt_match[] = {
 512         { .compatible = "mediatek,mt2701-ecc" },
 513         {},
 514 };
 515
 516 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
 517
 518 static struct platform_driver mtk_ecc_driver = {
 519         .probe  = mtk_ecc_probe,
 520         .driver = {
 521                 .name  = "mtk-ecc",
 522                 .of_match_table = of_match_ptr(mtk_ecc_dt_match),
 523 #ifdef CONFIG_PM_SLEEP
 524                 .pm = &mtk_ecc_pm_ops,
 525 #endif
 526         },
 527 };
 528
 529 module_platform_driver(mtk_ecc_driver);
 530
 531 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
 532 MODULE_DESCRIPTION("MTK Nand ECC Driver");
 533 MODULE_LICENSE("GPL");