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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bgmac.c
blobfd66fca00e0177aa6f2ebf8e01d59420cb14353e
1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/bcma/bcma.h>
13 #include <linux/etherdevice.h>
14 #include <linux/bcm47xx_nvram.h>
15 #include <linux/phy.h>
16 #include <linux/phy_fixed.h>
17 #include "bgmac.h"
18
19 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
20 u32 value, int timeout)
21 {
22 u32 val;
23 int i;
24
25 for (i = 0; i < timeout / 10; i++) {
26 val = bgmac_read(bgmac, reg);
27 if ((val & mask) == value)
28 return true;
29 udelay(10);
30 }
31 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
32 return false;
33 }
34
35 /**************************************************
36 * DMA
37 **************************************************/
38
39 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
40 {
41 u32 val;
42 int i;
43
44 if (!ring->mmio_base)
45 return;
46
47 /* Suspend DMA TX ring first.
48 * bgmac_wait_value doesn't support waiting for any of few values, so
49 * implement whole loop here.
50 */
51 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
52 BGMAC_DMA_TX_SUSPEND);
53 for (i = 0; i < 10000 / 10; i++) {
54 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
55 val &= BGMAC_DMA_TX_STAT;
56 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
57 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
58 val == BGMAC_DMA_TX_STAT_STOPPED) {
59 i = 0;
60 break;
61 }
62 udelay(10);
63 }
64 if (i)
65 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
66 ring->mmio_base, val);
67
68 /* Remove SUSPEND bit */
69 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
70 if (!bgmac_wait_value(bgmac,
71 ring->mmio_base + BGMAC_DMA_TX_STATUS,
72 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
73 10000)) {
74 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
75 ring->mmio_base);
76 udelay(300);
77 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
78 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
79 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
80 ring->mmio_base);
81 }
82 }
83
84 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
85 struct bgmac_dma_ring *ring)
86 {
87 u32 ctl;
88
89 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
90 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
91 ctl &= ~BGMAC_DMA_TX_BL_MASK;
92 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
93
94 ctl &= ~BGMAC_DMA_TX_MR_MASK;
95 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
96
97 ctl &= ~BGMAC_DMA_TX_PC_MASK;
98 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
99
100 ctl &= ~BGMAC_DMA_TX_PT_MASK;
101 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
102 }
103 ctl |= BGMAC_DMA_TX_ENABLE;
104 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
105 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
106 }
107
108 static void
109 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
110 int i, int len, u32 ctl0)
111 {
112 struct bgmac_slot_info *slot;
113 struct bgmac_dma_desc *dma_desc;
114 u32 ctl1;
115
116 if (i == BGMAC_TX_RING_SLOTS - 1)
117 ctl0 |= BGMAC_DESC_CTL0_EOT;
118
119 ctl1 = len & BGMAC_DESC_CTL1_LEN;
120
121 slot = &ring->slots[i];
122 dma_desc = &ring->cpu_base[i];
123 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
124 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
125 dma_desc->ctl0 = cpu_to_le32(ctl0);
126 dma_desc->ctl1 = cpu_to_le32(ctl1);
127 }
128
129 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
130 struct bgmac_dma_ring *ring,
131 struct sk_buff *skb)
132 {
133 struct device *dma_dev = bgmac->dma_dev;
134 struct net_device *net_dev = bgmac->net_dev;
135 int index = ring->end % BGMAC_TX_RING_SLOTS;
136 struct bgmac_slot_info *slot = &ring->slots[index];
137 int nr_frags;
138 u32 flags;
139 int i;
140
141 if (skb->len > BGMAC_DESC_CTL1_LEN) {
142 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
143 goto err_drop;
144 }
145
146 if (skb->ip_summed == CHECKSUM_PARTIAL)
147 skb_checksum_help(skb);
148
149 nr_frags = skb_shinfo(skb)->nr_frags;
150
151 /* ring->end - ring->start will return the number of valid slots,
152 * even when ring->end overflows
153 */
154 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
155 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
156 netif_stop_queue(net_dev);
157 return NETDEV_TX_BUSY;
158 }
159
160 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
161 DMA_TO_DEVICE);
162 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
163 goto err_dma_head;
164
165 flags = BGMAC_DESC_CTL0_SOF;
166 if (!nr_frags)
167 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
168
169 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
170 flags = 0;
171
172 for (i = 0; i < nr_frags; i++) {
173 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
174 int len = skb_frag_size(frag);
175
176 index = (index + 1) % BGMAC_TX_RING_SLOTS;
177 slot = &ring->slots[index];
178 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
179 len, DMA_TO_DEVICE);
180 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
181 goto err_dma;
182
183 if (i == nr_frags - 1)
184 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
185
186 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
187 }
188
189 slot->skb = skb;
190 ring->end += nr_frags + 1;
191 netdev_sent_queue(net_dev, skb->len);
192
193 wmb();
194
195 /* Increase ring->end to point empty slot. We tell hardware the first
196 * slot it should *not* read.
197 */
198 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
199 ring->index_base +
200 (ring->end % BGMAC_TX_RING_SLOTS) *
201 sizeof(struct bgmac_dma_desc));
202
203 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
204 netif_stop_queue(net_dev);
205
206 return NETDEV_TX_OK;
207
208 err_dma:
209 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
210 DMA_TO_DEVICE);
211
212 while (i-- > 0) {
213 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
214 struct bgmac_slot_info *slot = &ring->slots[index];
215 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
216 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
217
218 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
219 }
220
221 err_dma_head:
222 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
223 ring->mmio_base);
224
225 err_drop:
226 dev_kfree_skb(skb);
227 net_dev->stats.tx_dropped++;
228 net_dev->stats.tx_errors++;
229 return NETDEV_TX_OK;
230 }
231
232 /* Free transmitted packets */
233 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
234 {
235 struct device *dma_dev = bgmac->dma_dev;
236 int empty_slot;
237 bool freed = false;
238 unsigned bytes_compl = 0, pkts_compl = 0;
239
240 /* The last slot that hardware didn't consume yet */
241 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
242 empty_slot &= BGMAC_DMA_TX_STATDPTR;
243 empty_slot -= ring->index_base;
244 empty_slot &= BGMAC_DMA_TX_STATDPTR;
245 empty_slot /= sizeof(struct bgmac_dma_desc);
246
247 while (ring->start != ring->end) {
248 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
249 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
250 u32 ctl0, ctl1;
251 int len;
252
253 if (slot_idx == empty_slot)
254 break;
255
256 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
257 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
258 len = ctl1 & BGMAC_DESC_CTL1_LEN;
259 if (ctl0 & BGMAC_DESC_CTL0_SOF)
260 /* Unmap no longer used buffer */
261 dma_unmap_single(dma_dev, slot->dma_addr, len,
262 DMA_TO_DEVICE);
263 else
264 dma_unmap_page(dma_dev, slot->dma_addr, len,
265 DMA_TO_DEVICE);
266
267 if (slot->skb) {
268 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
269 bgmac->net_dev->stats.tx_packets++;
270 bytes_compl += slot->skb->len;
271 pkts_compl++;
272
273 /* Free memory! :) */
274 dev_kfree_skb(slot->skb);
275 slot->skb = NULL;
276 }
277
278 slot->dma_addr = 0;
279 ring->start++;
280 freed = true;
281 }
282
283 if (!pkts_compl)
284 return;
285
286 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
287
288 if (netif_queue_stopped(bgmac->net_dev))
289 netif_wake_queue(bgmac->net_dev);
290 }
291
292 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
293 {
294 if (!ring->mmio_base)
295 return;
296
297 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
298 if (!bgmac_wait_value(bgmac,
299 ring->mmio_base + BGMAC_DMA_RX_STATUS,
300 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
301 10000))
302 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
303 ring->mmio_base);
304 }
305
306 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
307 struct bgmac_dma_ring *ring)
308 {
309 u32 ctl;
310
311 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
312
313 /* preserve ONLY bits 16-17 from current hardware value */
314 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
315
316 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
317 ctl &= ~BGMAC_DMA_RX_BL_MASK;
318 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
319
320 ctl &= ~BGMAC_DMA_RX_PC_MASK;
321 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
322
323 ctl &= ~BGMAC_DMA_RX_PT_MASK;
324 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
325 }
326 ctl |= BGMAC_DMA_RX_ENABLE;
327 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
328 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
329 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
330 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
331 }
332
333 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
334 struct bgmac_slot_info *slot)
335 {
336 struct device *dma_dev = bgmac->dma_dev;
337 dma_addr_t dma_addr;
338 struct bgmac_rx_header *rx;
339 void *buf;
340
341 /* Alloc skb */
342 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
343 if (!buf)
344 return -ENOMEM;
345
346 /* Poison - if everything goes fine, hardware will overwrite it */
347 rx = buf + BGMAC_RX_BUF_OFFSET;
348 rx->len = cpu_to_le16(0xdead);
349 rx->flags = cpu_to_le16(0xbeef);
350
351 /* Map skb for the DMA */
352 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
353 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
354 if (dma_mapping_error(dma_dev, dma_addr)) {
355 netdev_err(bgmac->net_dev, "DMA mapping error\n");
356 put_page(virt_to_head_page(buf));
357 return -ENOMEM;
358 }
359
360 /* Update the slot */
361 slot->buf = buf;
362 slot->dma_addr = dma_addr;
363
364 return 0;
365 }
366
367 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
368 struct bgmac_dma_ring *ring)
369 {
370 dma_wmb();
371
372 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
373 ring->index_base +
374 ring->end * sizeof(struct bgmac_dma_desc));
375 }
376
377 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
378 struct bgmac_dma_ring *ring, int desc_idx)
379 {
380 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
381 u32 ctl0 = 0, ctl1 = 0;
382
383 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
384 ctl0 |= BGMAC_DESC_CTL0_EOT;
385 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
386 /* Is there any BGMAC device that requires extension? */
387 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
388 * B43_DMA64_DCTL1_ADDREXT_MASK;
389 */
390
391 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
392 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
393 dma_desc->ctl0 = cpu_to_le32(ctl0);
394 dma_desc->ctl1 = cpu_to_le32(ctl1);
395
396 ring->end = desc_idx;
397 }
398
399 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
400 struct bgmac_slot_info *slot)
401 {
402 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
403
404 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
405 DMA_FROM_DEVICE);
406 rx->len = cpu_to_le16(0xdead);
407 rx->flags = cpu_to_le16(0xbeef);
408 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
409 DMA_FROM_DEVICE);
410 }
411
412 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
413 int weight)
414 {
415 u32 end_slot;
416 int handled = 0;
417
418 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
419 end_slot &= BGMAC_DMA_RX_STATDPTR;
420 end_slot -= ring->index_base;
421 end_slot &= BGMAC_DMA_RX_STATDPTR;
422 end_slot /= sizeof(struct bgmac_dma_desc);
423
424 while (ring->start != end_slot) {
425 struct device *dma_dev = bgmac->dma_dev;
426 struct bgmac_slot_info *slot = &ring->slots[ring->start];
427 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
428 struct sk_buff *skb;
429 void *buf = slot->buf;
430 dma_addr_t dma_addr = slot->dma_addr;
431 u16 len, flags;
432
433 do {
434 /* Prepare new skb as replacement */
435 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
436 bgmac_dma_rx_poison_buf(dma_dev, slot);
437 break;
438 }
439
440 /* Unmap buffer to make it accessible to the CPU */
441 dma_unmap_single(dma_dev, dma_addr,
442 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
443
444 /* Get info from the header */
445 len = le16_to_cpu(rx->len);
446 flags = le16_to_cpu(rx->flags);
447
448 /* Check for poison and drop or pass the packet */
449 if (len == 0xdead && flags == 0xbeef) {
450 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
451 ring->start);
452 put_page(virt_to_head_page(buf));
453 bgmac->net_dev->stats.rx_errors++;
454 break;
455 }
456
457 if (len > BGMAC_RX_ALLOC_SIZE) {
458 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
459 ring->start);
460 put_page(virt_to_head_page(buf));
461 bgmac->net_dev->stats.rx_length_errors++;
462 bgmac->net_dev->stats.rx_errors++;
463 break;
464 }
465
466 /* Omit CRC. */
467 len -= ETH_FCS_LEN;
468
469 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
470 if (unlikely(!skb)) {
471 netdev_err(bgmac->net_dev, "build_skb failed\n");
472 put_page(virt_to_head_page(buf));
473 bgmac->net_dev->stats.rx_errors++;
474 break;
475 }
476 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
477 BGMAC_RX_BUF_OFFSET + len);
478 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
479 BGMAC_RX_BUF_OFFSET);
480
481 skb_checksum_none_assert(skb);
482 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
483 bgmac->net_dev->stats.rx_bytes += len;
484 bgmac->net_dev->stats.rx_packets++;
485 napi_gro_receive(&bgmac->napi, skb);
486 handled++;
487 } while (0);
488
489 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
490
491 if (++ring->start >= BGMAC_RX_RING_SLOTS)
492 ring->start = 0;
493
494 if (handled >= weight) /* Should never be greater */
495 break;
496 }
497
498 bgmac_dma_rx_update_index(bgmac, ring);
499
500 return handled;
501 }
502
503 /* Does ring support unaligned addressing? */
504 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
505 struct bgmac_dma_ring *ring,
506 enum bgmac_dma_ring_type ring_type)
507 {
508 switch (ring_type) {
509 case BGMAC_DMA_RING_TX:
510 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
511 0xff0);
512 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
513 return true;
514 break;
515 case BGMAC_DMA_RING_RX:
516 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
517 0xff0);
518 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
519 return true;
520 break;
521 }
522 return false;
523 }
524
525 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
526 struct bgmac_dma_ring *ring)
527 {
528 struct device *dma_dev = bgmac->dma_dev;
529 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
530 struct bgmac_slot_info *slot;
531 int i;
532
533 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
534 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
535
536 slot = &ring->slots[i];
537 dev_kfree_skb(slot->skb);
538
539 if (!slot->dma_addr)
540 continue;
541
542 if (slot->skb)
543 dma_unmap_single(dma_dev, slot->dma_addr,
544 len, DMA_TO_DEVICE);
545 else
546 dma_unmap_page(dma_dev, slot->dma_addr,
547 len, DMA_TO_DEVICE);
548 }
549 }
550
551 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
552 struct bgmac_dma_ring *ring)
553 {
554 struct device *dma_dev = bgmac->dma_dev;
555 struct bgmac_slot_info *slot;
556 int i;
557
558 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
559 slot = &ring->slots[i];
560 if (!slot->dma_addr)
561 continue;
562
563 dma_unmap_single(dma_dev, slot->dma_addr,
564 BGMAC_RX_BUF_SIZE,
565 DMA_FROM_DEVICE);
566 put_page(virt_to_head_page(slot->buf));
567 slot->dma_addr = 0;
568 }
569 }
570
571 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
572 struct bgmac_dma_ring *ring,
573 int num_slots)
574 {
575 struct device *dma_dev = bgmac->dma_dev;
576 int size;
577
578 if (!ring->cpu_base)
579 return;
580
581 /* Free ring of descriptors */
582 size = num_slots * sizeof(struct bgmac_dma_desc);
583 dma_free_coherent(dma_dev, size, ring->cpu_base,
584 ring->dma_base);
585 }
586
587 static void bgmac_dma_cleanup(struct bgmac *bgmac)
588 {
589 int i;
590
591 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
592 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
593
594 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
595 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
596 }
597
598 static void bgmac_dma_free(struct bgmac *bgmac)
599 {
600 int i;
601
602 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
603 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
604 BGMAC_TX_RING_SLOTS);
605
606 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
607 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
608 BGMAC_RX_RING_SLOTS);
609 }
610
611 static int bgmac_dma_alloc(struct bgmac *bgmac)
612 {
613 struct device *dma_dev = bgmac->dma_dev;
614 struct bgmac_dma_ring *ring;
615 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
616 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
617 int size; /* ring size: different for Tx and Rx */
618 int err;
619 int i;
620
621 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
622 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
623
624 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
625 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
626 return -ENOTSUPP;
627 }
628
629 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
630 ring = &bgmac->tx_ring[i];
631 ring->mmio_base = ring_base[i];
632
633 /* Alloc ring of descriptors */
634 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
635 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
636 &ring->dma_base,
637 GFP_KERNEL);
638 if (!ring->cpu_base) {
639 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
640 ring->mmio_base);
641 goto err_dma_free;
642 }
643
644 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
645 BGMAC_DMA_RING_TX);
646 if (ring->unaligned)
647 ring->index_base = lower_32_bits(ring->dma_base);
648 else
649 ring->index_base = 0;
650
651 /* No need to alloc TX slots yet */
652 }
653
654 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
655 ring = &bgmac->rx_ring[i];
656 ring->mmio_base = ring_base[i];
657
658 /* Alloc ring of descriptors */
659 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
660 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
661 &ring->dma_base,
662 GFP_KERNEL);
663 if (!ring->cpu_base) {
664 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
665 ring->mmio_base);
666 err = -ENOMEM;
667 goto err_dma_free;
668 }
669
670 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
671 BGMAC_DMA_RING_RX);
672 if (ring->unaligned)
673 ring->index_base = lower_32_bits(ring->dma_base);
674 else
675 ring->index_base = 0;
676 }
677
678 return 0;
679
680 err_dma_free:
681 bgmac_dma_free(bgmac);
682 return -ENOMEM;
683 }
684
685 static int bgmac_dma_init(struct bgmac *bgmac)
686 {
687 struct bgmac_dma_ring *ring;
688 int i, err;
689
690 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
691 ring = &bgmac->tx_ring[i];
692
693 if (!ring->unaligned)
694 bgmac_dma_tx_enable(bgmac, ring);
695 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
696 lower_32_bits(ring->dma_base));
697 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
698 upper_32_bits(ring->dma_base));
699 if (ring->unaligned)
700 bgmac_dma_tx_enable(bgmac, ring);
701
702 ring->start = 0;
703 ring->end = 0; /* Points the slot that should *not* be read */
704 }
705
706 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
707 int j;
708
709 ring = &bgmac->rx_ring[i];
710
711 if (!ring->unaligned)
712 bgmac_dma_rx_enable(bgmac, ring);
713 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
714 lower_32_bits(ring->dma_base));
715 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
716 upper_32_bits(ring->dma_base));
717 if (ring->unaligned)
718 bgmac_dma_rx_enable(bgmac, ring);
719
720 ring->start = 0;
721 ring->end = 0;
722 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
723 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
724 if (err)
725 goto error;
726
727 bgmac_dma_rx_setup_desc(bgmac, ring, j);
728 }
729
730 bgmac_dma_rx_update_index(bgmac, ring);
731 }
732
733 return 0;
734
735 error:
736 bgmac_dma_cleanup(bgmac);
737 return err;
738 }
739
740
741 /**************************************************
742 * Chip ops
743 **************************************************/
744
745 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
746 * nothing to change? Try if after stabilizng driver.
747 */
748 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
749 bool force)
750 {
751 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
752 u32 new_val = (cmdcfg & mask) | set;
753 u32 cmdcfg_sr;
754
755 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
756 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
757 else
758 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
759
760 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
761 udelay(2);
762
763 if (new_val != cmdcfg || force)
764 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
765
766 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
767 udelay(2);
768 }
769
770 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
771 {
772 u32 tmp;
773
774 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
775 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
776 tmp = (addr[4] << 8) | addr[5];
777 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
778 }
779
780 static void bgmac_set_rx_mode(struct net_device *net_dev)
781 {
782 struct bgmac *bgmac = netdev_priv(net_dev);
783
784 if (net_dev->flags & IFF_PROMISC)
785 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
786 else
787 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
788 }
789
790 #if 0 /* We don't use that regs yet */
791 static void bgmac_chip_stats_update(struct bgmac *bgmac)
792 {
793 int i;
794
795 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
796 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
797 bgmac->mib_tx_regs[i] =
798 bgmac_read(bgmac,
799 BGMAC_TX_GOOD_OCTETS + (i * 4));
800 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
801 bgmac->mib_rx_regs[i] =
802 bgmac_read(bgmac,
803 BGMAC_RX_GOOD_OCTETS + (i * 4));
804 }
805
806 /* TODO: what else? how to handle BCM4706? Specs are needed */
807 }
808 #endif
809
810 static void bgmac_clear_mib(struct bgmac *bgmac)
811 {
812 int i;
813
814 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
815 return;
816
817 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
818 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
819 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
820 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
821 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
822 }
823
824 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
825 static void bgmac_mac_speed(struct bgmac *bgmac)
826 {
827 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
828 u32 set = 0;
829
830 switch (bgmac->mac_speed) {
831 case SPEED_10:
832 set |= BGMAC_CMDCFG_ES_10;
833 break;
834 case SPEED_100:
835 set |= BGMAC_CMDCFG_ES_100;
836 break;
837 case SPEED_1000:
838 set |= BGMAC_CMDCFG_ES_1000;
839 break;
840 case SPEED_2500:
841 set |= BGMAC_CMDCFG_ES_2500;
842 break;
843 default:
844 dev_err(bgmac->dev, "Unsupported speed: %d\n",
845 bgmac->mac_speed);
846 }
847
848 if (bgmac->mac_duplex == DUPLEX_HALF)
849 set |= BGMAC_CMDCFG_HD;
850
851 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
852 }
853
854 static void bgmac_miiconfig(struct bgmac *bgmac)
855 {
856 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
857 bgmac_idm_write(bgmac, BCMA_IOCTL,
858 bgmac_idm_read(bgmac, BCMA_IOCTL) | 0x40 |
859 BGMAC_BCMA_IOCTL_SW_CLKEN);
860 bgmac->mac_speed = SPEED_2500;
861 bgmac->mac_duplex = DUPLEX_FULL;
862 bgmac_mac_speed(bgmac);
863 } else {
864 u8 imode;
865
866 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
867 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
868 if (imode == 0 || imode == 1) {
869 bgmac->mac_speed = SPEED_100;
870 bgmac->mac_duplex = DUPLEX_FULL;
871 bgmac_mac_speed(bgmac);
872 }
873 }
874 }
875
876 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
877 static void bgmac_chip_reset(struct bgmac *bgmac)
878 {
879 u32 cmdcfg_sr;
880 u32 iost;
881 int i;
882
883 if (bgmac_clk_enabled(bgmac)) {
884 if (!bgmac->stats_grabbed) {
885 /* bgmac_chip_stats_update(bgmac); */
886 bgmac->stats_grabbed = true;
887 }
888
889 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
890 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
891
892 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
893 udelay(1);
894
895 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
896 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
897
898 /* TODO: Clear software multicast filter list */
899 }
900
901 iost = bgmac_idm_read(bgmac, BCMA_IOST);
902 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
903 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
904
905 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
906 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
907 u32 flags = 0;
908 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
909 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
910 if (!bgmac->has_robosw)
911 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
912 }
913 bgmac_clk_enable(bgmac, flags);
914 }
915
916 /* Request Misc PLL for corerev > 2 */
917 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
918 bgmac_set(bgmac, BCMA_CLKCTLST,
919 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
920 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
921 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
922 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
923 1000);
924 }
925
926 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
927 u8 et_swtype = 0;
928 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
929 BGMAC_CHIPCTL_1_IF_TYPE_MII;
930 char buf[4];
931
932 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
933 if (kstrtou8(buf, 0, &et_swtype))
934 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
935 buf);
936 et_swtype &= 0x0f;
937 et_swtype <<= 4;
938 sw_type = et_swtype;
939 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
940 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
941 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
942 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
943 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
944 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
945 }
946 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
947 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
948 sw_type);
949 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
950 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
951 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
952 u8 et_swtype = 0;
953 char buf[4];
954
955 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
956 if (kstrtou8(buf, 0, &et_swtype))
957 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
958 buf);
959 sw_type = (et_swtype & 0x0f) << 12;
960 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
961 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
962 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
963 }
964 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
965 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
966 sw_type);
967 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
968 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
969 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
970 }
971
972 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
973 bgmac_idm_write(bgmac, BCMA_IOCTL,
974 bgmac_idm_read(bgmac, BCMA_IOCTL) &
975 ~BGMAC_BCMA_IOCTL_SW_RESET);
976
977 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
978 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
979 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
980 * be keps until taking MAC out of the reset.
981 */
982 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
983 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
984 else
985 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
986
987 bgmac_cmdcfg_maskset(bgmac,
988 ~(BGMAC_CMDCFG_TE |
989 BGMAC_CMDCFG_RE |
990 BGMAC_CMDCFG_RPI |
991 BGMAC_CMDCFG_TAI |
992 BGMAC_CMDCFG_HD |
993 BGMAC_CMDCFG_ML |
994 BGMAC_CMDCFG_CFE |
995 BGMAC_CMDCFG_RL |
996 BGMAC_CMDCFG_RED |
997 BGMAC_CMDCFG_PE |
998 BGMAC_CMDCFG_TPI |
999 BGMAC_CMDCFG_PAD_EN |
1000 BGMAC_CMDCFG_PF),
1001 BGMAC_CMDCFG_PROM |
1002 BGMAC_CMDCFG_NLC |
1003 BGMAC_CMDCFG_CFE |
1004 cmdcfg_sr,
1005 false);
1006 bgmac->mac_speed = SPEED_UNKNOWN;
1007 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1008
1009 bgmac_clear_mib(bgmac);
1010 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1011 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1012 BCMA_GMAC_CMN_PC_MTE);
1013 else
1014 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1015 bgmac_miiconfig(bgmac);
1016 if (bgmac->mii_bus)
1017 bgmac->mii_bus->reset(bgmac->mii_bus);
1018
1019 netdev_reset_queue(bgmac->net_dev);
1020 }
1021
1022 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1023 {
1024 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1025 }
1026
1027 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1028 {
1029 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1030 bgmac_read(bgmac, BGMAC_INT_MASK);
1031 }
1032
1033 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1034 static void bgmac_enable(struct bgmac *bgmac)
1035 {
1036 u32 cmdcfg_sr;
1037 u32 cmdcfg;
1038 u32 mode;
1039
1040 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1041 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1042 else
1043 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1044
1045 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1046 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1047 cmdcfg_sr, true);
1048 udelay(2);
1049 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1050 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1051
1052 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1053 BGMAC_DS_MM_SHIFT;
1054 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1055 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1056 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1057 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1058 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1059
1060 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1061 BGMAC_FEAT_FLW_CTRL2)) {
1062 u32 fl_ctl;
1063
1064 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1065 fl_ctl = 0x2300e1;
1066 else
1067 fl_ctl = 0x03cb04cb;
1068
1069 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1070 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1071 }
1072
1073 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1074 u32 rxq_ctl;
1075 u16 bp_clk;
1076 u8 mdp;
1077
1078 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1079 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1080 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1081 mdp = (bp_clk * 128 / 1000) - 3;
1082 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1083 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1084 }
1085 }
1086
1087 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1088 static void bgmac_chip_init(struct bgmac *bgmac)
1089 {
1090 /* Clear any erroneously pending interrupts */
1091 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1092
1093 /* 1 interrupt per received frame */
1094 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1095
1096 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1097 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1098
1099 bgmac_set_rx_mode(bgmac->net_dev);
1100
1101 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1102
1103 if (bgmac->loopback)
1104 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1105 else
1106 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1107
1108 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1109
1110 bgmac_chip_intrs_on(bgmac);
1111
1112 bgmac_enable(bgmac);
1113 }
1114
1115 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1116 {
1117 struct bgmac *bgmac = netdev_priv(dev_id);
1118
1119 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1120 int_status &= bgmac->int_mask;
1121
1122 if (!int_status)
1123 return IRQ_NONE;
1124
1125 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1126 if (int_status)
1127 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1128
1129 /* Disable new interrupts until handling existing ones */
1130 bgmac_chip_intrs_off(bgmac);
1131
1132 napi_schedule(&bgmac->napi);
1133
1134 return IRQ_HANDLED;
1135 }
1136
1137 static int bgmac_poll(struct napi_struct *napi, int weight)
1138 {
1139 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1140 int handled = 0;
1141
1142 /* Ack */
1143 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1144
1145 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1146 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1147
1148 /* Poll again if more events arrived in the meantime */
1149 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1150 return weight;
1151
1152 if (handled < weight) {
1153 napi_complete_done(napi, handled);
1154 bgmac_chip_intrs_on(bgmac);
1155 }
1156
1157 return handled;
1158 }
1159
1160 /**************************************************
1161 * net_device_ops
1162 **************************************************/
1163
1164 static int bgmac_open(struct net_device *net_dev)
1165 {
1166 struct bgmac *bgmac = netdev_priv(net_dev);
1167 int err = 0;
1168
1169 bgmac_chip_reset(bgmac);
1170
1171 err = bgmac_dma_init(bgmac);
1172 if (err)
1173 return err;
1174
1175 /* Specs say about reclaiming rings here, but we do that in DMA init */
1176 bgmac_chip_init(bgmac);
1177
1178 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1179 KBUILD_MODNAME, net_dev);
1180 if (err < 0) {
1181 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1182 bgmac_dma_cleanup(bgmac);
1183 return err;
1184 }
1185 napi_enable(&bgmac->napi);
1186
1187 phy_start(net_dev->phydev);
1188
1189 netif_start_queue(net_dev);
1190
1191 return 0;
1192 }
1193
1194 static int bgmac_stop(struct net_device *net_dev)
1195 {
1196 struct bgmac *bgmac = netdev_priv(net_dev);
1197
1198 netif_carrier_off(net_dev);
1199
1200 phy_stop(net_dev->phydev);
1201
1202 napi_disable(&bgmac->napi);
1203 bgmac_chip_intrs_off(bgmac);
1204 free_irq(bgmac->irq, net_dev);
1205
1206 bgmac_chip_reset(bgmac);
1207 bgmac_dma_cleanup(bgmac);
1208
1209 return 0;
1210 }
1211
1212 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1213 struct net_device *net_dev)
1214 {
1215 struct bgmac *bgmac = netdev_priv(net_dev);
1216 struct bgmac_dma_ring *ring;
1217
1218 /* No QOS support yet */
1219 ring = &bgmac->tx_ring[0];
1220 return bgmac_dma_tx_add(bgmac, ring, skb);
1221 }
1222
1223 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1224 {
1225 struct bgmac *bgmac = netdev_priv(net_dev);
1226 struct sockaddr *sa = addr;
1227 int ret;
1228
1229 ret = eth_prepare_mac_addr_change(net_dev, addr);
1230 if (ret < 0)
1231 return ret;
1232
1233 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1234 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1235
1236 eth_commit_mac_addr_change(net_dev, addr);
1237 return 0;
1238 }
1239
1240 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1241 {
1242 if (!netif_running(net_dev))
1243 return -EINVAL;
1244
1245 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1246 }
1247
1248 static const struct net_device_ops bgmac_netdev_ops = {
1249 .ndo_open = bgmac_open,
1250 .ndo_stop = bgmac_stop,
1251 .ndo_start_xmit = bgmac_start_xmit,
1252 .ndo_set_rx_mode = bgmac_set_rx_mode,
1253 .ndo_set_mac_address = bgmac_set_mac_address,
1254 .ndo_validate_addr = eth_validate_addr,
1255 .ndo_do_ioctl = bgmac_ioctl,
1256 };
1257
1258 /**************************************************
1259 * ethtool_ops
1260 **************************************************/
1261
1262 struct bgmac_stat {
1263 u8 size;
1264 u32 offset;
1265 const char *name;
1266 };
1267
1268 static struct bgmac_stat bgmac_get_strings_stats[] = {
1269 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1270 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1271 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1272 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1273 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1274 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1275 { 4, BGMAC_TX_LEN_64, "tx_64" },
1276 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1277 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1278 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1279 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1280 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1281 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1282 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1283 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1284 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1285 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1286 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1287 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1288 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1289 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1290 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1291 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1292 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1293 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1294 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1295 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1296 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1297 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1298 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1299 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1300 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1301 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1302 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1303 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1304 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1305 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1306 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1307 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1308 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1309 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1310 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1311 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1312 { 4, BGMAC_RX_LEN_64, "rx_64" },
1313 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1314 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1315 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1316 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1317 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1318 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1319 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1320 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1321 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1322 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1323 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1324 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1325 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1326 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1327 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1328 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1329 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1330 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1331 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1332 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1333 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1334 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1335 };
1336
1337 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1338
1339 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1340 {
1341 switch (string_set) {
1342 case ETH_SS_STATS:
1343 return BGMAC_STATS_LEN;
1344 }
1345
1346 return -EOPNOTSUPP;
1347 }
1348
1349 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1350 u8 *data)
1351 {
1352 int i;
1353
1354 if (stringset != ETH_SS_STATS)
1355 return;
1356
1357 for (i = 0; i < BGMAC_STATS_LEN; i++)
1358 strlcpy(data + i * ETH_GSTRING_LEN,
1359 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1360 }
1361
1362 static void bgmac_get_ethtool_stats(struct net_device *dev,
1363 struct ethtool_stats *ss, uint64_t *data)
1364 {
1365 struct bgmac *bgmac = netdev_priv(dev);
1366 const struct bgmac_stat *s;
1367 unsigned int i;
1368 u64 val;
1369
1370 if (!netif_running(dev))
1371 return;
1372
1373 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1374 s = &bgmac_get_strings_stats[i];
1375 val = 0;
1376 if (s->size == 8)
1377 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1378 val |= bgmac_read(bgmac, s->offset);
1379 data[i] = val;
1380 }
1381 }
1382
1383 static void bgmac_get_drvinfo(struct net_device *net_dev,
1384 struct ethtool_drvinfo *info)
1385 {
1386 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1387 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1388 }
1389
1390 static const struct ethtool_ops bgmac_ethtool_ops = {
1391 .get_strings = bgmac_get_strings,
1392 .get_sset_count = bgmac_get_sset_count,
1393 .get_ethtool_stats = bgmac_get_ethtool_stats,
1394 .get_drvinfo = bgmac_get_drvinfo,
1395 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1396 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1397 };
1398
1399 /**************************************************
1400 * MII
1401 **************************************************/
1402
1403 void bgmac_adjust_link(struct net_device *net_dev)
1404 {
1405 struct bgmac *bgmac = netdev_priv(net_dev);
1406 struct phy_device *phy_dev = net_dev->phydev;
1407 bool update = false;
1408
1409 if (phy_dev->link) {
1410 if (phy_dev->speed != bgmac->mac_speed) {
1411 bgmac->mac_speed = phy_dev->speed;
1412 update = true;
1413 }
1414
1415 if (phy_dev->duplex != bgmac->mac_duplex) {
1416 bgmac->mac_duplex = phy_dev->duplex;
1417 update = true;
1418 }
1419 }
1420
1421 if (update) {
1422 bgmac_mac_speed(bgmac);
1423 phy_print_status(phy_dev);
1424 }
1425 }
1426 EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1427
1428 int bgmac_phy_connect_direct(struct bgmac *bgmac)
1429 {
1430 struct fixed_phy_status fphy_status = {
1431 .link = 1,
1432 .speed = SPEED_1000,
1433 .duplex = DUPLEX_FULL,
1434 };
1435 struct phy_device *phy_dev;
1436 int err;
1437
1438 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1439 if (!phy_dev || IS_ERR(phy_dev)) {
1440 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1441 return -ENODEV;
1442 }
1443
1444 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1445 PHY_INTERFACE_MODE_MII);
1446 if (err) {
1447 dev_err(bgmac->dev, "Connecting PHY failed\n");
1448 return err;
1449 }
1450
1451 return err;
1452 }
1453 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1454
1455 struct bgmac *bgmac_alloc(struct device *dev)
1456 {
1457 struct net_device *net_dev;
1458 struct bgmac *bgmac;
1459
1460 /* Allocation and references */
1461 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1462 if (!net_dev)
1463 return NULL;
1464
1465 net_dev->netdev_ops = &bgmac_netdev_ops;
1466 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1467
1468 bgmac = netdev_priv(net_dev);
1469 bgmac->dev = dev;
1470 bgmac->net_dev = net_dev;
1471
1472 return bgmac;
1473 }
1474 EXPORT_SYMBOL_GPL(bgmac_alloc);
1475
1476 int bgmac_enet_probe(struct bgmac *bgmac)
1477 {
1478 struct net_device *net_dev = bgmac->net_dev;
1479 int err;
1480
1481 net_dev->irq = bgmac->irq;
1482 SET_NETDEV_DEV(net_dev, bgmac->dev);
1483
1484 if (!is_valid_ether_addr(net_dev->dev_addr)) {
1485 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1486 net_dev->dev_addr);
1487 eth_hw_addr_random(net_dev);
1488 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1489 net_dev->dev_addr);
1490 }
1491
1492 /* This (reset &) enable is not preset in specs or reference driver but
1493 * Broadcom does it in arch PCI code when enabling fake PCI device.
1494 */
1495 bgmac_clk_enable(bgmac, 0);
1496
1497 /* This seems to be fixing IRQ by assigning OOB #6 to the core */
1498 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1499 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1500
1501 bgmac_chip_reset(bgmac);
1502
1503 err = bgmac_dma_alloc(bgmac);
1504 if (err) {
1505 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1506 goto err_out;
1507 }
1508
1509 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1510 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1511 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1512
1513 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1514
1515 err = bgmac_phy_connect(bgmac);
1516 if (err) {
1517 dev_err(bgmac->dev, "Cannot connect to phy\n");
1518 goto err_dma_free;
1519 }
1520
1521 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1522 net_dev->hw_features = net_dev->features;
1523 net_dev->vlan_features = net_dev->features;
1524
1525 err = register_netdev(bgmac->net_dev);
1526 if (err) {
1527 dev_err(bgmac->dev, "Cannot register net device\n");
1528 goto err_phy_disconnect;
1529 }
1530
1531 netif_carrier_off(net_dev);
1532
1533 return 0;
1534
1535 err_phy_disconnect:
1536 phy_disconnect(net_dev->phydev);
1537 err_dma_free:
1538 bgmac_dma_free(bgmac);
1539 err_out:
1540
1541 return err;
1542 }
1543 EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1544
1545 void bgmac_enet_remove(struct bgmac *bgmac)
1546 {
1547 unregister_netdev(bgmac->net_dev);
1548 phy_disconnect(bgmac->net_dev->phydev);
1549 netif_napi_del(&bgmac->napi);
1550 bgmac_dma_free(bgmac);
1551 free_netdev(bgmac->net_dev);
1552 }
1553 EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1554
1555 MODULE_AUTHOR("Rafał Miłecki");
1556 MODULE_LICENSE("GPL");
Linux with added FPC-III support