drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  * Copyright (c) 2014 QLogic Corporation
   3  * All rights reserved
   4  *
   5  * Unless you and QLogic execute a separate written software license
   6  * agreement governing use of this software, this software is licensed to you
   7  * under the terms of the GNU General Public License version 2, available
   8  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
   9  *
  10  * Notwithstanding the above, under no circumstances may you combine this
  11  * software in any way with any other Qlogic software provided under a
  12  * license other than the GPL, without Qlogic's express prior written
  13  * consent.
  14  *
  15  * Written by Yaniv Rosner
  16  *
  17  */
  18
  19 #ifndef BNX2X_LINK_H
  20 #define BNX2X_LINK_H
  21
  22
  23
  24 /***********************************************************/
  25 /*                         Defines                         */
  26 /***********************************************************/
  27 #define DEFAULT_PHY_DEV_ADDR    3
  28 #define E2_DEFAULT_PHY_DEV_ADDR 5
  29
  30
  31
  32 #define BNX2X_FLOW_CTRL_AUTO            PORT_FEATURE_FLOW_CONTROL_AUTO
  33 #define BNX2X_FLOW_CTRL_TX              PORT_FEATURE_FLOW_CONTROL_TX
  34 #define BNX2X_FLOW_CTRL_RX              PORT_FEATURE_FLOW_CONTROL_RX
  35 #define BNX2X_FLOW_CTRL_BOTH            PORT_FEATURE_FLOW_CONTROL_BOTH
  36 #define BNX2X_FLOW_CTRL_NONE            PORT_FEATURE_FLOW_CONTROL_NONE
  37
  38 #define NET_SERDES_IF_XFI               1
  39 #define NET_SERDES_IF_SFI               2
  40 #define NET_SERDES_IF_KR                3
  41 #define NET_SERDES_IF_DXGXS     4
  42
  43 #define SPEED_AUTO_NEG          0
  44 #define SPEED_20000             20000
  45
  46 #define I2C_DEV_ADDR_A0                 0xa0
  47 #define I2C_DEV_ADDR_A2                 0xa2
  48
  49 #define SFP_EEPROM_PAGE_SIZE                    16
  50 #define SFP_EEPROM_VENDOR_NAME_ADDR             0x14
  51 #define SFP_EEPROM_VENDOR_NAME_SIZE             16
  52 #define SFP_EEPROM_VENDOR_OUI_ADDR              0x25
  53 #define SFP_EEPROM_VENDOR_OUI_SIZE              3
  54 #define SFP_EEPROM_PART_NO_ADDR                 0x28
  55 #define SFP_EEPROM_PART_NO_SIZE                 16
  56 #define SFP_EEPROM_REVISION_ADDR                0x38
  57 #define SFP_EEPROM_REVISION_SIZE                4
  58 #define SFP_EEPROM_SERIAL_ADDR                  0x44
  59 #define SFP_EEPROM_SERIAL_SIZE                  16
  60 #define SFP_EEPROM_DATE_ADDR                    0x54 /* ASCII YYMMDD */
  61 #define SFP_EEPROM_DATE_SIZE                    6
  62 #define SFP_EEPROM_DIAG_TYPE_ADDR               0x5c
  63 #define SFP_EEPROM_DIAG_TYPE_SIZE               1
  64 #define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ         (1<<2)
  65 #define SFP_EEPROM_SFF_8472_COMP_ADDR           0x5e
  66 #define SFP_EEPROM_SFF_8472_COMP_SIZE           1
  67
  68 #define SFP_EEPROM_A2_CHECKSUM_RANGE            0x5e
  69 #define SFP_EEPROM_A2_CC_DMI_ADDR               0x5f
  70
  71 #define PWR_FLT_ERR_MSG_LEN                     250
  72
  73 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
  74                 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
  75 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
  76                 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
  77                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
  78 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
  79                 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
  80
  81 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
  82 #define SINGLE_MEDIA_DIRECT(params)     (params->num_phys == 1)
  83 /* Single Media board contains single external phy */
  84 #define SINGLE_MEDIA(params)            (params->num_phys == 2)
  85 /* Dual Media board contains two external phy with different media */
  86 #define DUAL_MEDIA(params)              (params->num_phys == 3)
  87
  88 #define FW_PARAM_PHY_ADDR_MASK          0x000000FF
  89 #define FW_PARAM_PHY_TYPE_MASK          0x0000FF00
  90 #define FW_PARAM_MDIO_CTRL_MASK         0xFFFF0000
  91 #define FW_PARAM_MDIO_CTRL_OFFSET               16
  92 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
  93                                            FW_PARAM_PHY_ADDR_MASK)
  94 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
  95                                            FW_PARAM_PHY_TYPE_MASK)
  96 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
  97                                             FW_PARAM_MDIO_CTRL_MASK) >> \
  98                                             FW_PARAM_MDIO_CTRL_OFFSET)
  99 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
 100         (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
 101
 102
 103 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD                          170
 104 #define PFC_BRB_FULL_LB_XON_THRESHOLD                           250
 105
 106 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
 107
 108 #define BMAC_CONTROL_RX_ENABLE          2
 109 /***********************************************************/
 110 /*                         Structs                         */
 111 /***********************************************************/
 112 #define INT_PHY         0
 113 #define EXT_PHY1        1
 114 #define EXT_PHY2        2
 115 #define MAX_PHYS        3
 116
 117 /* Same configuration is shared between the XGXS and the first external phy */
 118 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
 119 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
 120                                          0 : (_phy_idx - 1))
 121 /***********************************************************/
 122 /*                      bnx2x_phy struct                     */
 123 /*  Defines the required arguments and function per phy    */
 124 /***********************************************************/
 125 struct link_vars;
 126 struct link_params;
 127 struct bnx2x_phy;
 128
 129 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
 130                             struct link_vars *vars);
 131 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
 132                             struct link_vars *vars);
 133 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
 134                              struct link_params *params);
 135 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
 136                                   struct link_params *params);
 137 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
 138 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
 139 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
 140                                struct link_params *params, u8 mode);
 141 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
 142                                     struct link_params *params, u32 action);
 143 struct bnx2x_reg_set {
 144         u8  devad;
 145         u16 reg;
 146         u16 val;
 147 };
 148
 149 struct bnx2x_phy {
 150         u32 type;
 151
 152         /* Loaded during init */
 153         u8 addr;
 154         u8 def_md_devad;
 155         u16 flags;
 156         /* No Over-Current detection */
 157 #define FLAGS_NOC                       (1<<1)
 158         /* Fan failure detection required */
 159 #define FLAGS_FAN_FAILURE_DET_REQ       (1<<2)
 160         /* Initialize first the XGXS and only then the phy itself */
 161 #define FLAGS_INIT_XGXS_FIRST           (1<<3)
 162 #define FLAGS_WC_DUAL_MODE              (1<<4)
 163 #define FLAGS_4_PORT_MODE               (1<<5)
 164 #define FLAGS_REARM_LATCH_SIGNAL        (1<<6)
 165 #define FLAGS_SFP_NOT_APPROVED          (1<<7)
 166 #define FLAGS_MDC_MDIO_WA               (1<<8)
 167 #define FLAGS_DUMMY_READ                (1<<9)
 168 #define FLAGS_MDC_MDIO_WA_B0            (1<<10)
 169 #define FLAGS_TX_ERROR_CHECK            (1<<12)
 170 #define FLAGS_EEE                       (1<<13)
 171 #define FLAGS_MDC_MDIO_WA_G             (1<<15)
 172
 173         /* preemphasis values for the rx side */
 174         u16 rx_preemphasis[4];
 175
 176         /* preemphasis values for the tx side */
 177         u16 tx_preemphasis[4];
 178
 179         /* EMAC address for access MDIO */
 180         u32 mdio_ctrl;
 181
 182         u32 supported;
 183
 184         u32 media_type;
 185 #define ETH_PHY_UNSPECIFIED     0x0
 186 #define ETH_PHY_SFPP_10G_FIBER  0x1
 187 #define ETH_PHY_XFP_FIBER               0x2
 188 #define ETH_PHY_DA_TWINAX               0x3
 189 #define ETH_PHY_BASE_T          0x4
 190 #define ETH_PHY_SFP_1G_FIBER    0x5
 191 #define ETH_PHY_KR              0xf0
 192 #define ETH_PHY_CX4             0xf1
 193 #define ETH_PHY_NOT_PRESENT     0xff
 194
 195         /* The address in which version is located*/
 196         u32 ver_addr;
 197
 198         u16 req_flow_ctrl;
 199
 200         u16 req_line_speed;
 201
 202         u32 speed_cap_mask;
 203
 204         u16 req_duplex;
 205         u16 rsrv;
 206         /* Called per phy/port init, and it configures LASI, speed, autoneg,
 207          duplex, flow control negotiation, etc. */
 208         config_init_t config_init;
 209
 210         /* Called due to interrupt. It determines the link, speed */
 211         read_status_t read_status;
 212
 213         /* Called when driver is unloading. Should reset the phy */
 214         link_reset_t link_reset;
 215
 216         /* Set the loopback configuration for the phy */
 217         config_loopback_t config_loopback;
 218
 219         /* Format the given raw number into str up to len */
 220         format_fw_ver_t format_fw_ver;
 221
 222         /* Reset the phy (both ports) */
 223         hw_reset_t hw_reset;
 224
 225         /* Set link led mode (on/off/oper)*/
 226         set_link_led_t set_link_led;
 227
 228         /* PHY Specific tasks */
 229         phy_specific_func_t phy_specific_func;
 230 #define DISABLE_TX      1
 231 #define ENABLE_TX       2
 232 #define PHY_INIT        3
 233 };
 234
 235 /* Inputs parameters to the CLC */
 236 struct link_params {
 237
 238         u8 port;
 239
 240         /* Default / User Configuration */
 241         u8 loopback_mode;
 242 #define LOOPBACK_NONE           0
 243 #define LOOPBACK_EMAC           1
 244 #define LOOPBACK_BMAC           2
 245 #define LOOPBACK_XGXS           3
 246 #define LOOPBACK_EXT_PHY        4
 247 #define LOOPBACK_EXT            5
 248 #define LOOPBACK_UMAC           6
 249 #define LOOPBACK_XMAC           7
 250
 251         /* Device parameters */
 252         u8 mac_addr[6];
 253
 254         u16 req_duplex[LINK_CONFIG_SIZE];
 255         u16 req_flow_ctrl[LINK_CONFIG_SIZE];
 256
 257         u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
 258
 259         /* shmem parameters */
 260         u32 shmem_base;
 261         u32 shmem2_base;
 262         u32 speed_cap_mask[LINK_CONFIG_SIZE];
 263         u32 switch_cfg;
 264 #define SWITCH_CFG_1G           PORT_FEATURE_CON_SWITCH_1G_SWITCH
 265 #define SWITCH_CFG_10G          PORT_FEATURE_CON_SWITCH_10G_SWITCH
 266 #define SWITCH_CFG_AUTO_DETECT  PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 267
 268         u32 lane_config;
 269
 270         /* Phy register parameter */
 271         u32 chip_id;
 272
 273         /* features */
 274         u32 feature_config_flags;
 275 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED     (1<<0)
 276 #define FEATURE_CONFIG_PFC_ENABLED                      (1<<1)
 277 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY         (1<<2)
 278 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
 279 #define FEATURE_CONFIG_BC_SUPPORTS_AFEX                 (1<<8)
 280 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED                       (1<<9)
 281 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED              (1<<10)
 282 #define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET         (1<<11)
 283 #define FEATURE_CONFIG_MT_SUPPORT                       (1<<13)
 284 #define FEATURE_CONFIG_BOOT_FROM_SAN                    (1<<14)
 285
 286         /* Will be populated during common init */
 287         struct bnx2x_phy phy[MAX_PHYS];
 288
 289         /* Will be populated during common init */
 290         u8 num_phys;
 291
 292         u8 rsrv;
 293
 294         /* Used to configure the EEE Tx LPI timer, has several modes of
 295          * operation, according to bits 29:28 -
 296          * 2'b00: Timer will be configured by nvram, output will be the value
 297          *        from nvram.
 298          * 2'b01: Timer will be configured by nvram, output will be in
 299          *        microseconds.
 300          * 2'b10: bits 1:0 contain an nvram value which will be used instead
 301          *        of the one located in the nvram. Output will be that value.
 302          * 2'b11: bits 19:0 contain the idle timer in microseconds; output
 303          *        will be in microseconds.
 304          * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
 305          */
 306         u32 eee_mode;
 307 #define EEE_MODE_NVRAM_BALANCED_TIME            (0xa00)
 308 #define EEE_MODE_NVRAM_AGGRESSIVE_TIME          (0x100)
 309 #define EEE_MODE_NVRAM_LATENCY_TIME             (0x6000)
 310 #define EEE_MODE_NVRAM_MASK             (0x3)
 311 #define EEE_MODE_TIMER_MASK             (0xfffff)
 312 #define EEE_MODE_OUTPUT_TIME            (1<<28)
 313 #define EEE_MODE_OVERRIDE_NVRAM         (1<<29)
 314 #define EEE_MODE_ENABLE_LPI             (1<<30)
 315 #define EEE_MODE_ADV_LPI                        (1<<31)
 316
 317         u16 hw_led_mode; /* part of the hw_config read from the shmem */
 318         u32 multi_phy_config;
 319
 320         /* Device pointer passed to all callback functions */
 321         struct bnx2x *bp;
 322         u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
 323                                 req_flow_ctrl is set to AUTO */
 324         u16 link_flags;
 325 #define LINK_FLAGS_INT_DISABLED         (1<<0)
 326 #define PHY_INITIALIZED         (1<<1)
 327         u32 lfa_base;
 328
 329         /* The same definitions as the shmem2 parameter */
 330         u32 link_attr_sync;
 331 };
 332
 333 /* Output parameters */
 334 struct link_vars {
 335         u8 phy_flags;
 336 #define PHY_XGXS_FLAG                   (1<<0)
 337 #define PHY_SGMII_FLAG                  (1<<1)
 338 #define PHY_PHYSICAL_LINK_FLAG          (1<<2)
 339 #define PHY_HALF_OPEN_CONN_FLAG         (1<<3)
 340 #define PHY_OVER_CURRENT_FLAG           (1<<4)
 341 #define PHY_SFP_TX_FAULT_FLAG           (1<<5)
 342
 343         u8 mac_type;
 344 #define MAC_TYPE_NONE           0
 345 #define MAC_TYPE_EMAC           1
 346 #define MAC_TYPE_BMAC           2
 347 #define MAC_TYPE_UMAC           3
 348 #define MAC_TYPE_XMAC           4
 349
 350         u8 phy_link_up; /* internal phy link indication */
 351         u8 link_up;
 352
 353         u16 line_speed;
 354         u16 duplex;
 355
 356         u16 flow_ctrl;
 357         u16 ieee_fc;
 358
 359         /* The same definitions as the shmem parameter */
 360         u32 link_status;
 361         u32 eee_status;
 362         u8 fault_detected;
 363         u8 check_kr2_recovery_cnt;
 364 #define CHECK_KR2_RECOVERY_CNT  5
 365         u16 periodic_flags;
 366 #define PERIODIC_FLAGS_LINK_EVENT       0x0001
 367
 368         u32 aeu_int_mask;
 369         u8 rx_tx_asic_rst;
 370         u8 turn_to_run_wc_rt;
 371         u16 rsrv2;
 372 };
 373
 374 /***********************************************************/
 375 /*                         Functions                       */
 376 /***********************************************************/
 377 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
 378
 379 /* Reset the link. Should be called when driver or interface goes down
 380    Before calling phy firmware upgrade, the reset_ext_phy should be set
 381    to 0 */
 382 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 383                      u8 reset_ext_phy);
 384 int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
 385 /* bnx2x_link_update should be called upon link interrupt */
 386 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
 387
 388 /* use the following phy functions to read/write from external_phy
 389   In order to use it to read/write internal phy registers, use
 390   DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
 391   the register */
 392 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
 393                    u8 devad, u16 reg, u16 *ret_val);
 394
 395 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
 396                     u8 devad, u16 reg, u16 val);
 397
 398 /* Reads the link_status from the shmem,
 399    and update the link vars accordingly */
 400 void bnx2x_link_status_update(struct link_params *input,
 401                             struct link_vars *output);
 402 /* returns string representing the fw_version of the external phy */
 403 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
 404                                  u16 len);
 405
 406 /* Set/Unset the led
 407    Basically, the CLC takes care of the led for the link, but in case one needs
 408    to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
 409    blink the led, and LED_MODE_OFF to set the led off.*/
 410 int bnx2x_set_led(struct link_params *params,
 411                   struct link_vars *vars, u8 mode, u32 speed);
 412 #define LED_MODE_OFF                    0
 413 #define LED_MODE_ON                     1
 414 #define LED_MODE_OPER                   2
 415 #define LED_MODE_FRONT_PANEL_OFF        3
 416
 417 /* bnx2x_handle_module_detect_int should be called upon module detection
 418    interrupt */
 419 void bnx2x_handle_module_detect_int(struct link_params *params);
 420
 421 /* Get the actual link status. In case it returns 0, link is up,
 422         otherwise link is down*/
 423 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
 424                     u8 is_serdes);
 425
 426 /* One-time initialization for external phy after power up */
 427 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
 428                           u32 shmem2_base_path[], u32 chip_id);
 429
 430 /* Reset the external PHY using GPIO */
 431 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
 432
 433 /* Reset the external of SFX7101 */
 434 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
 435
 436 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
 437 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
 438                                  struct link_params *params, u8 dev_addr,
 439                                  u16 addr, u16 byte_cnt, u8 *o_buf);
 440
 441 void bnx2x_hw_reset_phy(struct link_params *params);
 442
 443 /* Check swap bit and adjust PHY order */
 444 u32 bnx2x_phy_selection(struct link_params *params);
 445
 446 /* Probe the phys on board, and populate them in "params" */
 447 int bnx2x_phy_probe(struct link_params *params);
 448
 449 /* Checks if fan failure detection is required on one of the phys on board */
 450 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
 451                              u32 shmem2_base, u8 port);
 452
 453 /* Open / close the gate between the NIG and the BRB */
 454 void bnx2x_set_rx_filter(struct link_params *params, u8 en);
 455
 456 /* DCBX structs */
 457
 458 /* Number of maximum COS per chip */
 459 #define DCBX_E2E3_MAX_NUM_COS           (2)
 460 #define DCBX_E3B0_MAX_NUM_COS_PORT0     (6)
 461 #define DCBX_E3B0_MAX_NUM_COS_PORT1     (3)
 462 #define DCBX_E3B0_MAX_NUM_COS           ( \
 463                         MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
 464                             DCBX_E3B0_MAX_NUM_COS_PORT1))
 465
 466 #define DCBX_MAX_NUM_COS                        ( \
 467                         MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
 468                             DCBX_E2E3_MAX_NUM_COS))
 469
 470 /* PFC port configuration params */
 471 struct bnx2x_nig_brb_pfc_port_params {
 472         /* NIG */
 473         u32 pause_enable;
 474         u32 llfc_out_en;
 475         u32 llfc_enable;
 476         u32 pkt_priority_to_cos;
 477         u8 num_of_rx_cos_priority_mask;
 478         u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
 479         u32 llfc_high_priority_classes;
 480         u32 llfc_low_priority_classes;
 481 };
 482
 483
 484 /* ETS port configuration params */
 485 struct bnx2x_ets_bw_params {
 486         u8 bw;
 487 };
 488
 489 struct bnx2x_ets_sp_params {
 490         /**
 491          * valid values are 0 - 5. 0 is highest strict priority.
 492          * There can't be two COS's with the same pri.
 493          */
 494         u8 pri;
 495 };
 496
 497 enum bnx2x_cos_state {
 498         bnx2x_cos_state_strict = 0,
 499         bnx2x_cos_state_bw = 1,
 500 };
 501
 502 struct bnx2x_ets_cos_params {
 503         enum bnx2x_cos_state state ;
 504         union {
 505                 struct bnx2x_ets_bw_params bw_params;
 506                 struct bnx2x_ets_sp_params sp_params;
 507         } params;
 508 };
 509
 510 struct bnx2x_ets_params {
 511         u8 num_of_cos; /* Number of valid COS entries*/
 512         struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
 513 };
 514
 515 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 516  * when link is already up
 517  */
 518 int bnx2x_update_pfc(struct link_params *params,
 519                       struct link_vars *vars,
 520                       struct bnx2x_nig_brb_pfc_port_params *pfc_params);
 521
 522
 523 /* Used to configure the ETS to disable */
 524 int bnx2x_ets_disabled(struct link_params *params,
 525                        struct link_vars *vars);
 526
 527 /* Used to configure the ETS to BW limited */
 528 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 529                         const u32 cos1_bw);
 530
 531 /* Used to configure the ETS to strict */
 532 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
 533
 534
 535 /*  Configure the COS to ETS according to BW and SP settings.*/
 536 int bnx2x_ets_e3b0_config(const struct link_params *params,
 537                          const struct link_vars *vars,
 538                          struct bnx2x_ets_params *ets_params);
 539
 540 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
 541                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
 542                             u8 port);
 543
 544 void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
 545
 546 #endif /* BNX2X_LINK_H */