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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / dec / tulip / de4x5.c
blobdf4a871df633d269436a30bb108f157143b692a2
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Up to 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <linux/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static const char version[] =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485 #define c_char const char
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow up to 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 bool fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901 static int de4x5_close(struct net_device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct net_device *dev);
905 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907 /*
908 ** Private functions
909 */
910 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int de4x5_init(struct net_device *dev);
912 static int de4x5_sw_reset(struct net_device *dev);
913 static int de4x5_rx(struct net_device *dev);
914 static int de4x5_tx(struct net_device *dev);
915 static void de4x5_ast(struct net_device *dev);
916 static int de4x5_txur(struct net_device *dev);
917 static int de4x5_rx_ovfc(struct net_device *dev);
918
919 static int autoconf_media(struct net_device *dev);
920 static void create_packet(struct net_device *dev, char *frame, int len);
921 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int dc21040_autoconf(struct net_device *dev);
923 static int dc21041_autoconf(struct net_device *dev);
924 static int dc21140m_autoconf(struct net_device *dev);
925 static int dc2114x_autoconf(struct net_device *dev);
926 static int srom_autoconf(struct net_device *dev);
927 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int test_for_100Mb(struct net_device *dev, int msec);
931 static int wait_for_link(struct net_device *dev);
932 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933 static int is_spd_100(struct net_device *dev);
934 static int is_100_up(struct net_device *dev);
935 static int is_10_up(struct net_device *dev);
936 static int is_anc_capable(struct net_device *dev);
937 static int ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void de4x5_free_rx_buffs(struct net_device *dev);
940 static void de4x5_free_tx_buffs(struct net_device *dev);
941 static void de4x5_save_skbs(struct net_device *dev);
942 static void de4x5_rst_desc_ring(struct net_device *dev);
943 static void de4x5_cache_state(struct net_device *dev, int flag);
944 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void de4x5_setup_intr(struct net_device *dev);
948 static void de4x5_init_connection(struct net_device *dev);
949 static int de4x5_reset_phy(struct net_device *dev);
950 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int test_tp(struct net_device *dev, s32 msec);
953 static int EISA_signature(char *name, struct device *device);
954 static int PCI_signature(char *name, struct de4x5_private *lp);
955 static void DevicePresent(struct net_device *dev, u_long iobase);
956 static void enet_addr_rst(u_long aprom_addr);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
958 static short srom_rd(u_long address, u_char offset);
959 static void srom_latch(u_int command, u_long address);
960 static void srom_command(u_int command, u_long address);
961 static void srom_address(u_int command, u_long address, u_char offset);
962 static short srom_data(u_int command, u_long address);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command, u_long addr);
965 static int getfrom_srom(u_long addr);
966 static int srom_map_media(struct net_device *dev);
967 static int srom_infoleaf_info(struct net_device *dev);
968 static void srom_init(struct net_device *dev);
969 static void srom_exec(struct net_device *dev, u_char *p);
970 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int mii_rdata(u_long ioaddr);
973 static void mii_wdata(int data, int len, u_long ioaddr);
974 static void mii_ta(u_long rw, u_long ioaddr);
975 static int mii_swap(int data, int len);
976 static void mii_address(u_char addr, u_long ioaddr);
977 static void sendto_mii(u32 command, int data, u_long ioaddr);
978 static int getfrom_mii(u32 command, u_long ioaddr);
979 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int mii_get_phy(struct net_device *dev);
981 static void SetMulticastFilter(struct net_device *dev);
982 static int get_hw_addr(struct net_device *dev);
983 static void srom_repair(struct net_device *dev, int card);
984 static int test_bad_enet(struct net_device *dev, int status);
985 static int an_exception(struct de4x5_private *lp);
986 static char *build_setup_frame(struct net_device *dev, int mode);
987 static void disable_ast(struct net_device *dev);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void yawn(struct net_device *dev, int state);
992 static void de4x5_parse_params(struct net_device *dev);
993 static void de4x5_dbg_open(struct net_device *dev);
994 static void de4x5_dbg_mii(struct net_device *dev, int k);
995 static void de4x5_dbg_media(struct net_device *dev);
996 static void de4x5_dbg_srom(struct de4x5_srom *p);
997 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998 static int dc21041_infoleaf(struct net_device *dev);
999 static int dc21140_infoleaf(struct net_device *dev);
1000 static int dc21142_infoleaf(struct net_device *dev);
1001 static int dc21143_infoleaf(struct net_device *dev);
1002 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1003 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1009
1010 /*
1011 ** Note now that module autoprobing is allowed under EISA and PCI. The
1012 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1013 ** to "do the right thing".
1014 */
1015
1016 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1017
1018 module_param(io, int, 0);
1019 module_param(de4x5_debug, int, 0);
1020 module_param(dec_only, int, 0);
1021 module_param(args, charp, 0);
1022
1023 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1024 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1025 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1026 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1027 MODULE_LICENSE("GPL");
1028
1029 /*
1030 ** List the SROM infoleaf functions and chipsets
1031 */
1032 struct InfoLeaf {
1033 int chipset;
1034 int (*fn)(struct net_device *);
1035 };
1036 static struct InfoLeaf infoleaf_array[] = {
1037 {DC21041, dc21041_infoleaf},
1038 {DC21140, dc21140_infoleaf},
1039 {DC21142, dc21142_infoleaf},
1040 {DC21143, dc21143_infoleaf}
1041 };
1042 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1043
1044 /*
1045 ** List the SROM info block functions
1046 */
1047 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1048 type0_infoblock,
1049 type1_infoblock,
1050 type2_infoblock,
1051 type3_infoblock,
1052 type4_infoblock,
1053 type5_infoblock,
1054 compact_infoblock
1055 };
1056
1057 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1058
1059 /*
1060 ** Miscellaneous defines...
1061 */
1062 #define RESET_DE4X5 {\
1063 int i;\
1064 i=inl(DE4X5_BMR);\
1065 mdelay(1);\
1066 outl(i | BMR_SWR, DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i, DE4X5_BMR);\
1069 mdelay(1);\
1070 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1071 mdelay(1);\
1072 }
1073
1074 #define PHY_HARD_RESET {\
1075 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1076 mdelay(1); /* Assert for 1ms */\
1077 outl(0x00, DE4X5_GEP);\
1078 mdelay(2); /* Wait for 2ms */\
1079 }
1080
1081 static const struct net_device_ops de4x5_netdev_ops = {
1082 .ndo_open = de4x5_open,
1083 .ndo_stop = de4x5_close,
1084 .ndo_start_xmit = de4x5_queue_pkt,
1085 .ndo_get_stats = de4x5_get_stats,
1086 .ndo_set_rx_mode = set_multicast_list,
1087 .ndo_do_ioctl = de4x5_ioctl,
1088 .ndo_set_mac_address= eth_mac_addr,
1089 .ndo_validate_addr = eth_validate_addr,
1090 };
1091
1092
1093 static int
1094 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1095 {
1096 char name[DE4X5_NAME_LENGTH + 1];
1097 struct de4x5_private *lp = netdev_priv(dev);
1098 struct pci_dev *pdev = NULL;
1099 int i, status=0;
1100
1101 dev_set_drvdata(gendev, dev);
1102
1103 /* Ensure we're not sleeping */
1104 if (lp->bus == EISA) {
1105 outb(WAKEUP, PCI_CFPM);
1106 } else {
1107 pdev = to_pci_dev (gendev);
1108 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1109 }
1110 mdelay(10);
1111
1112 RESET_DE4X5;
1113
1114 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1115 return -ENXIO; /* Hardware could not reset */
1116 }
1117
1118 /*
1119 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1120 */
1121 lp->useSROM = false;
1122 if (lp->bus == PCI) {
1123 PCI_signature(name, lp);
1124 } else {
1125 EISA_signature(name, gendev);
1126 }
1127
1128 if (*name == '\0') { /* Not found a board signature */
1129 return -ENXIO;
1130 }
1131
1132 dev->base_addr = iobase;
1133 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1134
1135 status = get_hw_addr(dev);
1136 printk(", h/w address %pM\n", dev->dev_addr);
1137
1138 if (status != 0) {
1139 printk(" which has an Ethernet PROM CRC error.\n");
1140 return -ENXIO;
1141 } else {
1142 skb_queue_head_init(&lp->cache.queue);
1143 lp->cache.gepc = GEP_INIT;
1144 lp->asBit = GEP_SLNK;
1145 lp->asPolarity = GEP_SLNK;
1146 lp->asBitValid = ~0;
1147 lp->timeout = -1;
1148 lp->gendev = gendev;
1149 spin_lock_init(&lp->lock);
1150 init_timer(&lp->timer);
1151 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1152 lp->timer.data = (unsigned long)dev;
1153 de4x5_parse_params(dev);
1154
1155 /*
1156 ** Choose correct autosensing in case someone messed up
1157 */
1158 lp->autosense = lp->params.autosense;
1159 if (lp->chipset != DC21140) {
1160 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1161 lp->params.autosense = TP;
1162 }
1163 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1164 lp->params.autosense = BNC;
1165 }
1166 }
1167 lp->fdx = lp->params.fdx;
1168 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1169
1170 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1171 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1172 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1173 #endif
1174 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1175 &lp->dma_rings, GFP_ATOMIC);
1176 if (lp->rx_ring == NULL) {
1177 return -ENOMEM;
1178 }
1179
1180 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1181
1182 /*
1183 ** Set up the RX descriptor ring (Intels)
1184 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1185 */
1186 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1187 for (i=0; i<NUM_RX_DESC; i++) {
1188 lp->rx_ring[i].status = 0;
1189 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1190 lp->rx_ring[i].buf = 0;
1191 lp->rx_ring[i].next = 0;
1192 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1193 }
1194
1195 #else
1196 {
1197 dma_addr_t dma_rx_bufs;
1198
1199 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1200 * sizeof(struct de4x5_desc);
1201 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1202 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1203 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1204 for (i=0; i<NUM_RX_DESC; i++) {
1205 lp->rx_ring[i].status = 0;
1206 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1207 lp->rx_ring[i].buf =
1208 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1209 lp->rx_ring[i].next = 0;
1210 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1211 }
1212
1213 }
1214 #endif
1215
1216 barrier();
1217
1218 lp->rxRingSize = NUM_RX_DESC;
1219 lp->txRingSize = NUM_TX_DESC;
1220
1221 /* Write the end of list marker to the descriptor lists */
1222 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1223 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1224
1225 /* Tell the adapter where the TX/RX rings are located. */
1226 outl(lp->dma_rings, DE4X5_RRBA);
1227 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1228 DE4X5_TRBA);
1229
1230 /* Initialise the IRQ mask and Enable/Disable */
1231 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1232 lp->irq_en = IMR_NIM | IMR_AIM;
1233
1234 /* Create a loopback packet frame for later media probing */
1235 create_packet(dev, lp->frame, sizeof(lp->frame));
1236
1237 /* Check if the RX overflow bug needs testing for */
1238 i = lp->cfrv & 0x000000fe;
1239 if ((lp->chipset == DC21140) && (i == 0x20)) {
1240 lp->rx_ovf = 1;
1241 }
1242
1243 /* Initialise the SROM pointers if possible */
1244 if (lp->useSROM) {
1245 lp->state = INITIALISED;
1246 if (srom_infoleaf_info(dev)) {
1247 dma_free_coherent (gendev, lp->dma_size,
1248 lp->rx_ring, lp->dma_rings);
1249 return -ENXIO;
1250 }
1251 srom_init(dev);
1252 }
1253
1254 lp->state = CLOSED;
1255
1256 /*
1257 ** Check for an MII interface
1258 */
1259 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1260 mii_get_phy(dev);
1261 }
1262
1263 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1264 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1265 }
1266
1267 if (de4x5_debug & DEBUG_VERSION) {
1268 printk(version);
1269 }
1270
1271 /* The DE4X5-specific entries in the device structure. */
1272 SET_NETDEV_DEV(dev, gendev);
1273 dev->netdev_ops = &de4x5_netdev_ops;
1274 dev->mem_start = 0;
1275
1276 /* Fill in the generic fields of the device structure. */
1277 if ((status = register_netdev (dev))) {
1278 dma_free_coherent (gendev, lp->dma_size,
1279 lp->rx_ring, lp->dma_rings);
1280 return status;
1281 }
1282
1283 /* Let the adapter sleep to save power */
1284 yawn(dev, SLEEP);
1285
1286 return status;
1287 }
1288
1289
1290 static int
1291 de4x5_open(struct net_device *dev)
1292 {
1293 struct de4x5_private *lp = netdev_priv(dev);
1294 u_long iobase = dev->base_addr;
1295 int i, status = 0;
1296 s32 omr;
1297
1298 /* Allocate the RX buffers */
1299 for (i=0; i<lp->rxRingSize; i++) {
1300 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1301 de4x5_free_rx_buffs(dev);
1302 return -EAGAIN;
1303 }
1304 }
1305
1306 /*
1307 ** Wake up the adapter
1308 */
1309 yawn(dev, WAKEUP);
1310
1311 /*
1312 ** Re-initialize the DE4X5...
1313 */
1314 status = de4x5_init(dev);
1315 spin_lock_init(&lp->lock);
1316 lp->state = OPEN;
1317 de4x5_dbg_open(dev);
1318
1319 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1320 lp->adapter_name, dev)) {
1321 printk("de4x5_open(): Requested IRQ%d is busy - attempting FAST/SHARE...", dev->irq);
1322 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1323 lp->adapter_name, dev)) {
1324 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1325 disable_ast(dev);
1326 de4x5_free_rx_buffs(dev);
1327 de4x5_free_tx_buffs(dev);
1328 yawn(dev, SLEEP);
1329 lp->state = CLOSED;
1330 return -EAGAIN;
1331 } else {
1332 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1333 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1334 }
1335 }
1336
1337 lp->interrupt = UNMASK_INTERRUPTS;
1338 netif_trans_update(dev); /* prevent tx timeout */
1339
1340 START_DE4X5;
1341
1342 de4x5_setup_intr(dev);
1343
1344 if (de4x5_debug & DEBUG_OPEN) {
1345 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1346 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1347 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1348 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1349 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1350 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1351 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1352 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1353 }
1354
1355 return status;
1356 }
1357
1358 /*
1359 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1360 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1361 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1362 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1363 ** to be data corruption problems if it is larger (UDP errors seen from a
1364 ** ttcp source).
1365 */
1366 static int
1367 de4x5_init(struct net_device *dev)
1368 {
1369 /* Lock out other processes whilst setting up the hardware */
1370 netif_stop_queue(dev);
1371
1372 de4x5_sw_reset(dev);
1373
1374 /* Autoconfigure the connected port */
1375 autoconf_media(dev);
1376
1377 return 0;
1378 }
1379
1380 static int
1381 de4x5_sw_reset(struct net_device *dev)
1382 {
1383 struct de4x5_private *lp = netdev_priv(dev);
1384 u_long iobase = dev->base_addr;
1385 int i, j, status = 0;
1386 s32 bmr, omr;
1387
1388 /* Select the MII or SRL port now and RESET the MAC */
1389 if (!lp->useSROM) {
1390 if (lp->phy[lp->active].id != 0) {
1391 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1392 } else {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1394 }
1395 de4x5_switch_mac_port(dev);
1396 }
1397
1398 /*
1399 ** Set the programmable burst length to 8 longwords for all the DC21140
1400 ** Fasternet chips and 4 longwords for all others: DMA errors result
1401 ** without these values. Cache align 16 long.
1402 */
1403 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1404 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1405 outl(bmr, DE4X5_BMR);
1406
1407 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1408 if (lp->chipset == DC21140) {
1409 omr |= (OMR_SDP | OMR_SB);
1410 }
1411 lp->setup_f = PERFECT;
1412 outl(lp->dma_rings, DE4X5_RRBA);
1413 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1414 DE4X5_TRBA);
1415
1416 lp->rx_new = lp->rx_old = 0;
1417 lp->tx_new = lp->tx_old = 0;
1418
1419 for (i = 0; i < lp->rxRingSize; i++) {
1420 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1421 }
1422
1423 for (i = 0; i < lp->txRingSize; i++) {
1424 lp->tx_ring[i].status = cpu_to_le32(0);
1425 }
1426
1427 barrier();
1428
1429 /* Build the setup frame depending on filtering mode */
1430 SetMulticastFilter(dev);
1431
1432 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1433 outl(omr|OMR_ST, DE4X5_OMR);
1434
1435 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1436
1437 for (j=0, i=0;(i<500) && (j==0);i++) { /* Up to 500ms delay */
1438 mdelay(1);
1439 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1440 }
1441 outl(omr, DE4X5_OMR); /* Stop everything! */
1442
1443 if (j == 0) {
1444 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1445 inl(DE4X5_STS));
1446 status = -EIO;
1447 }
1448
1449 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1450 lp->tx_old = lp->tx_new;
1451
1452 return status;
1453 }
1454
1455 /*
1456 ** Writes a socket buffer address to the next available transmit descriptor.
1457 */
1458 static netdev_tx_t
1459 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1460 {
1461 struct de4x5_private *lp = netdev_priv(dev);
1462 u_long iobase = dev->base_addr;
1463 u_long flags = 0;
1464
1465 netif_stop_queue(dev);
1466 if (!lp->tx_enable) /* Cannot send for now */
1467 goto tx_err;
1468
1469 /*
1470 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1471 ** interrupts are lost by delayed descriptor status updates relative to
1472 ** the irq assertion, especially with a busy PCI bus.
1473 */
1474 spin_lock_irqsave(&lp->lock, flags);
1475 de4x5_tx(dev);
1476 spin_unlock_irqrestore(&lp->lock, flags);
1477
1478 /* Test if cache is already locked - requeue skb if so */
1479 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1480 goto tx_err;
1481
1482 /* Transmit descriptor ring full or stale skb */
1483 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1484 if (lp->interrupt) {
1485 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1486 } else {
1487 de4x5_put_cache(dev, skb);
1488 }
1489 if (de4x5_debug & DEBUG_TX) {
1490 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1491 }
1492 } else if (skb->len > 0) {
1493 /* If we already have stuff queued locally, use that first */
1494 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1495 de4x5_put_cache(dev, skb);
1496 skb = de4x5_get_cache(dev);
1497 }
1498
1499 while (skb && !netif_queue_stopped(dev) &&
1500 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1501 spin_lock_irqsave(&lp->lock, flags);
1502 netif_stop_queue(dev);
1503 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1504 lp->stats.tx_bytes += skb->len;
1505 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1506
1507 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1508
1509 if (TX_BUFFS_AVAIL) {
1510 netif_start_queue(dev); /* Another pkt may be queued */
1511 }
1512 skb = de4x5_get_cache(dev);
1513 spin_unlock_irqrestore(&lp->lock, flags);
1514 }
1515 if (skb) de4x5_putb_cache(dev, skb);
1516 }
1517
1518 lp->cache.lock = 0;
1519
1520 return NETDEV_TX_OK;
1521 tx_err:
1522 dev_kfree_skb_any(skb);
1523 return NETDEV_TX_OK;
1524 }
1525
1526 /*
1527 ** The DE4X5 interrupt handler.
1528 **
1529 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1530 ** so that the asserted interrupt always has some real data to work with -
1531 ** if these I/O accesses are ever changed to memory accesses, ensure the
1532 ** STS write is read immediately to complete the transaction if the adapter
1533 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1534 ** is high and descriptor status bits cannot be set before the associated
1535 ** interrupt is asserted and this routine entered.
1536 */
1537 static irqreturn_t
1538 de4x5_interrupt(int irq, void *dev_id)
1539 {
1540 struct net_device *dev = dev_id;
1541 struct de4x5_private *lp;
1542 s32 imr, omr, sts, limit;
1543 u_long iobase;
1544 unsigned int handled = 0;
1545
1546 lp = netdev_priv(dev);
1547 spin_lock(&lp->lock);
1548 iobase = dev->base_addr;
1549
1550 DISABLE_IRQs; /* Ensure non re-entrancy */
1551
1552 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1553 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1554
1555 synchronize_irq(dev->irq);
1556
1557 for (limit=0; limit<8; limit++) {
1558 sts = inl(DE4X5_STS); /* Read IRQ status */
1559 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1560
1561 if (!(sts & lp->irq_mask)) break;/* All done */
1562 handled = 1;
1563
1564 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1565 de4x5_rx(dev);
1566
1567 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1568 de4x5_tx(dev);
1569
1570 if (sts & STS_LNF) { /* TP Link has failed */
1571 lp->irq_mask &= ~IMR_LFM;
1572 }
1573
1574 if (sts & STS_UNF) { /* Transmit underrun */
1575 de4x5_txur(dev);
1576 }
1577
1578 if (sts & STS_SE) { /* Bus Error */
1579 STOP_DE4X5;
1580 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1581 dev->name, sts);
1582 spin_unlock(&lp->lock);
1583 return IRQ_HANDLED;
1584 }
1585 }
1586
1587 /* Load the TX ring with any locally stored packets */
1588 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1589 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1590 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1591 }
1592 lp->cache.lock = 0;
1593 }
1594
1595 lp->interrupt = UNMASK_INTERRUPTS;
1596 ENABLE_IRQs;
1597 spin_unlock(&lp->lock);
1598
1599 return IRQ_RETVAL(handled);
1600 }
1601
1602 static int
1603 de4x5_rx(struct net_device *dev)
1604 {
1605 struct de4x5_private *lp = netdev_priv(dev);
1606 u_long iobase = dev->base_addr;
1607 int entry;
1608 s32 status;
1609
1610 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1611 entry=lp->rx_new) {
1612 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1613
1614 if (lp->rx_ovf) {
1615 if (inl(DE4X5_MFC) & MFC_FOCM) {
1616 de4x5_rx_ovfc(dev);
1617 break;
1618 }
1619 }
1620
1621 if (status & RD_FS) { /* Remember the start of frame */
1622 lp->rx_old = entry;
1623 }
1624
1625 if (status & RD_LS) { /* Valid frame status */
1626 if (lp->tx_enable) lp->linkOK++;
1627 if (status & RD_ES) { /* There was an error. */
1628 lp->stats.rx_errors++; /* Update the error stats. */
1629 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1630 if (status & RD_CE) lp->stats.rx_crc_errors++;
1631 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1632 if (status & RD_TL) lp->stats.rx_length_errors++;
1633 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1634 if (status & RD_CS) lp->pktStats.rx_collision++;
1635 if (status & RD_DB) lp->pktStats.rx_dribble++;
1636 if (status & RD_OF) lp->pktStats.rx_overflow++;
1637 } else { /* A valid frame received */
1638 struct sk_buff *skb;
1639 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1640 >> 16) - 4;
1641
1642 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1643 printk("%s: Insufficient memory; nuking packet.\n",
1644 dev->name);
1645 lp->stats.rx_dropped++;
1646 } else {
1647 de4x5_dbg_rx(skb, pkt_len);
1648
1649 /* Push up the protocol stack */
1650 skb->protocol=eth_type_trans(skb,dev);
1651 de4x5_local_stats(dev, skb->data, pkt_len);
1652 netif_rx(skb);
1653
1654 /* Update stats */
1655 lp->stats.rx_packets++;
1656 lp->stats.rx_bytes += pkt_len;
1657 }
1658 }
1659
1660 /* Change buffer ownership for this frame, back to the adapter */
1661 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1662 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1663 barrier();
1664 }
1665 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1666 barrier();
1667 }
1668
1669 /*
1670 ** Update entry information
1671 */
1672 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1673 }
1674
1675 return 0;
1676 }
1677
1678 static inline void
1679 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680 {
1681 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1682 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683 DMA_TO_DEVICE);
1684 if ((u_long) lp->tx_skb[entry] > 1)
1685 dev_kfree_skb_irq(lp->tx_skb[entry]);
1686 lp->tx_skb[entry] = NULL;
1687 }
1688
1689 /*
1690 ** Buffer sent - check for TX buffer errors.
1691 */
1692 static int
1693 de4x5_tx(struct net_device *dev)
1694 {
1695 struct de4x5_private *lp = netdev_priv(dev);
1696 u_long iobase = dev->base_addr;
1697 int entry;
1698 s32 status;
1699
1700 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1701 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1702 if (status < 0) { /* Buffer not sent yet */
1703 break;
1704 } else if (status != 0x7fffffff) { /* Not setup frame */
1705 if (status & TD_ES) { /* An error happened */
1706 lp->stats.tx_errors++;
1707 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1708 if (status & TD_LC) lp->stats.tx_window_errors++;
1709 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1710 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1711 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1712
1713 if (TX_PKT_PENDING) {
1714 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1715 }
1716 } else { /* Packet sent */
1717 lp->stats.tx_packets++;
1718 if (lp->tx_enable) lp->linkOK++;
1719 }
1720 /* Update the collision counter */
1721 lp->stats.collisions += ((status & TD_EC) ? 16 :
1722 ((status & TD_CC) >> 3));
1723
1724 /* Free the buffer. */
1725 if (lp->tx_skb[entry] != NULL)
1726 de4x5_free_tx_buff(lp, entry);
1727 }
1728
1729 /* Update all the pointers */
1730 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1731 }
1732
1733 /* Any resources available? */
1734 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1735 if (lp->interrupt)
1736 netif_wake_queue(dev);
1737 else
1738 netif_start_queue(dev);
1739 }
1740
1741 return 0;
1742 }
1743
1744 static void
1745 de4x5_ast(struct net_device *dev)
1746 {
1747 struct de4x5_private *lp = netdev_priv(dev);
1748 int next_tick = DE4X5_AUTOSENSE_MS;
1749 int dt;
1750
1751 if (lp->useSROM)
1752 next_tick = srom_autoconf(dev);
1753 else if (lp->chipset == DC21140)
1754 next_tick = dc21140m_autoconf(dev);
1755 else if (lp->chipset == DC21041)
1756 next_tick = dc21041_autoconf(dev);
1757 else if (lp->chipset == DC21040)
1758 next_tick = dc21040_autoconf(dev);
1759 lp->linkOK = 0;
1760
1761 dt = (next_tick * HZ) / 1000;
1762
1763 if (!dt)
1764 dt = 1;
1765
1766 mod_timer(&lp->timer, jiffies + dt);
1767 }
1768
1769 static int
1770 de4x5_txur(struct net_device *dev)
1771 {
1772 struct de4x5_private *lp = netdev_priv(dev);
1773 u_long iobase = dev->base_addr;
1774 int omr;
1775
1776 omr = inl(DE4X5_OMR);
1777 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1778 omr &= ~(OMR_ST|OMR_SR);
1779 outl(omr, DE4X5_OMR);
1780 while (inl(DE4X5_STS) & STS_TS);
1781 if ((omr & OMR_TR) < OMR_TR) {
1782 omr += 0x4000;
1783 } else {
1784 omr |= OMR_SF;
1785 }
1786 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1787 }
1788
1789 return 0;
1790 }
1791
1792 static int
1793 de4x5_rx_ovfc(struct net_device *dev)
1794 {
1795 struct de4x5_private *lp = netdev_priv(dev);
1796 u_long iobase = dev->base_addr;
1797 int omr;
1798
1799 omr = inl(DE4X5_OMR);
1800 outl(omr & ~OMR_SR, DE4X5_OMR);
1801 while (inl(DE4X5_STS) & STS_RS);
1802
1803 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1804 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1805 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1806 }
1807
1808 outl(omr, DE4X5_OMR);
1809
1810 return 0;
1811 }
1812
1813 static int
1814 de4x5_close(struct net_device *dev)
1815 {
1816 struct de4x5_private *lp = netdev_priv(dev);
1817 u_long iobase = dev->base_addr;
1818 s32 imr, omr;
1819
1820 disable_ast(dev);
1821
1822 netif_stop_queue(dev);
1823
1824 if (de4x5_debug & DEBUG_CLOSE) {
1825 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1826 dev->name, inl(DE4X5_STS));
1827 }
1828
1829 /*
1830 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1831 */
1832 DISABLE_IRQs;
1833 STOP_DE4X5;
1834
1835 /* Free the associated irq */
1836 free_irq(dev->irq, dev);
1837 lp->state = CLOSED;
1838
1839 /* Free any socket buffers */
1840 de4x5_free_rx_buffs(dev);
1841 de4x5_free_tx_buffs(dev);
1842
1843 /* Put the adapter to sleep to save power */
1844 yawn(dev, SLEEP);
1845
1846 return 0;
1847 }
1848
1849 static struct net_device_stats *
1850 de4x5_get_stats(struct net_device *dev)
1851 {
1852 struct de4x5_private *lp = netdev_priv(dev);
1853 u_long iobase = dev->base_addr;
1854
1855 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1856
1857 return &lp->stats;
1858 }
1859
1860 static void
1861 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1862 {
1863 struct de4x5_private *lp = netdev_priv(dev);
1864 int i;
1865
1866 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1867 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1868 lp->pktStats.bins[i]++;
1869 i = DE4X5_PKT_STAT_SZ;
1870 }
1871 }
1872 if (is_multicast_ether_addr(buf)) {
1873 if (is_broadcast_ether_addr(buf)) {
1874 lp->pktStats.broadcast++;
1875 } else {
1876 lp->pktStats.multicast++;
1877 }
1878 } else if (ether_addr_equal(buf, dev->dev_addr)) {
1879 lp->pktStats.unicast++;
1880 }
1881
1882 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1883 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1884 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1885 }
1886 }
1887
1888 /*
1889 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1890 ** If the flag is changed on a descriptor that is being read by the hardware,
1891 ** I assume PCI transaction ordering will mean you are either successful or
1892 ** just miss asserting the change to the hardware. Anyway you're messing with
1893 ** a descriptor you don't own, but this shouldn't kill the chip provided
1894 ** the descriptor register is read only to the hardware.
1895 */
1896 static void
1897 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1898 {
1899 struct de4x5_private *lp = netdev_priv(dev);
1900 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1901 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1902
1903 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1904 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1905 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1906 lp->tx_skb[lp->tx_new] = skb;
1907 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1908 barrier();
1909
1910 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1911 barrier();
1912 }
1913
1914 /*
1915 ** Set or clear the multicast filter for this adaptor.
1916 */
1917 static void
1918 set_multicast_list(struct net_device *dev)
1919 {
1920 struct de4x5_private *lp = netdev_priv(dev);
1921 u_long iobase = dev->base_addr;
1922
1923 /* First, double check that the adapter is open */
1924 if (lp->state == OPEN) {
1925 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1926 u32 omr;
1927 omr = inl(DE4X5_OMR);
1928 omr |= OMR_PR;
1929 outl(omr, DE4X5_OMR);
1930 } else {
1931 SetMulticastFilter(dev);
1932 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1933 SETUP_FRAME_LEN, (struct sk_buff *)1);
1934
1935 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1936 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1937 netif_trans_update(dev); /* prevent tx timeout */
1938 }
1939 }
1940 }
1941
1942 /*
1943 ** Calculate the hash code and update the logical address filter
1944 ** from a list of ethernet multicast addresses.
1945 ** Little endian crc one liner from Matt Thomas, DEC.
1946 */
1947 static void
1948 SetMulticastFilter(struct net_device *dev)
1949 {
1950 struct de4x5_private *lp = netdev_priv(dev);
1951 struct netdev_hw_addr *ha;
1952 u_long iobase = dev->base_addr;
1953 int i, bit, byte;
1954 u16 hashcode;
1955 u32 omr, crc;
1956 char *pa;
1957 unsigned char *addrs;
1958
1959 omr = inl(DE4X5_OMR);
1960 omr &= ~(OMR_PR | OMR_PM);
1961 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1962
1963 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1964 omr |= OMR_PM; /* Pass all multicasts */
1965 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1966 netdev_for_each_mc_addr(ha, dev) {
1967 crc = ether_crc_le(ETH_ALEN, ha->addr);
1968 hashcode = crc & DE4X5_HASH_BITS; /* hashcode is 9 LSb of CRC */
1969
1970 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1971 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1972
1973 byte <<= 1; /* calc offset into setup frame */
1974 if (byte & 0x02) {
1975 byte -= 1;
1976 }
1977 lp->setup_frame[byte] |= bit;
1978 }
1979 } else { /* Perfect filtering */
1980 netdev_for_each_mc_addr(ha, dev) {
1981 addrs = ha->addr;
1982 for (i=0; i<ETH_ALEN; i++) {
1983 *(pa + (i&1)) = *addrs++;
1984 if (i & 0x01) pa += 4;
1985 }
1986 }
1987 }
1988 outl(omr, DE4X5_OMR);
1989 }
1990
1991 #ifdef CONFIG_EISA
1992
1993 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1994
1995 static int de4x5_eisa_probe(struct device *gendev)
1996 {
1997 struct eisa_device *edev;
1998 u_long iobase;
1999 u_char irq, regval;
2000 u_short vendor;
2001 u32 cfid;
2002 int status, device;
2003 struct net_device *dev;
2004 struct de4x5_private *lp;
2005
2006 edev = to_eisa_device (gendev);
2007 iobase = edev->base_addr;
2008
2009 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2010 return -EBUSY;
2011
2012 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2013 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2014 status = -EBUSY;
2015 goto release_reg_1;
2016 }
2017
2018 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2019 status = -ENOMEM;
2020 goto release_reg_2;
2021 }
2022 lp = netdev_priv(dev);
2023
2024 cfid = (u32) inl(PCI_CFID);
2025 lp->cfrv = (u_short) inl(PCI_CFRV);
2026 device = (cfid >> 8) & 0x00ffff00;
2027 vendor = (u_short) cfid;
2028
2029 /* Read the EISA Configuration Registers */
2030 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2031 #ifdef CONFIG_ALPHA
2032 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2033 * care about the EISA configuration, and thus doesn't
2034 * configure the PLX bridge properly. Oh well... Simply mimic
2035 * the EISA config file to sort it out. */
2036
2037 /* EISA REG1: Assert DecChip 21040 HW Reset */
2038 outb (ER1_IAM | 1, EISA_REG1);
2039 mdelay (1);
2040
2041 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2042 outb (ER1_IAM, EISA_REG1);
2043 mdelay (1);
2044
2045 /* EISA REG3: R/W Burst Transfer Enable */
2046 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2047
2048 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2049 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2050 #endif
2051 irq = de4x5_irq[(regval >> 1) & 0x03];
2052
2053 if (is_DC2114x) {
2054 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2055 }
2056 lp->chipset = device;
2057 lp->bus = EISA;
2058
2059 /* Write the PCI Configuration Registers */
2060 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2061 outl(0x00006000, PCI_CFLT);
2062 outl(iobase, PCI_CBIO);
2063
2064 DevicePresent(dev, EISA_APROM);
2065
2066 dev->irq = irq;
2067
2068 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2069 return 0;
2070 }
2071
2072 free_netdev (dev);
2073 release_reg_2:
2074 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2075 release_reg_1:
2076 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2077
2078 return status;
2079 }
2080
2081 static int de4x5_eisa_remove(struct device *device)
2082 {
2083 struct net_device *dev;
2084 u_long iobase;
2085
2086 dev = dev_get_drvdata(device);
2087 iobase = dev->base_addr;
2088
2089 unregister_netdev (dev);
2090 free_netdev (dev);
2091 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2092 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2093
2094 return 0;
2095 }
2096
2097 static struct eisa_device_id de4x5_eisa_ids[] = {
2098 { "DEC4250", 0 }, /* 0 is the board name index... */
2099 { "" }
2100 };
2101 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2102
2103 static struct eisa_driver de4x5_eisa_driver = {
2104 .id_table = de4x5_eisa_ids,
2105 .driver = {
2106 .name = "de4x5",
2107 .probe = de4x5_eisa_probe,
2108 .remove = de4x5_eisa_remove,
2109 }
2110 };
2111 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2112 #endif
2113
2114 #ifdef CONFIG_PCI
2115
2116 /*
2117 ** This function searches the current bus (which is >0) for a DECchip with an
2118 ** SROM, so that in multiport cards that have one SROM shared between multiple
2119 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2120 ** For single port cards this is a time waster...
2121 */
2122 static void
2123 srom_search(struct net_device *dev, struct pci_dev *pdev)
2124 {
2125 u_char pb;
2126 u_short vendor, status;
2127 u_int irq = 0, device;
2128 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2129 int i, j;
2130 struct de4x5_private *lp = netdev_priv(dev);
2131 struct pci_dev *this_dev;
2132
2133 list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) {
2134 vendor = this_dev->vendor;
2135 device = this_dev->device << 8;
2136 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2137
2138 /* Get the chip configuration revision register */
2139 pb = this_dev->bus->number;
2140
2141 /* Set the device number information */
2142 lp->device = PCI_SLOT(this_dev->devfn);
2143 lp->bus_num = pb;
2144
2145 /* Set the chipset information */
2146 if (is_DC2114x) {
2147 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2148 ? DC21142 : DC21143);
2149 }
2150 lp->chipset = device;
2151
2152 /* Get the board I/O address (64 bits on sparc64) */
2153 iobase = pci_resource_start(this_dev, 0);
2154
2155 /* Fetch the IRQ to be used */
2156 irq = this_dev->irq;
2157 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2158
2159 /* Check if I/O accesses are enabled */
2160 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2161 if (!(status & PCI_COMMAND_IO)) continue;
2162
2163 /* Search for a valid SROM attached to this DECchip */
2164 DevicePresent(dev, DE4X5_APROM);
2165 for (j=0, i=0; i<ETH_ALEN; i++) {
2166 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2167 }
2168 if (j != 0 && j != 6 * 0xff) {
2169 last.chipset = device;
2170 last.bus = pb;
2171 last.irq = irq;
2172 for (i=0; i<ETH_ALEN; i++) {
2173 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2174 }
2175 return;
2176 }
2177 }
2178 }
2179
2180 /*
2181 ** PCI bus I/O device probe
2182 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2183 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2184 ** enabled by the user first in the set up utility. Hence we just check for
2185 ** enabled features and silently ignore the card if they're not.
2186 **
2187 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2188 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2189 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2190 ** PC doesn't conform to the PCI standard)!
2191 **
2192 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2193 ** kernels use the V0.535[n] drivers.
2194 */
2195
2196 static int de4x5_pci_probe(struct pci_dev *pdev,
2197 const struct pci_device_id *ent)
2198 {
2199 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2200 u_short vendor, status;
2201 u_int irq = 0, device;
2202 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2203 int error;
2204 struct net_device *dev;
2205 struct de4x5_private *lp;
2206
2207 dev_num = PCI_SLOT(pdev->devfn);
2208 pb = pdev->bus->number;
2209
2210 if (io) { /* probe a single PCI device */
2211 pbus = (u_short)(io >> 8);
2212 dnum = (u_short)(io & 0xff);
2213 if ((pbus != pb) || (dnum != dev_num))
2214 return -ENODEV;
2215 }
2216
2217 vendor = pdev->vendor;
2218 device = pdev->device << 8;
2219 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2220 return -ENODEV;
2221
2222 /* Ok, the device seems to be for us. */
2223 if ((error = pci_enable_device (pdev)))
2224 return error;
2225
2226 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2227 error = -ENOMEM;
2228 goto disable_dev;
2229 }
2230
2231 lp = netdev_priv(dev);
2232 lp->bus = PCI;
2233 lp->bus_num = 0;
2234
2235 /* Search for an SROM on this bus */
2236 if (lp->bus_num != pb) {
2237 lp->bus_num = pb;
2238 srom_search(dev, pdev);
2239 }
2240
2241 /* Get the chip configuration revision register */
2242 lp->cfrv = pdev->revision;
2243
2244 /* Set the device number information */
2245 lp->device = dev_num;
2246 lp->bus_num = pb;
2247
2248 /* Set the chipset information */
2249 if (is_DC2114x) {
2250 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2251 }
2252 lp->chipset = device;
2253
2254 /* Get the board I/O address (64 bits on sparc64) */
2255 iobase = pci_resource_start(pdev, 0);
2256
2257 /* Fetch the IRQ to be used */
2258 irq = pdev->irq;
2259 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2260 error = -ENODEV;
2261 goto free_dev;
2262 }
2263
2264 /* Check if I/O accesses and Bus Mastering are enabled */
2265 pci_read_config_word(pdev, PCI_COMMAND, &status);
2266 #ifdef __powerpc__
2267 if (!(status & PCI_COMMAND_IO)) {
2268 status |= PCI_COMMAND_IO;
2269 pci_write_config_word(pdev, PCI_COMMAND, status);
2270 pci_read_config_word(pdev, PCI_COMMAND, &status);
2271 }
2272 #endif /* __powerpc__ */
2273 if (!(status & PCI_COMMAND_IO)) {
2274 error = -ENODEV;
2275 goto free_dev;
2276 }
2277
2278 if (!(status & PCI_COMMAND_MASTER)) {
2279 status |= PCI_COMMAND_MASTER;
2280 pci_write_config_word(pdev, PCI_COMMAND, status);
2281 pci_read_config_word(pdev, PCI_COMMAND, &status);
2282 }
2283 if (!(status & PCI_COMMAND_MASTER)) {
2284 error = -ENODEV;
2285 goto free_dev;
2286 }
2287
2288 /* Check the latency timer for values >= 0x60 */
2289 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2290 if (timer < 0x60) {
2291 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2292 }
2293
2294 DevicePresent(dev, DE4X5_APROM);
2295
2296 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2297 error = -EBUSY;
2298 goto free_dev;
2299 }
2300
2301 dev->irq = irq;
2302
2303 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2304 goto release;
2305 }
2306
2307 return 0;
2308
2309 release:
2310 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2311 free_dev:
2312 free_netdev (dev);
2313 disable_dev:
2314 pci_disable_device (pdev);
2315 return error;
2316 }
2317
2318 static void de4x5_pci_remove(struct pci_dev *pdev)
2319 {
2320 struct net_device *dev;
2321 u_long iobase;
2322
2323 dev = pci_get_drvdata(pdev);
2324 iobase = dev->base_addr;
2325
2326 unregister_netdev (dev);
2327 free_netdev (dev);
2328 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2329 pci_disable_device (pdev);
2330 }
2331
2332 static const struct pci_device_id de4x5_pci_tbl[] = {
2333 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2335 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2337 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2339 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2341 { },
2342 };
2343
2344 static struct pci_driver de4x5_pci_driver = {
2345 .name = "de4x5",
2346 .id_table = de4x5_pci_tbl,
2347 .probe = de4x5_pci_probe,
2348 .remove = de4x5_pci_remove,
2349 };
2350
2351 #endif
2352
2353 /*
2354 ** Auto configure the media here rather than setting the port at compile
2355 ** time. This routine is called by de4x5_init() and when a loss of media is
2356 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2357 ** [TP] or no recent receive activity) to check whether the user has been
2358 ** sneaky and changed the port on us.
2359 */
2360 static int
2361 autoconf_media(struct net_device *dev)
2362 {
2363 struct de4x5_private *lp = netdev_priv(dev);
2364 u_long iobase = dev->base_addr;
2365
2366 disable_ast(dev);
2367
2368 lp->c_media = AUTO; /* Bogus last media */
2369 inl(DE4X5_MFC); /* Zero the lost frames counter */
2370 lp->media = INIT;
2371 lp->tcount = 0;
2372
2373 de4x5_ast(dev);
2374
2375 return lp->media;
2376 }
2377
2378 /*
2379 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2380 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2381 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2382 ** The only way to test for that is to place a loopback packet onto the
2383 ** network and watch for errors. Since we're messing with the interrupt mask
2384 ** register, disable the board interrupts and do not allow any more packets to
2385 ** be queued to the hardware. Re-enable everything only when the media is
2386 ** found.
2387 ** I may have to "age out" locally queued packets so that the higher layer
2388 ** timeouts don't effectively duplicate packets on the network.
2389 */
2390 static int
2391 dc21040_autoconf(struct net_device *dev)
2392 {
2393 struct de4x5_private *lp = netdev_priv(dev);
2394 u_long iobase = dev->base_addr;
2395 int next_tick = DE4X5_AUTOSENSE_MS;
2396 s32 imr;
2397
2398 switch (lp->media) {
2399 case INIT:
2400 DISABLE_IRQs;
2401 lp->tx_enable = false;
2402 lp->timeout = -1;
2403 de4x5_save_skbs(dev);
2404 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2405 lp->media = TP;
2406 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2407 lp->media = BNC_AUI;
2408 } else if (lp->autosense == EXT_SIA) {
2409 lp->media = EXT_SIA;
2410 } else {
2411 lp->media = NC;
2412 }
2413 lp->local_state = 0;
2414 next_tick = dc21040_autoconf(dev);
2415 break;
2416
2417 case TP:
2418 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2419 TP_SUSPECT, test_tp);
2420 break;
2421
2422 case TP_SUSPECT:
2423 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2424 break;
2425
2426 case BNC:
2427 case AUI:
2428 case BNC_AUI:
2429 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2430 BNC_AUI_SUSPECT, ping_media);
2431 break;
2432
2433 case BNC_AUI_SUSPECT:
2434 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2435 break;
2436
2437 case EXT_SIA:
2438 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2439 NC, EXT_SIA_SUSPECT, ping_media);
2440 break;
2441
2442 case EXT_SIA_SUSPECT:
2443 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2444 break;
2445
2446 case NC:
2447 /* default to TP for all */
2448 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2449 if (lp->media != lp->c_media) {
2450 de4x5_dbg_media(dev);
2451 lp->c_media = lp->media;
2452 }
2453 lp->media = INIT;
2454 lp->tx_enable = false;
2455 break;
2456 }
2457
2458 return next_tick;
2459 }
2460
2461 static int
2462 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2463 int next_state, int suspect_state,
2464 int (*fn)(struct net_device *, int))
2465 {
2466 struct de4x5_private *lp = netdev_priv(dev);
2467 int next_tick = DE4X5_AUTOSENSE_MS;
2468 int linkBad;
2469
2470 switch (lp->local_state) {
2471 case 0:
2472 reset_init_sia(dev, csr13, csr14, csr15);
2473 lp->local_state++;
2474 next_tick = 500;
2475 break;
2476
2477 case 1:
2478 if (!lp->tx_enable) {
2479 linkBad = fn(dev, timeout);
2480 if (linkBad < 0) {
2481 next_tick = linkBad & ~TIMER_CB;
2482 } else {
2483 if (linkBad && (lp->autosense == AUTO)) {
2484 lp->local_state = 0;
2485 lp->media = next_state;
2486 } else {
2487 de4x5_init_connection(dev);
2488 }
2489 }
2490 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2491 lp->media = suspect_state;
2492 next_tick = 3000;
2493 }
2494 break;
2495 }
2496
2497 return next_tick;
2498 }
2499
2500 static int
2501 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2502 int (*fn)(struct net_device *, int),
2503 int (*asfn)(struct net_device *))
2504 {
2505 struct de4x5_private *lp = netdev_priv(dev);
2506 int next_tick = DE4X5_AUTOSENSE_MS;
2507 int linkBad;
2508
2509 switch (lp->local_state) {
2510 case 1:
2511 if (lp->linkOK) {
2512 lp->media = prev_state;
2513 } else {
2514 lp->local_state++;
2515 next_tick = asfn(dev);
2516 }
2517 break;
2518
2519 case 2:
2520 linkBad = fn(dev, timeout);
2521 if (linkBad < 0) {
2522 next_tick = linkBad & ~TIMER_CB;
2523 } else if (!linkBad) {
2524 lp->local_state--;
2525 lp->media = prev_state;
2526 } else {
2527 lp->media = INIT;
2528 lp->tcount++;
2529 }
2530 }
2531
2532 return next_tick;
2533 }
2534
2535 /*
2536 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2537 ** before BNC, because the BNC port will indicate activity if it's not
2538 ** terminated correctly. The only way to test for that is to place a loopback
2539 ** packet onto the network and watch for errors. Since we're messing with
2540 ** the interrupt mask register, disable the board interrupts and do not allow
2541 ** any more packets to be queued to the hardware. Re-enable everything only
2542 ** when the media is found.
2543 */
2544 static int
2545 dc21041_autoconf(struct net_device *dev)
2546 {
2547 struct de4x5_private *lp = netdev_priv(dev);
2548 u_long iobase = dev->base_addr;
2549 s32 sts, irqs, irq_mask, imr, omr;
2550 int next_tick = DE4X5_AUTOSENSE_MS;
2551
2552 switch (lp->media) {
2553 case INIT:
2554 DISABLE_IRQs;
2555 lp->tx_enable = false;
2556 lp->timeout = -1;
2557 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2558 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2559 lp->media = TP; /* On chip auto negotiation is broken */
2560 } else if (lp->autosense == TP) {
2561 lp->media = TP;
2562 } else if (lp->autosense == BNC) {
2563 lp->media = BNC;
2564 } else if (lp->autosense == AUI) {
2565 lp->media = AUI;
2566 } else {
2567 lp->media = NC;
2568 }
2569 lp->local_state = 0;
2570 next_tick = dc21041_autoconf(dev);
2571 break;
2572
2573 case TP_NW:
2574 if (lp->timeout < 0) {
2575 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2576 outl(omr | OMR_FDX, DE4X5_OMR);
2577 }
2578 irqs = STS_LNF | STS_LNP;
2579 irq_mask = IMR_LFM | IMR_LPM;
2580 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2581 if (sts < 0) {
2582 next_tick = sts & ~TIMER_CB;
2583 } else {
2584 if (sts & STS_LNP) {
2585 lp->media = ANS;
2586 } else {
2587 lp->media = AUI;
2588 }
2589 next_tick = dc21041_autoconf(dev);
2590 }
2591 break;
2592
2593 case ANS:
2594 if (!lp->tx_enable) {
2595 irqs = STS_LNP;
2596 irq_mask = IMR_LPM;
2597 sts = test_ans(dev, irqs, irq_mask, 3000);
2598 if (sts < 0) {
2599 next_tick = sts & ~TIMER_CB;
2600 } else {
2601 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2602 lp->media = TP;
2603 next_tick = dc21041_autoconf(dev);
2604 } else {
2605 lp->local_state = 1;
2606 de4x5_init_connection(dev);
2607 }
2608 }
2609 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2610 lp->media = ANS_SUSPECT;
2611 next_tick = 3000;
2612 }
2613 break;
2614
2615 case ANS_SUSPECT:
2616 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2617 break;
2618
2619 case TP:
2620 if (!lp->tx_enable) {
2621 if (lp->timeout < 0) {
2622 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2623 outl(omr & ~OMR_FDX, DE4X5_OMR);
2624 }
2625 irqs = STS_LNF | STS_LNP;
2626 irq_mask = IMR_LFM | IMR_LPM;
2627 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2628 if (sts < 0) {
2629 next_tick = sts & ~TIMER_CB;
2630 } else {
2631 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2632 if (inl(DE4X5_SISR) & SISR_NRA) {
2633 lp->media = AUI; /* Non selected port activity */
2634 } else {
2635 lp->media = BNC;
2636 }
2637 next_tick = dc21041_autoconf(dev);
2638 } else {
2639 lp->local_state = 1;
2640 de4x5_init_connection(dev);
2641 }
2642 }
2643 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2644 lp->media = TP_SUSPECT;
2645 next_tick = 3000;
2646 }
2647 break;
2648
2649 case TP_SUSPECT:
2650 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2651 break;
2652
2653 case AUI:
2654 if (!lp->tx_enable) {
2655 if (lp->timeout < 0) {
2656 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2657 outl(omr & ~OMR_FDX, DE4X5_OMR);
2658 }
2659 irqs = 0;
2660 irq_mask = 0;
2661 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2662 if (sts < 0) {
2663 next_tick = sts & ~TIMER_CB;
2664 } else {
2665 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2666 lp->media = BNC;
2667 next_tick = dc21041_autoconf(dev);
2668 } else {
2669 lp->local_state = 1;
2670 de4x5_init_connection(dev);
2671 }
2672 }
2673 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2674 lp->media = AUI_SUSPECT;
2675 next_tick = 3000;
2676 }
2677 break;
2678
2679 case AUI_SUSPECT:
2680 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2681 break;
2682
2683 case BNC:
2684 switch (lp->local_state) {
2685 case 0:
2686 if (lp->timeout < 0) {
2687 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2688 outl(omr & ~OMR_FDX, DE4X5_OMR);
2689 }
2690 irqs = 0;
2691 irq_mask = 0;
2692 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2693 if (sts < 0) {
2694 next_tick = sts & ~TIMER_CB;
2695 } else {
2696 lp->local_state++; /* Ensure media connected */
2697 next_tick = dc21041_autoconf(dev);
2698 }
2699 break;
2700
2701 case 1:
2702 if (!lp->tx_enable) {
2703 if ((sts = ping_media(dev, 3000)) < 0) {
2704 next_tick = sts & ~TIMER_CB;
2705 } else {
2706 if (sts) {
2707 lp->local_state = 0;
2708 lp->media = NC;
2709 } else {
2710 de4x5_init_connection(dev);
2711 }
2712 }
2713 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2714 lp->media = BNC_SUSPECT;
2715 next_tick = 3000;
2716 }
2717 break;
2718 }
2719 break;
2720
2721 case BNC_SUSPECT:
2722 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2723 break;
2724
2725 case NC:
2726 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2727 outl(omr | OMR_FDX, DE4X5_OMR);
2728 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2729 if (lp->media != lp->c_media) {
2730 de4x5_dbg_media(dev);
2731 lp->c_media = lp->media;
2732 }
2733 lp->media = INIT;
2734 lp->tx_enable = false;
2735 break;
2736 }
2737
2738 return next_tick;
2739 }
2740
2741 /*
2742 ** Some autonegotiation chips are broken in that they do not return the
2743 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2744 ** register, except at the first power up negotiation.
2745 */
2746 static int
2747 dc21140m_autoconf(struct net_device *dev)
2748 {
2749 struct de4x5_private *lp = netdev_priv(dev);
2750 int ana, anlpa, cap, cr, slnk, sr;
2751 int next_tick = DE4X5_AUTOSENSE_MS;
2752 u_long imr, omr, iobase = dev->base_addr;
2753
2754 switch(lp->media) {
2755 case INIT:
2756 if (lp->timeout < 0) {
2757 DISABLE_IRQs;
2758 lp->tx_enable = false;
2759 lp->linkOK = 0;
2760 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2761 }
2762 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2763 next_tick &= ~TIMER_CB;
2764 } else {
2765 if (lp->useSROM) {
2766 if (srom_map_media(dev) < 0) {
2767 lp->tcount++;
2768 return next_tick;
2769 }
2770 srom_exec(dev, lp->phy[lp->active].gep);
2771 if (lp->infoblock_media == ANS) {
2772 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2773 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2774 }
2775 } else {
2776 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2777 SET_10Mb;
2778 if (lp->autosense == _100Mb) {
2779 lp->media = _100Mb;
2780 } else if (lp->autosense == _10Mb) {
2781 lp->media = _10Mb;
2782 } else if ((lp->autosense == AUTO) &&
2783 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2784 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2785 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2786 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2787 lp->media = ANS;
2788 } else if (lp->autosense == AUTO) {
2789 lp->media = SPD_DET;
2790 } else if (is_spd_100(dev) && is_100_up(dev)) {
2791 lp->media = _100Mb;
2792 } else {
2793 lp->media = NC;
2794 }
2795 }
2796 lp->local_state = 0;
2797 next_tick = dc21140m_autoconf(dev);
2798 }
2799 break;
2800
2801 case ANS:
2802 switch (lp->local_state) {
2803 case 0:
2804 if (lp->timeout < 0) {
2805 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2806 }
2807 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2808 if (cr < 0) {
2809 next_tick = cr & ~TIMER_CB;
2810 } else {
2811 if (cr) {
2812 lp->local_state = 0;
2813 lp->media = SPD_DET;
2814 } else {
2815 lp->local_state++;
2816 }
2817 next_tick = dc21140m_autoconf(dev);
2818 }
2819 break;
2820
2821 case 1:
2822 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2823 next_tick = sr & ~TIMER_CB;
2824 } else {
2825 lp->media = SPD_DET;
2826 lp->local_state = 0;
2827 if (sr) { /* Success! */
2828 lp->tmp = MII_SR_ASSC;
2829 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2830 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2831 if (!(anlpa & MII_ANLPA_RF) &&
2832 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2833 if (cap & MII_ANA_100M) {
2834 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2835 lp->media = _100Mb;
2836 } else if (cap & MII_ANA_10M) {
2837 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2838
2839 lp->media = _10Mb;
2840 }
2841 }
2842 } /* Auto Negotiation failed to finish */
2843 next_tick = dc21140m_autoconf(dev);
2844 } /* Auto Negotiation failed to start */
2845 break;
2846 }
2847 break;
2848
2849 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2850 if (lp->timeout < 0) {
2851 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2852 (~gep_rd(dev) & GEP_LNP));
2853 SET_100Mb_PDET;
2854 }
2855 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2856 next_tick = slnk & ~TIMER_CB;
2857 } else {
2858 if (is_spd_100(dev) && is_100_up(dev)) {
2859 lp->media = _100Mb;
2860 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2861 lp->media = _10Mb;
2862 } else {
2863 lp->media = NC;
2864 }
2865 next_tick = dc21140m_autoconf(dev);
2866 }
2867 break;
2868
2869 case _100Mb: /* Set 100Mb/s */
2870 next_tick = 3000;
2871 if (!lp->tx_enable) {
2872 SET_100Mb;
2873 de4x5_init_connection(dev);
2874 } else {
2875 if (!lp->linkOK && (lp->autosense == AUTO)) {
2876 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2877 lp->media = INIT;
2878 lp->tcount++;
2879 next_tick = DE4X5_AUTOSENSE_MS;
2880 }
2881 }
2882 }
2883 break;
2884
2885 case BNC:
2886 case AUI:
2887 case _10Mb: /* Set 10Mb/s */
2888 next_tick = 3000;
2889 if (!lp->tx_enable) {
2890 SET_10Mb;
2891 de4x5_init_connection(dev);
2892 } else {
2893 if (!lp->linkOK && (lp->autosense == AUTO)) {
2894 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2895 lp->media = INIT;
2896 lp->tcount++;
2897 next_tick = DE4X5_AUTOSENSE_MS;
2898 }
2899 }
2900 }
2901 break;
2902
2903 case NC:
2904 if (lp->media != lp->c_media) {
2905 de4x5_dbg_media(dev);
2906 lp->c_media = lp->media;
2907 }
2908 lp->media = INIT;
2909 lp->tx_enable = false;
2910 break;
2911 }
2912
2913 return next_tick;
2914 }
2915
2916 /*
2917 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2918 ** changing how I figure out the media - but trying to keep it backwards
2919 ** compatible with the de500-xa and de500-aa.
2920 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2921 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2922 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2923 ** active.
2924 ** When autonegotiation is working, the ANS part searches the SROM for
2925 ** the highest common speed (TP) link that both can run and if that can
2926 ** be full duplex. That infoblock is executed and then the link speed set.
2927 **
2928 ** Only _10Mb and _100Mb are tested here.
2929 */
2930 static int
2931 dc2114x_autoconf(struct net_device *dev)
2932 {
2933 struct de4x5_private *lp = netdev_priv(dev);
2934 u_long iobase = dev->base_addr;
2935 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2936 int next_tick = DE4X5_AUTOSENSE_MS;
2937
2938 switch (lp->media) {
2939 case INIT:
2940 if (lp->timeout < 0) {
2941 DISABLE_IRQs;
2942 lp->tx_enable = false;
2943 lp->linkOK = 0;
2944 lp->timeout = -1;
2945 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2946 if (lp->params.autosense & ~AUTO) {
2947 srom_map_media(dev); /* Fixed media requested */
2948 if (lp->media != lp->params.autosense) {
2949 lp->tcount++;
2950 lp->media = INIT;
2951 return next_tick;
2952 }
2953 lp->media = INIT;
2954 }
2955 }
2956 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2957 next_tick &= ~TIMER_CB;
2958 } else {
2959 if (lp->autosense == _100Mb) {
2960 lp->media = _100Mb;
2961 } else if (lp->autosense == _10Mb) {
2962 lp->media = _10Mb;
2963 } else if (lp->autosense == TP) {
2964 lp->media = TP;
2965 } else if (lp->autosense == BNC) {
2966 lp->media = BNC;
2967 } else if (lp->autosense == AUI) {
2968 lp->media = AUI;
2969 } else {
2970 lp->media = SPD_DET;
2971 if ((lp->infoblock_media == ANS) &&
2972 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2973 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2974 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2975 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2976 lp->media = ANS;
2977 }
2978 }
2979 lp->local_state = 0;
2980 next_tick = dc2114x_autoconf(dev);
2981 }
2982 break;
2983
2984 case ANS:
2985 switch (lp->local_state) {
2986 case 0:
2987 if (lp->timeout < 0) {
2988 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2989 }
2990 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2991 if (cr < 0) {
2992 next_tick = cr & ~TIMER_CB;
2993 } else {
2994 if (cr) {
2995 lp->local_state = 0;
2996 lp->media = SPD_DET;
2997 } else {
2998 lp->local_state++;
2999 }
3000 next_tick = dc2114x_autoconf(dev);
3001 }
3002 break;
3003
3004 case 1:
3005 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3006 if (sr < 0) {
3007 next_tick = sr & ~TIMER_CB;
3008 } else {
3009 lp->media = SPD_DET;
3010 lp->local_state = 0;
3011 if (sr) { /* Success! */
3012 lp->tmp = MII_SR_ASSC;
3013 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3014 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3015 if (!(anlpa & MII_ANLPA_RF) &&
3016 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3017 if (cap & MII_ANA_100M) {
3018 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3019 lp->media = _100Mb;
3020 } else if (cap & MII_ANA_10M) {
3021 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3022 lp->media = _10Mb;
3023 }
3024 }
3025 } /* Auto Negotiation failed to finish */
3026 next_tick = dc2114x_autoconf(dev);
3027 } /* Auto Negotiation failed to start */
3028 break;
3029 }
3030 break;
3031
3032 case AUI:
3033 if (!lp->tx_enable) {
3034 if (lp->timeout < 0) {
3035 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3036 outl(omr & ~OMR_FDX, DE4X5_OMR);
3037 }
3038 irqs = 0;
3039 irq_mask = 0;
3040 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3041 if (sts < 0) {
3042 next_tick = sts & ~TIMER_CB;
3043 } else {
3044 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3045 lp->media = BNC;
3046 next_tick = dc2114x_autoconf(dev);
3047 } else {
3048 lp->local_state = 1;
3049 de4x5_init_connection(dev);
3050 }
3051 }
3052 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3053 lp->media = AUI_SUSPECT;
3054 next_tick = 3000;
3055 }
3056 break;
3057
3058 case AUI_SUSPECT:
3059 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3060 break;
3061
3062 case BNC:
3063 switch (lp->local_state) {
3064 case 0:
3065 if (lp->timeout < 0) {
3066 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3067 outl(omr & ~OMR_FDX, DE4X5_OMR);
3068 }
3069 irqs = 0;
3070 irq_mask = 0;
3071 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3072 if (sts < 0) {
3073 next_tick = sts & ~TIMER_CB;
3074 } else {
3075 lp->local_state++; /* Ensure media connected */
3076 next_tick = dc2114x_autoconf(dev);
3077 }
3078 break;
3079
3080 case 1:
3081 if (!lp->tx_enable) {
3082 if ((sts = ping_media(dev, 3000)) < 0) {
3083 next_tick = sts & ~TIMER_CB;
3084 } else {
3085 if (sts) {
3086 lp->local_state = 0;
3087 lp->tcount++;
3088 lp->media = INIT;
3089 } else {
3090 de4x5_init_connection(dev);
3091 }
3092 }
3093 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3094 lp->media = BNC_SUSPECT;
3095 next_tick = 3000;
3096 }
3097 break;
3098 }
3099 break;
3100
3101 case BNC_SUSPECT:
3102 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3103 break;
3104
3105 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3106 if (srom_map_media(dev) < 0) {
3107 lp->tcount++;
3108 lp->media = INIT;
3109 return next_tick;
3110 }
3111 if (lp->media == _100Mb) {
3112 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3113 lp->media = SPD_DET;
3114 return slnk & ~TIMER_CB;
3115 }
3116 } else {
3117 if (wait_for_link(dev) < 0) {
3118 lp->media = SPD_DET;
3119 return PDET_LINK_WAIT;
3120 }
3121 }
3122 if (lp->media == ANS) { /* Do MII parallel detection */
3123 if (is_spd_100(dev)) {
3124 lp->media = _100Mb;
3125 } else {
3126 lp->media = _10Mb;
3127 }
3128 next_tick = dc2114x_autoconf(dev);
3129 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3130 (((lp->media == _10Mb) || (lp->media == TP) ||
3131 (lp->media == BNC) || (lp->media == AUI)) &&
3132 is_10_up(dev))) {
3133 next_tick = dc2114x_autoconf(dev);
3134 } else {
3135 lp->tcount++;
3136 lp->media = INIT;
3137 }
3138 break;
3139
3140 case _10Mb:
3141 next_tick = 3000;
3142 if (!lp->tx_enable) {
3143 SET_10Mb;
3144 de4x5_init_connection(dev);
3145 } else {
3146 if (!lp->linkOK && (lp->autosense == AUTO)) {
3147 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3148 lp->media = INIT;
3149 lp->tcount++;
3150 next_tick = DE4X5_AUTOSENSE_MS;
3151 }
3152 }
3153 }
3154 break;
3155
3156 case _100Mb:
3157 next_tick = 3000;
3158 if (!lp->tx_enable) {
3159 SET_100Mb;
3160 de4x5_init_connection(dev);
3161 } else {
3162 if (!lp->linkOK && (lp->autosense == AUTO)) {
3163 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3164 lp->media = INIT;
3165 lp->tcount++;
3166 next_tick = DE4X5_AUTOSENSE_MS;
3167 }
3168 }
3169 }
3170 break;
3171
3172 default:
3173 lp->tcount++;
3174 printk("Huh?: media:%02x\n", lp->media);
3175 lp->media = INIT;
3176 break;
3177 }
3178
3179 return next_tick;
3180 }
3181
3182 static int
3183 srom_autoconf(struct net_device *dev)
3184 {
3185 struct de4x5_private *lp = netdev_priv(dev);
3186
3187 return lp->infoleaf_fn(dev);
3188 }
3189
3190 /*
3191 ** This mapping keeps the original media codes and FDX flag unchanged.
3192 ** While it isn't strictly necessary, it helps me for the moment...
3193 ** The early return avoids a media state / SROM media space clash.
3194 */
3195 static int
3196 srom_map_media(struct net_device *dev)
3197 {
3198 struct de4x5_private *lp = netdev_priv(dev);
3199
3200 lp->fdx = false;
3201 if (lp->infoblock_media == lp->media)
3202 return 0;
3203
3204 switch(lp->infoblock_media) {
3205 case SROM_10BASETF:
3206 if (!lp->params.fdx) return -1;
3207 lp->fdx = true;
3208 case SROM_10BASET:
3209 if (lp->params.fdx && !lp->fdx) return -1;
3210 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3211 lp->media = _10Mb;
3212 } else {
3213 lp->media = TP;
3214 }
3215 break;
3216
3217 case SROM_10BASE2:
3218 lp->media = BNC;
3219 break;
3220
3221 case SROM_10BASE5:
3222 lp->media = AUI;
3223 break;
3224
3225 case SROM_100BASETF:
3226 if (!lp->params.fdx) return -1;
3227 lp->fdx = true;
3228 case SROM_100BASET:
3229 if (lp->params.fdx && !lp->fdx) return -1;
3230 lp->media = _100Mb;
3231 break;
3232
3233 case SROM_100BASET4:
3234 lp->media = _100Mb;
3235 break;
3236
3237 case SROM_100BASEFF:
3238 if (!lp->params.fdx) return -1;
3239 lp->fdx = true;
3240 case SROM_100BASEF:
3241 if (lp->params.fdx && !lp->fdx) return -1;
3242 lp->media = _100Mb;
3243 break;
3244
3245 case ANS:
3246 lp->media = ANS;
3247 lp->fdx = lp->params.fdx;
3248 break;
3249
3250 default:
3251 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3252 lp->infoblock_media);
3253 return -1;
3254 }
3255
3256 return 0;
3257 }
3258
3259 static void
3260 de4x5_init_connection(struct net_device *dev)
3261 {
3262 struct de4x5_private *lp = netdev_priv(dev);
3263 u_long iobase = dev->base_addr;
3264 u_long flags = 0;
3265
3266 if (lp->media != lp->c_media) {
3267 de4x5_dbg_media(dev);
3268 lp->c_media = lp->media; /* Stop scrolling media messages */
3269 }
3270
3271 spin_lock_irqsave(&lp->lock, flags);
3272 de4x5_rst_desc_ring(dev);
3273 de4x5_setup_intr(dev);
3274 lp->tx_enable = true;
3275 spin_unlock_irqrestore(&lp->lock, flags);
3276 outl(POLL_DEMAND, DE4X5_TPD);
3277
3278 netif_wake_queue(dev);
3279 }
3280
3281 /*
3282 ** General PHY reset function. Some MII devices don't reset correctly
3283 ** since their MII address pins can float at voltages that are dependent
3284 ** on the signal pin use. Do a double reset to ensure a reset.
3285 */
3286 static int
3287 de4x5_reset_phy(struct net_device *dev)
3288 {
3289 struct de4x5_private *lp = netdev_priv(dev);
3290 u_long iobase = dev->base_addr;
3291 int next_tick = 0;
3292
3293 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3294 if (lp->timeout < 0) {
3295 if (lp->useSROM) {
3296 if (lp->phy[lp->active].rst) {
3297 srom_exec(dev, lp->phy[lp->active].rst);
3298 srom_exec(dev, lp->phy[lp->active].rst);
3299 } else if (lp->rst) { /* Type 5 infoblock reset */
3300 srom_exec(dev, lp->rst);
3301 srom_exec(dev, lp->rst);
3302 }
3303 } else {
3304 PHY_HARD_RESET;
3305 }
3306 if (lp->useMII) {
3307 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3308 }
3309 }
3310 if (lp->useMII) {
3311 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3312 }
3313 } else if (lp->chipset == DC21140) {
3314 PHY_HARD_RESET;
3315 }
3316
3317 return next_tick;
3318 }
3319
3320 static int
3321 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3322 {
3323 struct de4x5_private *lp = netdev_priv(dev);
3324 u_long iobase = dev->base_addr;
3325 s32 sts, csr12;
3326
3327 if (lp->timeout < 0) {
3328 lp->timeout = msec/100;
3329 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3330 reset_init_sia(dev, csr13, csr14, csr15);
3331 }
3332
3333 /* set up the interrupt mask */
3334 outl(irq_mask, DE4X5_IMR);
3335
3336 /* clear all pending interrupts */
3337 sts = inl(DE4X5_STS);
3338 outl(sts, DE4X5_STS);
3339
3340 /* clear csr12 NRA and SRA bits */
3341 if ((lp->chipset == DC21041) || lp->useSROM) {
3342 csr12 = inl(DE4X5_SISR);
3343 outl(csr12, DE4X5_SISR);
3344 }
3345 }
3346
3347 sts = inl(DE4X5_STS) & ~TIMER_CB;
3348
3349 if (!(sts & irqs) && --lp->timeout) {
3350 sts = 100 | TIMER_CB;
3351 } else {
3352 lp->timeout = -1;
3353 }
3354
3355 return sts;
3356 }
3357
3358 static int
3359 test_tp(struct net_device *dev, s32 msec)
3360 {
3361 struct de4x5_private *lp = netdev_priv(dev);
3362 u_long iobase = dev->base_addr;
3363 int sisr;
3364
3365 if (lp->timeout < 0) {
3366 lp->timeout = msec/100;
3367 }
3368
3369 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3370
3371 if (sisr && --lp->timeout) {
3372 sisr = 100 | TIMER_CB;
3373 } else {
3374 lp->timeout = -1;
3375 }
3376
3377 return sisr;
3378 }
3379
3380 /*
3381 ** Samples the 100Mb Link State Signal. The sample interval is important
3382 ** because too fast a rate can give erroneous results and confuse the
3383 ** speed sense algorithm.
3384 */
3385 #define SAMPLE_INTERVAL 500 /* ms */
3386 #define SAMPLE_DELAY 2000 /* ms */
3387 static int
3388 test_for_100Mb(struct net_device *dev, int msec)
3389 {
3390 struct de4x5_private *lp = netdev_priv(dev);
3391 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3392
3393 if (lp->timeout < 0) {
3394 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3395 if (msec > SAMPLE_DELAY) {
3396 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3397 gep = SAMPLE_DELAY | TIMER_CB;
3398 return gep;
3399 } else {
3400 lp->timeout = msec/SAMPLE_INTERVAL;
3401 }
3402 }
3403
3404 if (lp->phy[lp->active].id || lp->useSROM) {
3405 gep = is_100_up(dev) | is_spd_100(dev);
3406 } else {
3407 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3408 }
3409 if (!(gep & ret) && --lp->timeout) {
3410 gep = SAMPLE_INTERVAL | TIMER_CB;
3411 } else {
3412 lp->timeout = -1;
3413 }
3414
3415 return gep;
3416 }
3417
3418 static int
3419 wait_for_link(struct net_device *dev)
3420 {
3421 struct de4x5_private *lp = netdev_priv(dev);
3422
3423 if (lp->timeout < 0) {
3424 lp->timeout = 1;
3425 }
3426
3427 if (lp->timeout--) {
3428 return TIMER_CB;
3429 } else {
3430 lp->timeout = -1;
3431 }
3432
3433 return 0;
3434 }
3435
3436 /*
3437 **
3438 **
3439 */
3440 static int
3441 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3442 {
3443 struct de4x5_private *lp = netdev_priv(dev);
3444 int test;
3445 u_long iobase = dev->base_addr;
3446
3447 if (lp->timeout < 0) {
3448 lp->timeout = msec/100;
3449 }
3450
3451 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3452 test = (reg ^ (pol ? ~0 : 0)) & mask;
3453
3454 if (test && --lp->timeout) {
3455 reg = 100 | TIMER_CB;
3456 } else {
3457 lp->timeout = -1;
3458 }
3459
3460 return reg;
3461 }
3462
3463 static int
3464 is_spd_100(struct net_device *dev)
3465 {
3466 struct de4x5_private *lp = netdev_priv(dev);
3467 u_long iobase = dev->base_addr;
3468 int spd;
3469
3470 if (lp->useMII) {
3471 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3472 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3473 spd &= lp->phy[lp->active].spd.mask;
3474 } else if (!lp->useSROM) { /* de500-xa */
3475 spd = ((~gep_rd(dev)) & GEP_SLNK);
3476 } else {
3477 if ((lp->ibn == 2) || !lp->asBitValid)
3478 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3479
3480 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3481 (lp->linkOK & ~lp->asBitValid);
3482 }
3483
3484 return spd;
3485 }
3486
3487 static int
3488 is_100_up(struct net_device *dev)
3489 {
3490 struct de4x5_private *lp = netdev_priv(dev);
3491 u_long iobase = dev->base_addr;
3492
3493 if (lp->useMII) {
3494 /* Double read for sticky bits & temporary drops */
3495 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3496 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3497 } else if (!lp->useSROM) { /* de500-xa */
3498 return (~gep_rd(dev)) & GEP_SLNK;
3499 } else {
3500 if ((lp->ibn == 2) || !lp->asBitValid)
3501 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3502
3503 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3504 (lp->linkOK & ~lp->asBitValid);
3505 }
3506 }
3507
3508 static int
3509 is_10_up(struct net_device *dev)
3510 {
3511 struct de4x5_private *lp = netdev_priv(dev);
3512 u_long iobase = dev->base_addr;
3513
3514 if (lp->useMII) {
3515 /* Double read for sticky bits & temporary drops */
3516 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3517 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3518 } else if (!lp->useSROM) { /* de500-xa */
3519 return (~gep_rd(dev)) & GEP_LNP;
3520 } else {
3521 if ((lp->ibn == 2) || !lp->asBitValid)
3522 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3523 (~inl(DE4X5_SISR)&SISR_LS10):
3524 0;
3525
3526 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3527 (lp->linkOK & ~lp->asBitValid);
3528 }
3529 }
3530
3531 static int
3532 is_anc_capable(struct net_device *dev)
3533 {
3534 struct de4x5_private *lp = netdev_priv(dev);
3535 u_long iobase = dev->base_addr;
3536
3537 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3538 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3539 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3540 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3541 } else {
3542 return 0;
3543 }
3544 }
3545
3546 /*
3547 ** Send a packet onto the media and watch for send errors that indicate the
3548 ** media is bad or unconnected.
3549 */
3550 static int
3551 ping_media(struct net_device *dev, int msec)
3552 {
3553 struct de4x5_private *lp = netdev_priv(dev);
3554 u_long iobase = dev->base_addr;
3555 int sisr;
3556
3557 if (lp->timeout < 0) {
3558 lp->timeout = msec/100;
3559
3560 lp->tmp = lp->tx_new; /* Remember the ring position */
3561 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3562 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3563 outl(POLL_DEMAND, DE4X5_TPD);
3564 }
3565
3566 sisr = inl(DE4X5_SISR);
3567
3568 if ((!(sisr & SISR_NCR)) &&
3569 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3570 (--lp->timeout)) {
3571 sisr = 100 | TIMER_CB;
3572 } else {
3573 if ((!(sisr & SISR_NCR)) &&
3574 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3575 lp->timeout) {
3576 sisr = 0;
3577 } else {
3578 sisr = 1;
3579 }
3580 lp->timeout = -1;
3581 }
3582
3583 return sisr;
3584 }
3585
3586 /*
3587 ** This function does 2 things: on Intels it kmalloc's another buffer to
3588 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3589 ** into which the packet is copied.
3590 */
3591 static struct sk_buff *
3592 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3593 {
3594 struct de4x5_private *lp = netdev_priv(dev);
3595 struct sk_buff *p;
3596
3597 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3598 struct sk_buff *ret;
3599 u_long i=0, tmp;
3600
3601 p = netdev_alloc_skb(dev, IEEE802_3_SZ + DE4X5_ALIGN + 2);
3602 if (!p) return NULL;
3603
3604 tmp = virt_to_bus(p->data);
3605 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3606 skb_reserve(p, i);
3607 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3608
3609 ret = lp->rx_skb[index];
3610 lp->rx_skb[index] = p;
3611
3612 if ((u_long) ret > 1) {
3613 skb_put(ret, len);
3614 }
3615
3616 return ret;
3617
3618 #else
3619 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3620
3621 p = netdev_alloc_skb(dev, len + 2);
3622 if (!p) return NULL;
3623
3624 skb_reserve(p, 2); /* Align */
3625 if (index < lp->rx_old) { /* Wrapped buffer */
3626 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3627 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3628 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3629 } else { /* Linear buffer */
3630 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3631 }
3632
3633 return p;
3634 #endif
3635 }
3636
3637 static void
3638 de4x5_free_rx_buffs(struct net_device *dev)
3639 {
3640 struct de4x5_private *lp = netdev_priv(dev);
3641 int i;
3642
3643 for (i=0; i<lp->rxRingSize; i++) {
3644 if ((u_long) lp->rx_skb[i] > 1) {
3645 dev_kfree_skb(lp->rx_skb[i]);
3646 }
3647 lp->rx_ring[i].status = 0;
3648 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3649 }
3650 }
3651
3652 static void
3653 de4x5_free_tx_buffs(struct net_device *dev)
3654 {
3655 struct de4x5_private *lp = netdev_priv(dev);
3656 int i;
3657
3658 for (i=0; i<lp->txRingSize; i++) {
3659 if (lp->tx_skb[i])
3660 de4x5_free_tx_buff(lp, i);
3661 lp->tx_ring[i].status = 0;
3662 }
3663
3664 /* Unload the locally queued packets */
3665 __skb_queue_purge(&lp->cache.queue);
3666 }
3667
3668 /*
3669 ** When a user pulls a connection, the DECchip can end up in a
3670 ** 'running - waiting for end of transmission' state. This means that we
3671 ** have to perform a chip soft reset to ensure that we can synchronize
3672 ** the hardware and software and make any media probes using a loopback
3673 ** packet meaningful.
3674 */
3675 static void
3676 de4x5_save_skbs(struct net_device *dev)
3677 {
3678 struct de4x5_private *lp = netdev_priv(dev);
3679 u_long iobase = dev->base_addr;
3680 s32 omr;
3681
3682 if (!lp->cache.save_cnt) {
3683 STOP_DE4X5;
3684 de4x5_tx(dev); /* Flush any sent skb's */
3685 de4x5_free_tx_buffs(dev);
3686 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3687 de4x5_sw_reset(dev);
3688 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3689 lp->cache.save_cnt++;
3690 START_DE4X5;
3691 }
3692 }
3693
3694 static void
3695 de4x5_rst_desc_ring(struct net_device *dev)
3696 {
3697 struct de4x5_private *lp = netdev_priv(dev);
3698 u_long iobase = dev->base_addr;
3699 int i;
3700 s32 omr;
3701
3702 if (lp->cache.save_cnt) {
3703 STOP_DE4X5;
3704 outl(lp->dma_rings, DE4X5_RRBA);
3705 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3706 DE4X5_TRBA);
3707
3708 lp->rx_new = lp->rx_old = 0;
3709 lp->tx_new = lp->tx_old = 0;
3710
3711 for (i = 0; i < lp->rxRingSize; i++) {
3712 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3713 }
3714
3715 for (i = 0; i < lp->txRingSize; i++) {
3716 lp->tx_ring[i].status = cpu_to_le32(0);
3717 }
3718
3719 barrier();
3720 lp->cache.save_cnt--;
3721 START_DE4X5;
3722 }
3723 }
3724
3725 static void
3726 de4x5_cache_state(struct net_device *dev, int flag)
3727 {
3728 struct de4x5_private *lp = netdev_priv(dev);
3729 u_long iobase = dev->base_addr;
3730
3731 switch(flag) {
3732 case DE4X5_SAVE_STATE:
3733 lp->cache.csr0 = inl(DE4X5_BMR);
3734 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3735 lp->cache.csr7 = inl(DE4X5_IMR);
3736 break;
3737
3738 case DE4X5_RESTORE_STATE:
3739 outl(lp->cache.csr0, DE4X5_BMR);
3740 outl(lp->cache.csr6, DE4X5_OMR);
3741 outl(lp->cache.csr7, DE4X5_IMR);
3742 if (lp->chipset == DC21140) {
3743 gep_wr(lp->cache.gepc, dev);
3744 gep_wr(lp->cache.gep, dev);
3745 } else {
3746 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3747 lp->cache.csr15);
3748 }
3749 break;
3750 }
3751 }
3752
3753 static void
3754 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3755 {
3756 struct de4x5_private *lp = netdev_priv(dev);
3757
3758 __skb_queue_tail(&lp->cache.queue, skb);
3759 }
3760
3761 static void
3762 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3763 {
3764 struct de4x5_private *lp = netdev_priv(dev);
3765
3766 __skb_queue_head(&lp->cache.queue, skb);
3767 }
3768
3769 static struct sk_buff *
3770 de4x5_get_cache(struct net_device *dev)
3771 {
3772 struct de4x5_private *lp = netdev_priv(dev);
3773
3774 return __skb_dequeue(&lp->cache.queue);
3775 }
3776
3777 /*
3778 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3779 ** is received and the auto-negotiation status is NWAY OK.
3780 */
3781 static int
3782 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3783 {
3784 struct de4x5_private *lp = netdev_priv(dev);
3785 u_long iobase = dev->base_addr;
3786 s32 sts, ans;
3787
3788 if (lp->timeout < 0) {
3789 lp->timeout = msec/100;
3790 outl(irq_mask, DE4X5_IMR);
3791
3792 /* clear all pending interrupts */
3793 sts = inl(DE4X5_STS);
3794 outl(sts, DE4X5_STS);
3795 }
3796
3797 ans = inl(DE4X5_SISR) & SISR_ANS;
3798 sts = inl(DE4X5_STS) & ~TIMER_CB;
3799
3800 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3801 sts = 100 | TIMER_CB;
3802 } else {
3803 lp->timeout = -1;
3804 }
3805
3806 return sts;
3807 }
3808
3809 static void
3810 de4x5_setup_intr(struct net_device *dev)
3811 {
3812 struct de4x5_private *lp = netdev_priv(dev);
3813 u_long iobase = dev->base_addr;
3814 s32 imr, sts;
3815
3816 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3817 imr = 0;
3818 UNMASK_IRQs;
3819 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3820 outl(sts, DE4X5_STS);
3821 ENABLE_IRQs;
3822 }
3823 }
3824
3825 /*
3826 **
3827 */
3828 static void
3829 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3830 {
3831 struct de4x5_private *lp = netdev_priv(dev);
3832 u_long iobase = dev->base_addr;
3833
3834 RESET_SIA;
3835 if (lp->useSROM) {
3836 if (lp->ibn == 3) {
3837 srom_exec(dev, lp->phy[lp->active].rst);
3838 srom_exec(dev, lp->phy[lp->active].gep);
3839 outl(1, DE4X5_SICR);
3840 return;
3841 } else {
3842 csr15 = lp->cache.csr15;
3843 csr14 = lp->cache.csr14;
3844 csr13 = lp->cache.csr13;
3845 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3846 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3847 }
3848 } else {
3849 outl(csr15, DE4X5_SIGR);
3850 }
3851 outl(csr14, DE4X5_STRR);
3852 outl(csr13, DE4X5_SICR);
3853
3854 mdelay(10);
3855 }
3856
3857 /*
3858 ** Create a loopback ethernet packet
3859 */
3860 static void
3861 create_packet(struct net_device *dev, char *frame, int len)
3862 {
3863 int i;
3864 char *buf = frame;
3865
3866 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3867 *buf++ = dev->dev_addr[i];
3868 }
3869 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3870 *buf++ = dev->dev_addr[i];
3871 }
3872
3873 *buf++ = 0; /* Packet length (2 bytes) */
3874 *buf++ = 1;
3875 }
3876
3877 /*
3878 ** Look for a particular board name in the EISA configuration space
3879 */
3880 static int
3881 EISA_signature(char *name, struct device *device)
3882 {
3883 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3884 struct eisa_device *edev;
3885
3886 *name = '\0';
3887 edev = to_eisa_device (device);
3888 i = edev->id.driver_data;
3889
3890 if (i >= 0 && i < siglen) {
3891 strcpy (name, de4x5_signatures[i]);
3892 status = 1;
3893 }
3894
3895 return status; /* return the device name string */
3896 }
3897
3898 /*
3899 ** Look for a particular board name in the PCI configuration space
3900 */
3901 static int
3902 PCI_signature(char *name, struct de4x5_private *lp)
3903 {
3904 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3905
3906 if (lp->chipset == DC21040) {
3907 strcpy(name, "DE434/5");
3908 return status;
3909 } else { /* Search for a DEC name in the SROM */
3910 int tmp = *((char *)&lp->srom + 19) * 3;
3911 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3912 }
3913 name[8] = '\0';
3914 for (i=0; i<siglen; i++) {
3915 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3916 }
3917 if (i == siglen) {
3918 if (dec_only) {
3919 *name = '\0';
3920 } else { /* Use chip name to avoid confusion */
3921 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3922 ((lp->chipset == DC21041) ? "DC21041" :
3923 ((lp->chipset == DC21140) ? "DC21140" :
3924 ((lp->chipset == DC21142) ? "DC21142" :
3925 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3926 )))))));
3927 }
3928 if (lp->chipset != DC21041) {
3929 lp->useSROM = true; /* card is not recognisably DEC */
3930 }
3931 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3932 lp->useSROM = true;
3933 }
3934
3935 return status;
3936 }
3937
3938 /*
3939 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3940 ** the DC21040, else read the SROM for the other chips.
3941 ** The SROM may not be present in a multi-MAC card, so first read the
3942 ** MAC address and check for a bad address. If there is a bad one then exit
3943 ** immediately with the prior srom contents intact (the h/w address will
3944 ** be fixed up later).
3945 */
3946 static void
3947 DevicePresent(struct net_device *dev, u_long aprom_addr)
3948 {
3949 int i, j=0;
3950 struct de4x5_private *lp = netdev_priv(dev);
3951
3952 if (lp->chipset == DC21040) {
3953 if (lp->bus == EISA) {
3954 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3955 } else {
3956 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3957 }
3958 } else { /* Read new srom */
3959 u_short tmp;
3960 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3961 for (i=0; i<(ETH_ALEN>>1); i++) {
3962 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3963 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3964 *p = cpu_to_le16(tmp);
3965 }
3966 if (j == 0 || j == 3 * 0xffff) {
3967 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3968 return;
3969 }
3970
3971 p = (__le16 *)&lp->srom;
3972 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3973 tmp = srom_rd(aprom_addr, i);
3974 *p++ = cpu_to_le16(tmp);
3975 }
3976 de4x5_dbg_srom(&lp->srom);
3977 }
3978 }
3979
3980 /*
3981 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
3982 ** pointer correctly (at least on my DE425 EISA card), this routine should do
3983 ** it...from depca.c.
3984 */
3985 static void
3986 enet_addr_rst(u_long aprom_addr)
3987 {
3988 union {
3989 struct {
3990 u32 a;
3991 u32 b;
3992 } llsig;
3993 char Sig[sizeof(u32) << 1];
3994 } dev;
3995 short sigLength=0;
3996 s8 data;
3997 int i, j;
3998
3999 dev.llsig.a = ETH_PROM_SIG;
4000 dev.llsig.b = ETH_PROM_SIG;
4001 sigLength = sizeof(u32) << 1;
4002
4003 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4004 data = inb(aprom_addr);
4005 if (dev.Sig[j] == data) { /* track signature */
4006 j++;
4007 } else { /* lost signature; begin search again */
4008 if (data == dev.Sig[0]) { /* rare case.... */
4009 j=1;
4010 } else {
4011 j=0;
4012 }
4013 }
4014 }
4015 }
4016
4017 /*
4018 ** For the bad status case and no SROM, then add one to the previous
4019 ** address. However, need to add one backwards in case we have 0xff
4020 ** as one or more of the bytes. Only the last 3 bytes should be checked
4021 ** as the first three are invariant - assigned to an organisation.
4022 */
4023 static int
4024 get_hw_addr(struct net_device *dev)
4025 {
4026 u_long iobase = dev->base_addr;
4027 int broken, i, k, tmp, status = 0;
4028 u_short j,chksum;
4029 struct de4x5_private *lp = netdev_priv(dev);
4030
4031 broken = de4x5_bad_srom(lp);
4032
4033 for (i=0,k=0,j=0;j<3;j++) {
4034 k <<= 1;
4035 if (k > 0xffff) k-=0xffff;
4036
4037 if (lp->bus == PCI) {
4038 if (lp->chipset == DC21040) {
4039 while ((tmp = inl(DE4X5_APROM)) < 0);
4040 k += (u_char) tmp;
4041 dev->dev_addr[i++] = (u_char) tmp;
4042 while ((tmp = inl(DE4X5_APROM)) < 0);
4043 k += (u_short) (tmp << 8);
4044 dev->dev_addr[i++] = (u_char) tmp;
4045 } else if (!broken) {
4046 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4047 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4048 } else if ((broken == SMC) || (broken == ACCTON)) {
4049 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4050 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4051 }
4052 } else {
4053 k += (u_char) (tmp = inb(EISA_APROM));
4054 dev->dev_addr[i++] = (u_char) tmp;
4055 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4056 dev->dev_addr[i++] = (u_char) tmp;
4057 }
4058
4059 if (k > 0xffff) k-=0xffff;
4060 }
4061 if (k == 0xffff) k=0;
4062
4063 if (lp->bus == PCI) {
4064 if (lp->chipset == DC21040) {
4065 while ((tmp = inl(DE4X5_APROM)) < 0);
4066 chksum = (u_char) tmp;
4067 while ((tmp = inl(DE4X5_APROM)) < 0);
4068 chksum |= (u_short) (tmp << 8);
4069 if ((k != chksum) && (dec_only)) status = -1;
4070 }
4071 } else {
4072 chksum = (u_char) inb(EISA_APROM);
4073 chksum |= (u_short) (inb(EISA_APROM) << 8);
4074 if ((k != chksum) && (dec_only)) status = -1;
4075 }
4076
4077 /* If possible, try to fix a broken card - SMC only so far */
4078 srom_repair(dev, broken);
4079
4080 #ifdef CONFIG_PPC_PMAC
4081 /*
4082 ** If the address starts with 00 a0, we have to bit-reverse
4083 ** each byte of the address.
4084 */
4085 if ( machine_is(powermac) &&
4086 (dev->dev_addr[0] == 0) &&
4087 (dev->dev_addr[1] == 0xa0) )
4088 {
4089 for (i = 0; i < ETH_ALEN; ++i)
4090 {
4091 int x = dev->dev_addr[i];
4092 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4093 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4094 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4095 }
4096 }
4097 #endif /* CONFIG_PPC_PMAC */
4098
4099 /* Test for a bad enet address */
4100 status = test_bad_enet(dev, status);
4101
4102 return status;
4103 }
4104
4105 /*
4106 ** Test for enet addresses in the first 32 bytes.
4107 */
4108 static int
4109 de4x5_bad_srom(struct de4x5_private *lp)
4110 {
4111 int i, status = 0;
4112
4113 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4114 if (!memcmp(&lp->srom, &enet_det[i], 3) &&
4115 !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) {
4116 if (i == 0) {
4117 status = SMC;
4118 } else if (i == 1) {
4119 status = ACCTON;
4120 }
4121 break;
4122 }
4123 }
4124
4125 return status;
4126 }
4127
4128 static void
4129 srom_repair(struct net_device *dev, int card)
4130 {
4131 struct de4x5_private *lp = netdev_priv(dev);
4132
4133 switch(card) {
4134 case SMC:
4135 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4136 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4137 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4138 lp->useSROM = true;
4139 break;
4140 }
4141 }
4142
4143 /*
4144 ** Assume that the irq's do not follow the PCI spec - this is seems
4145 ** to be true so far (2 for 2).
4146 */
4147 static int
4148 test_bad_enet(struct net_device *dev, int status)
4149 {
4150 struct de4x5_private *lp = netdev_priv(dev);
4151 int i, tmp;
4152
4153 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4154 if ((tmp == 0) || (tmp == 0x5fa)) {
4155 if ((lp->chipset == last.chipset) &&
4156 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4157 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4158 for (i=ETH_ALEN-1; i>2; --i) {
4159 dev->dev_addr[i] += 1;
4160 if (dev->dev_addr[i] != 0) break;
4161 }
4162 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4163 if (!an_exception(lp)) {
4164 dev->irq = last.irq;
4165 }
4166
4167 status = 0;
4168 }
4169 } else if (!status) {
4170 last.chipset = lp->chipset;
4171 last.bus = lp->bus_num;
4172 last.irq = dev->irq;
4173 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4174 }
4175
4176 return status;
4177 }
4178
4179 /*
4180 ** List of board exceptions with correctly wired IRQs
4181 */
4182 static int
4183 an_exception(struct de4x5_private *lp)
4184 {
4185 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4186 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4187 return -1;
4188 }
4189
4190 return 0;
4191 }
4192
4193 /*
4194 ** SROM Read
4195 */
4196 static short
4197 srom_rd(u_long addr, u_char offset)
4198 {
4199 sendto_srom(SROM_RD | SROM_SR, addr);
4200
4201 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4202 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4203 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4204
4205 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4206 }
4207
4208 static void
4209 srom_latch(u_int command, u_long addr)
4210 {
4211 sendto_srom(command, addr);
4212 sendto_srom(command | DT_CLK, addr);
4213 sendto_srom(command, addr);
4214 }
4215
4216 static void
4217 srom_command(u_int command, u_long addr)
4218 {
4219 srom_latch(command, addr);
4220 srom_latch(command, addr);
4221 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4222 }
4223
4224 static void
4225 srom_address(u_int command, u_long addr, u_char offset)
4226 {
4227 int i, a;
4228
4229 a = offset << 2;
4230 for (i=0; i<6; i++, a <<= 1) {
4231 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4232 }
4233 udelay(1);
4234
4235 i = (getfrom_srom(addr) >> 3) & 0x01;
4236 }
4237
4238 static short
4239 srom_data(u_int command, u_long addr)
4240 {
4241 int i;
4242 short word = 0;
4243 s32 tmp;
4244
4245 for (i=0; i<16; i++) {
4246 sendto_srom(command | DT_CLK, addr);
4247 tmp = getfrom_srom(addr);
4248 sendto_srom(command, addr);
4249
4250 word = (word << 1) | ((tmp >> 3) & 0x01);
4251 }
4252
4253 sendto_srom(command & 0x0000ff00, addr);
4254
4255 return word;
4256 }
4257
4258 /*
4259 static void
4260 srom_busy(u_int command, u_long addr)
4261 {
4262 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4263
4264 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4265 mdelay(1);
4266 }
4267
4268 sendto_srom(command & 0x0000ff00, addr);
4269 }
4270 */
4271
4272 static void
4273 sendto_srom(u_int command, u_long addr)
4274 {
4275 outl(command, addr);
4276 udelay(1);
4277 }
4278
4279 static int
4280 getfrom_srom(u_long addr)
4281 {
4282 s32 tmp;
4283
4284 tmp = inl(addr);
4285 udelay(1);
4286
4287 return tmp;
4288 }
4289
4290 static int
4291 srom_infoleaf_info(struct net_device *dev)
4292 {
4293 struct de4x5_private *lp = netdev_priv(dev);
4294 int i, count;
4295 u_char *p;
4296
4297 /* Find the infoleaf decoder function that matches this chipset */
4298 for (i=0; i<INFOLEAF_SIZE; i++) {
4299 if (lp->chipset == infoleaf_array[i].chipset) break;
4300 }
4301 if (i == INFOLEAF_SIZE) {
4302 lp->useSROM = false;
4303 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4304 dev->name);
4305 return -ENXIO;
4306 }
4307
4308 lp->infoleaf_fn = infoleaf_array[i].fn;
4309
4310 /* Find the information offset that this function should use */
4311 count = *((u_char *)&lp->srom + 19);
4312 p = (u_char *)&lp->srom + 26;
4313
4314 if (count > 1) {
4315 for (i=count; i; --i, p+=3) {
4316 if (lp->device == *p) break;
4317 }
4318 if (i == 0) {
4319 lp->useSROM = false;
4320 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4321 dev->name, lp->device);
4322 return -ENXIO;
4323 }
4324 }
4325
4326 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4327
4328 return 0;
4329 }
4330
4331 /*
4332 ** This routine loads any type 1 or 3 MII info into the mii device
4333 ** struct and executes any type 5 code to reset PHY devices for this
4334 ** controller.
4335 ** The info for the MII devices will be valid since the index used
4336 ** will follow the discovery process from MII address 1-31 then 0.
4337 */
4338 static void
4339 srom_init(struct net_device *dev)
4340 {
4341 struct de4x5_private *lp = netdev_priv(dev);
4342 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4343 u_char count;
4344
4345 p+=2;
4346 if (lp->chipset == DC21140) {
4347 lp->cache.gepc = (*p++ | GEP_CTRL);
4348 gep_wr(lp->cache.gepc, dev);
4349 }
4350
4351 /* Block count */
4352 count = *p++;
4353
4354 /* Jump the infoblocks to find types */
4355 for (;count; --count) {
4356 if (*p < 128) {
4357 p += COMPACT_LEN;
4358 } else if (*(p+1) == 5) {
4359 type5_infoblock(dev, 1, p);
4360 p += ((*p & BLOCK_LEN) + 1);
4361 } else if (*(p+1) == 4) {
4362 p += ((*p & BLOCK_LEN) + 1);
4363 } else if (*(p+1) == 3) {
4364 type3_infoblock(dev, 1, p);
4365 p += ((*p & BLOCK_LEN) + 1);
4366 } else if (*(p+1) == 2) {
4367 p += ((*p & BLOCK_LEN) + 1);
4368 } else if (*(p+1) == 1) {
4369 type1_infoblock(dev, 1, p);
4370 p += ((*p & BLOCK_LEN) + 1);
4371 } else {
4372 p += ((*p & BLOCK_LEN) + 1);
4373 }
4374 }
4375 }
4376
4377 /*
4378 ** A generic routine that writes GEP control, data and reset information
4379 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4380 */
4381 static void
4382 srom_exec(struct net_device *dev, u_char *p)
4383 {
4384 struct de4x5_private *lp = netdev_priv(dev);
4385 u_long iobase = dev->base_addr;
4386 u_char count = (p ? *p++ : 0);
4387 u_short *w = (u_short *)p;
4388
4389 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4390
4391 if (lp->chipset != DC21140) RESET_SIA;
4392
4393 while (count--) {
4394 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4395 *p++ : get_unaligned_le16(w++)), dev);
4396 mdelay(2); /* 2ms per action */
4397 }
4398
4399 if (lp->chipset != DC21140) {
4400 outl(lp->cache.csr14, DE4X5_STRR);
4401 outl(lp->cache.csr13, DE4X5_SICR);
4402 }
4403 }
4404
4405 /*
4406 ** Basically this function is a NOP since it will never be called,
4407 ** unless I implement the DC21041 SROM functions. There's no need
4408 ** since the existing code will be satisfactory for all boards.
4409 */
4410 static int
4411 dc21041_infoleaf(struct net_device *dev)
4412 {
4413 return DE4X5_AUTOSENSE_MS;
4414 }
4415
4416 static int
4417 dc21140_infoleaf(struct net_device *dev)
4418 {
4419 struct de4x5_private *lp = netdev_priv(dev);
4420 u_char count = 0;
4421 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4422 int next_tick = DE4X5_AUTOSENSE_MS;
4423
4424 /* Read the connection type */
4425 p+=2;
4426
4427 /* GEP control */
4428 lp->cache.gepc = (*p++ | GEP_CTRL);
4429
4430 /* Block count */
4431 count = *p++;
4432
4433 /* Recursively figure out the info blocks */
4434 if (*p < 128) {
4435 next_tick = dc_infoblock[COMPACT](dev, count, p);
4436 } else {
4437 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4438 }
4439
4440 if (lp->tcount == count) {
4441 lp->media = NC;
4442 if (lp->media != lp->c_media) {
4443 de4x5_dbg_media(dev);
4444 lp->c_media = lp->media;
4445 }
4446 lp->media = INIT;
4447 lp->tcount = 0;
4448 lp->tx_enable = false;
4449 }
4450
4451 return next_tick & ~TIMER_CB;
4452 }
4453
4454 static int
4455 dc21142_infoleaf(struct net_device *dev)
4456 {
4457 struct de4x5_private *lp = netdev_priv(dev);
4458 u_char count = 0;
4459 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4460 int next_tick = DE4X5_AUTOSENSE_MS;
4461
4462 /* Read the connection type */
4463 p+=2;
4464
4465 /* Block count */
4466 count = *p++;
4467
4468 /* Recursively figure out the info blocks */
4469 if (*p < 128) {
4470 next_tick = dc_infoblock[COMPACT](dev, count, p);
4471 } else {
4472 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4473 }
4474
4475 if (lp->tcount == count) {
4476 lp->media = NC;
4477 if (lp->media != lp->c_media) {
4478 de4x5_dbg_media(dev);
4479 lp->c_media = lp->media;
4480 }
4481 lp->media = INIT;
4482 lp->tcount = 0;
4483 lp->tx_enable = false;
4484 }
4485
4486 return next_tick & ~TIMER_CB;
4487 }
4488
4489 static int
4490 dc21143_infoleaf(struct net_device *dev)
4491 {
4492 struct de4x5_private *lp = netdev_priv(dev);
4493 u_char count = 0;
4494 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4495 int next_tick = DE4X5_AUTOSENSE_MS;
4496
4497 /* Read the connection type */
4498 p+=2;
4499
4500 /* Block count */
4501 count = *p++;
4502
4503 /* Recursively figure out the info blocks */
4504 if (*p < 128) {
4505 next_tick = dc_infoblock[COMPACT](dev, count, p);
4506 } else {
4507 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4508 }
4509 if (lp->tcount == count) {
4510 lp->media = NC;
4511 if (lp->media != lp->c_media) {
4512 de4x5_dbg_media(dev);
4513 lp->c_media = lp->media;
4514 }
4515 lp->media = INIT;
4516 lp->tcount = 0;
4517 lp->tx_enable = false;
4518 }
4519
4520 return next_tick & ~TIMER_CB;
4521 }
4522
4523 /*
4524 ** The compact infoblock is only designed for DC21140[A] chips, so
4525 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4526 */
4527 static int
4528 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4529 {
4530 struct de4x5_private *lp = netdev_priv(dev);
4531 u_char flags, csr6;
4532
4533 /* Recursively figure out the info blocks */
4534 if (--count > lp->tcount) {
4535 if (*(p+COMPACT_LEN) < 128) {
4536 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4537 } else {
4538 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4539 }
4540 }
4541
4542 if ((lp->media == INIT) && (lp->timeout < 0)) {
4543 lp->ibn = COMPACT;
4544 lp->active = 0;
4545 gep_wr(lp->cache.gepc, dev);
4546 lp->infoblock_media = (*p++) & COMPACT_MC;
4547 lp->cache.gep = *p++;
4548 csr6 = *p++;
4549 flags = *p++;
4550
4551 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4552 lp->defMedium = (flags & 0x40) ? -1 : 0;
4553 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4554 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4555 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4556 lp->useMII = false;
4557
4558 de4x5_switch_mac_port(dev);
4559 }
4560
4561 return dc21140m_autoconf(dev);
4562 }
4563
4564 /*
4565 ** This block describes non MII media for the DC21140[A] only.
4566 */
4567 static int
4568 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4569 {
4570 struct de4x5_private *lp = netdev_priv(dev);
4571 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4572
4573 /* Recursively figure out the info blocks */
4574 if (--count > lp->tcount) {
4575 if (*(p+len) < 128) {
4576 return dc_infoblock[COMPACT](dev, count, p+len);
4577 } else {
4578 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4579 }
4580 }
4581
4582 if ((lp->media == INIT) && (lp->timeout < 0)) {
4583 lp->ibn = 0;
4584 lp->active = 0;
4585 gep_wr(lp->cache.gepc, dev);
4586 p+=2;
4587 lp->infoblock_media = (*p++) & BLOCK0_MC;
4588 lp->cache.gep = *p++;
4589 csr6 = *p++;
4590 flags = *p++;
4591
4592 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4593 lp->defMedium = (flags & 0x40) ? -1 : 0;
4594 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4595 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4596 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4597 lp->useMII = false;
4598
4599 de4x5_switch_mac_port(dev);
4600 }
4601
4602 return dc21140m_autoconf(dev);
4603 }
4604
4605 /* These functions are under construction! */
4606
4607 static int
4608 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4609 {
4610 struct de4x5_private *lp = netdev_priv(dev);
4611 u_char len = (*p & BLOCK_LEN)+1;
4612
4613 /* Recursively figure out the info blocks */
4614 if (--count > lp->tcount) {
4615 if (*(p+len) < 128) {
4616 return dc_infoblock[COMPACT](dev, count, p+len);
4617 } else {
4618 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4619 }
4620 }
4621
4622 p += 2;
4623 if (lp->state == INITIALISED) {
4624 lp->ibn = 1;
4625 lp->active = *p++;
4626 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4627 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4628 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4629 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4630 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4631 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4632 return 0;
4633 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4634 lp->ibn = 1;
4635 lp->active = *p;
4636 lp->infoblock_csr6 = OMR_MII_100;
4637 lp->useMII = true;
4638 lp->infoblock_media = ANS;
4639
4640 de4x5_switch_mac_port(dev);
4641 }
4642
4643 return dc21140m_autoconf(dev);
4644 }
4645
4646 static int
4647 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4648 {
4649 struct de4x5_private *lp = netdev_priv(dev);
4650 u_char len = (*p & BLOCK_LEN)+1;
4651
4652 /* Recursively figure out the info blocks */
4653 if (--count > lp->tcount) {
4654 if (*(p+len) < 128) {
4655 return dc_infoblock[COMPACT](dev, count, p+len);
4656 } else {
4657 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4658 }
4659 }
4660
4661 if ((lp->media == INIT) && (lp->timeout < 0)) {
4662 lp->ibn = 2;
4663 lp->active = 0;
4664 p += 2;
4665 lp->infoblock_media = (*p) & MEDIA_CODE;
4666
4667 if ((*p++) & EXT_FIELD) {
4668 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4669 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4670 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4671 } else {
4672 lp->cache.csr13 = CSR13;
4673 lp->cache.csr14 = CSR14;
4674 lp->cache.csr15 = CSR15;
4675 }
4676 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4677 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4678 lp->infoblock_csr6 = OMR_SIA;
4679 lp->useMII = false;
4680
4681 de4x5_switch_mac_port(dev);
4682 }
4683
4684 return dc2114x_autoconf(dev);
4685 }
4686
4687 static int
4688 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4689 {
4690 struct de4x5_private *lp = netdev_priv(dev);
4691 u_char len = (*p & BLOCK_LEN)+1;
4692
4693 /* Recursively figure out the info blocks */
4694 if (--count > lp->tcount) {
4695 if (*(p+len) < 128) {
4696 return dc_infoblock[COMPACT](dev, count, p+len);
4697 } else {
4698 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4699 }
4700 }
4701
4702 p += 2;
4703 if (lp->state == INITIALISED) {
4704 lp->ibn = 3;
4705 lp->active = *p++;
4706 if (MOTO_SROM_BUG) lp->active = 0;
4707 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4708 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4709 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4710 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4711 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4712 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4713 lp->phy[lp->active].mci = *p;
4714 return 0;
4715 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4716 lp->ibn = 3;
4717 lp->active = *p;
4718 if (MOTO_SROM_BUG) lp->active = 0;
4719 lp->infoblock_csr6 = OMR_MII_100;
4720 lp->useMII = true;
4721 lp->infoblock_media = ANS;
4722
4723 de4x5_switch_mac_port(dev);
4724 }
4725
4726 return dc2114x_autoconf(dev);
4727 }
4728
4729 static int
4730 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4731 {
4732 struct de4x5_private *lp = netdev_priv(dev);
4733 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4734
4735 /* Recursively figure out the info blocks */
4736 if (--count > lp->tcount) {
4737 if (*(p+len) < 128) {
4738 return dc_infoblock[COMPACT](dev, count, p+len);
4739 } else {
4740 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4741 }
4742 }
4743
4744 if ((lp->media == INIT) && (lp->timeout < 0)) {
4745 lp->ibn = 4;
4746 lp->active = 0;
4747 p+=2;
4748 lp->infoblock_media = (*p++) & MEDIA_CODE;
4749 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4750 lp->cache.csr14 = CSR14;
4751 lp->cache.csr15 = CSR15;
4752 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4753 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4754 csr6 = *p++;
4755 flags = *p++;
4756
4757 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4758 lp->defMedium = (flags & 0x40) ? -1 : 0;
4759 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4760 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4761 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4762 lp->useMII = false;
4763
4764 de4x5_switch_mac_port(dev);
4765 }
4766
4767 return dc2114x_autoconf(dev);
4768 }
4769
4770 /*
4771 ** This block type provides information for resetting external devices
4772 ** (chips) through the General Purpose Register.
4773 */
4774 static int
4775 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4776 {
4777 struct de4x5_private *lp = netdev_priv(dev);
4778 u_char len = (*p & BLOCK_LEN)+1;
4779
4780 /* Recursively figure out the info blocks */
4781 if (--count > lp->tcount) {
4782 if (*(p+len) < 128) {
4783 return dc_infoblock[COMPACT](dev, count, p+len);
4784 } else {
4785 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4786 }
4787 }
4788
4789 /* Must be initializing to run this code */
4790 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4791 p+=2;
4792 lp->rst = p;
4793 srom_exec(dev, lp->rst);
4794 }
4795
4796 return DE4X5_AUTOSENSE_MS;
4797 }
4798
4799 /*
4800 ** MII Read/Write
4801 */
4802
4803 static int
4804 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4805 {
4806 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4807 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4808 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4809 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4810 mii_address(phyreg, ioaddr); /* PHY Register to read */
4811 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4812
4813 return mii_rdata(ioaddr); /* Read data */
4814 }
4815
4816 static void
4817 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4818 {
4819 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4820 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4821 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4822 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4823 mii_address(phyreg, ioaddr); /* PHY Register to write */
4824 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4825 data = mii_swap(data, 16); /* Swap data bit ordering */
4826 mii_wdata(data, 16, ioaddr); /* Write data */
4827 }
4828
4829 static int
4830 mii_rdata(u_long ioaddr)
4831 {
4832 int i;
4833 s32 tmp = 0;
4834
4835 for (i=0; i<16; i++) {
4836 tmp <<= 1;
4837 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4838 }
4839
4840 return tmp;
4841 }
4842
4843 static void
4844 mii_wdata(int data, int len, u_long ioaddr)
4845 {
4846 int i;
4847
4848 for (i=0; i<len; i++) {
4849 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4850 data >>= 1;
4851 }
4852 }
4853
4854 static void
4855 mii_address(u_char addr, u_long ioaddr)
4856 {
4857 int i;
4858
4859 addr = mii_swap(addr, 5);
4860 for (i=0; i<5; i++) {
4861 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4862 addr >>= 1;
4863 }
4864 }
4865
4866 static void
4867 mii_ta(u_long rw, u_long ioaddr)
4868 {
4869 if (rw == MII_STWR) {
4870 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4871 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4872 } else {
4873 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4874 }
4875 }
4876
4877 static int
4878 mii_swap(int data, int len)
4879 {
4880 int i, tmp = 0;
4881
4882 for (i=0; i<len; i++) {
4883 tmp <<= 1;
4884 tmp |= (data & 1);
4885 data >>= 1;
4886 }
4887
4888 return tmp;
4889 }
4890
4891 static void
4892 sendto_mii(u32 command, int data, u_long ioaddr)
4893 {
4894 u32 j;
4895
4896 j = (data & 1) << 17;
4897 outl(command | j, ioaddr);
4898 udelay(1);
4899 outl(command | MII_MDC | j, ioaddr);
4900 udelay(1);
4901 }
4902
4903 static int
4904 getfrom_mii(u32 command, u_long ioaddr)
4905 {
4906 outl(command, ioaddr);
4907 udelay(1);
4908 outl(command | MII_MDC, ioaddr);
4909 udelay(1);
4910
4911 return (inl(ioaddr) >> 19) & 1;
4912 }
4913
4914 /*
4915 ** Here's 3 ways to calculate the OUI from the ID registers.
4916 */
4917 static int
4918 mii_get_oui(u_char phyaddr, u_long ioaddr)
4919 {
4920 /*
4921 union {
4922 u_short reg;
4923 u_char breg[2];
4924 } a;
4925 int i, r2, r3, ret=0;*/
4926 int r2, r3;
4927
4928 /* Read r2 and r3 */
4929 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4930 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4931 /* SEEQ and Cypress way * /
4932 / * Shuffle r2 and r3 * /
4933 a.reg=0;
4934 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4935 r2 = ((r2>>2)&0x3fff);
4936
4937 / * Bit reverse r3 * /
4938 for (i=0;i<8;i++) {
4939 ret<<=1;
4940 ret |= (r3&1);
4941 r3>>=1;
4942 }
4943
4944 / * Bit reverse r2 * /
4945 for (i=0;i<16;i++) {
4946 a.reg<<=1;
4947 a.reg |= (r2&1);
4948 r2>>=1;
4949 }
4950
4951 / * Swap r2 bytes * /
4952 i=a.breg[0];
4953 a.breg[0]=a.breg[1];
4954 a.breg[1]=i;
4955
4956 return (a.reg<<8)|ret; */ /* SEEQ and Cypress way */
4957 /* return (r2<<6)|(u_int)(r3>>10); */ /* NATIONAL and BROADCOM way */
4958 return r2; /* (I did it) My way */
4959 }
4960
4961 /*
4962 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4963 */
4964 static int
4965 mii_get_phy(struct net_device *dev)
4966 {
4967 struct de4x5_private *lp = netdev_priv(dev);
4968 u_long iobase = dev->base_addr;
4969 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4970 int id;
4971
4972 lp->active = 0;
4973 lp->useMII = true;
4974
4975 /* Search the MII address space for possible PHY devices */
4976 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4977 lp->phy[lp->active].addr = i;
4978 if (i==0) n++; /* Count cycles */
4979 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
4980 id = mii_get_oui(i, DE4X5_MII);
4981 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
4982 for (j=0; j<limit; j++) { /* Search PHY table */
4983 if (id != phy_info[j].id) continue; /* ID match? */
4984 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4985 if (k < DE4X5_MAX_PHY) {
4986 memcpy((char *)&lp->phy[k],
4987 (char *)&phy_info[j], sizeof(struct phy_table));
4988 lp->phy[k].addr = i;
4989 lp->mii_cnt++;
4990 lp->active++;
4991 } else {
4992 goto purgatory; /* Stop the search */
4993 }
4994 break;
4995 }
4996 if ((j == limit) && (i < DE4X5_MAX_MII)) {
4997 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4998 lp->phy[k].addr = i;
4999 lp->phy[k].id = id;
5000 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5001 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5002 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5003 lp->mii_cnt++;
5004 lp->active++;
5005 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5006 j = de4x5_debug;
5007 de4x5_debug |= DEBUG_MII;
5008 de4x5_dbg_mii(dev, k);
5009 de4x5_debug = j;
5010 printk("\n");
5011 }
5012 }
5013 purgatory:
5014 lp->active = 0;
5015 if (lp->phy[0].id) { /* Reset the PHY devices */
5016 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5017 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5018 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5019
5020 de4x5_dbg_mii(dev, k);
5021 }
5022 }
5023 if (!lp->mii_cnt) lp->useMII = false;
5024
5025 return lp->mii_cnt;
5026 }
5027
5028 static char *
5029 build_setup_frame(struct net_device *dev, int mode)
5030 {
5031 struct de4x5_private *lp = netdev_priv(dev);
5032 int i;
5033 char *pa = lp->setup_frame;
5034
5035 /* Initialise the setup frame */
5036 if (mode == ALL) {
5037 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5038 }
5039
5040 if (lp->setup_f == HASH_PERF) {
5041 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5042 *(pa + i) = dev->dev_addr[i]; /* Host address */
5043 if (i & 0x01) pa += 2;
5044 }
5045 *(lp->setup_frame + (DE4X5_HASH_TABLE_LEN >> 3) - 3) = 0x80;
5046 } else {
5047 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5048 *(pa + (i&1)) = dev->dev_addr[i];
5049 if (i & 0x01) pa += 4;
5050 }
5051 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5052 *(pa + (i&1)) = (char) 0xff;
5053 if (i & 0x01) pa += 4;
5054 }
5055 }
5056
5057 return pa; /* Points to the next entry */
5058 }
5059
5060 static void
5061 disable_ast(struct net_device *dev)
5062 {
5063 struct de4x5_private *lp = netdev_priv(dev);
5064 del_timer_sync(&lp->timer);
5065 }
5066
5067 static long
5068 de4x5_switch_mac_port(struct net_device *dev)
5069 {
5070 struct de4x5_private *lp = netdev_priv(dev);
5071 u_long iobase = dev->base_addr;
5072 s32 omr;
5073
5074 STOP_DE4X5;
5075
5076 /* Assert the OMR_PS bit in CSR6 */
5077 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5078 OMR_FDX));
5079 omr |= lp->infoblock_csr6;
5080 if (omr & OMR_PS) omr |= OMR_HBD;
5081 outl(omr, DE4X5_OMR);
5082
5083 /* Soft Reset */
5084 RESET_DE4X5;
5085
5086 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5087 if (lp->chipset == DC21140) {
5088 gep_wr(lp->cache.gepc, dev);
5089 gep_wr(lp->cache.gep, dev);
5090 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5091 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5092 }
5093
5094 /* Restore CSR6 */
5095 outl(omr, DE4X5_OMR);
5096
5097 /* Reset CSR8 */
5098 inl(DE4X5_MFC);
5099
5100 return omr;
5101 }
5102
5103 static void
5104 gep_wr(s32 data, struct net_device *dev)
5105 {
5106 struct de4x5_private *lp = netdev_priv(dev);
5107 u_long iobase = dev->base_addr;
5108
5109 if (lp->chipset == DC21140) {
5110 outl(data, DE4X5_GEP);
5111 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5112 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5113 }
5114 }
5115
5116 static int
5117 gep_rd(struct net_device *dev)
5118 {
5119 struct de4x5_private *lp = netdev_priv(dev);
5120 u_long iobase = dev->base_addr;
5121
5122 if (lp->chipset == DC21140) {
5123 return inl(DE4X5_GEP);
5124 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5125 return inl(DE4X5_SIGR) & 0x000fffff;
5126 }
5127
5128 return 0;
5129 }
5130
5131 static void
5132 yawn(struct net_device *dev, int state)
5133 {
5134 struct de4x5_private *lp = netdev_priv(dev);
5135 u_long iobase = dev->base_addr;
5136
5137 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5138
5139 if(lp->bus == EISA) {
5140 switch(state) {
5141 case WAKEUP:
5142 outb(WAKEUP, PCI_CFPM);
5143 mdelay(10);
5144 break;
5145
5146 case SNOOZE:
5147 outb(SNOOZE, PCI_CFPM);
5148 break;
5149
5150 case SLEEP:
5151 outl(0, DE4X5_SICR);
5152 outb(SLEEP, PCI_CFPM);
5153 break;
5154 }
5155 } else {
5156 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5157 switch(state) {
5158 case WAKEUP:
5159 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5160 mdelay(10);
5161 break;
5162
5163 case SNOOZE:
5164 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5165 break;
5166
5167 case SLEEP:
5168 outl(0, DE4X5_SICR);
5169 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5170 break;
5171 }
5172 }
5173 }
5174
5175 static void
5176 de4x5_parse_params(struct net_device *dev)
5177 {
5178 struct de4x5_private *lp = netdev_priv(dev);
5179 char *p, *q, t;
5180
5181 lp->params.fdx = false;
5182 lp->params.autosense = AUTO;
5183
5184 if (args == NULL) return;
5185
5186 if ((p = strstr(args, dev->name))) {
5187 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5188 t = *q;
5189 *q = '\0';
5190
5191 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5192
5193 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5194 if (strstr(p, "TP_NW")) {
5195 lp->params.autosense = TP_NW;
5196 } else if (strstr(p, "TP")) {
5197 lp->params.autosense = TP;
5198 } else if (strstr(p, "BNC_AUI")) {
5199 lp->params.autosense = BNC;
5200 } else if (strstr(p, "BNC")) {
5201 lp->params.autosense = BNC;
5202 } else if (strstr(p, "AUI")) {
5203 lp->params.autosense = AUI;
5204 } else if (strstr(p, "10Mb")) {
5205 lp->params.autosense = _10Mb;
5206 } else if (strstr(p, "100Mb")) {
5207 lp->params.autosense = _100Mb;
5208 } else if (strstr(p, "AUTO")) {
5209 lp->params.autosense = AUTO;
5210 }
5211 }
5212 *q = t;
5213 }
5214 }
5215
5216 static void
5217 de4x5_dbg_open(struct net_device *dev)
5218 {
5219 struct de4x5_private *lp = netdev_priv(dev);
5220 int i;
5221
5222 if (de4x5_debug & DEBUG_OPEN) {
5223 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5224 printk("\tphysical address: %pM\n", dev->dev_addr);
5225 printk("Descriptor head addresses:\n");
5226 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5227 printk("Descriptor addresses:\nRX: ");
5228 for (i=0;i<lp->rxRingSize-1;i++){
5229 if (i < 3) {
5230 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5231 }
5232 }
5233 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5234 printk("TX: ");
5235 for (i=0;i<lp->txRingSize-1;i++){
5236 if (i < 3) {
5237 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5238 }
5239 }
5240 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5241 printk("Descriptor buffers:\nRX: ");
5242 for (i=0;i<lp->rxRingSize-1;i++){
5243 if (i < 3) {
5244 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5245 }
5246 }
5247 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5248 printk("TX: ");
5249 for (i=0;i<lp->txRingSize-1;i++){
5250 if (i < 3) {
5251 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5252 }
5253 }
5254 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5255 printk("Ring size:\nRX: %d\nTX: %d\n",
5256 (short)lp->rxRingSize,
5257 (short)lp->txRingSize);
5258 }
5259 }
5260
5261 static void
5262 de4x5_dbg_mii(struct net_device *dev, int k)
5263 {
5264 struct de4x5_private *lp = netdev_priv(dev);
5265 u_long iobase = dev->base_addr;
5266
5267 if (de4x5_debug & DEBUG_MII) {
5268 printk("\nMII device address: %d\n", lp->phy[k].addr);
5269 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5270 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5271 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5272 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5273 if (lp->phy[k].id != BROADCOM_T4) {
5274 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5275 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5276 }
5277 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5278 if (lp->phy[k].id != BROADCOM_T4) {
5279 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5280 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5281 } else {
5282 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5283 }
5284 }
5285 }
5286
5287 static void
5288 de4x5_dbg_media(struct net_device *dev)
5289 {
5290 struct de4x5_private *lp = netdev_priv(dev);
5291
5292 if (lp->media != lp->c_media) {
5293 if (de4x5_debug & DEBUG_MEDIA) {
5294 printk("%s: media is %s%s\n", dev->name,
5295 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5296 (lp->media == TP ? "TP" :
5297 (lp->media == ANS ? "TP/Nway" :
5298 (lp->media == BNC ? "BNC" :
5299 (lp->media == AUI ? "AUI" :
5300 (lp->media == BNC_AUI ? "BNC/AUI" :
5301 (lp->media == EXT_SIA ? "EXT SIA" :
5302 (lp->media == _100Mb ? "100Mb/s" :
5303 (lp->media == _10Mb ? "10Mb/s" :
5304 "???"
5305 ))))))))), (lp->fdx?" full duplex.":"."));
5306 }
5307 lp->c_media = lp->media;
5308 }
5309 }
5310
5311 static void
5312 de4x5_dbg_srom(struct de4x5_srom *p)
5313 {
5314 int i;
5315
5316 if (de4x5_debug & DEBUG_SROM) {
5317 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5318 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5319 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5320 printk("SROM version: %02x\n", (u_char)(p->version));
5321 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5322
5323 printk("Hardware Address: %pM\n", p->ieee_addr);
5324 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5325 for (i=0; i<64; i++) {
5326 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5327 }
5328 }
5329 }
5330
5331 static void
5332 de4x5_dbg_rx(struct sk_buff *skb, int len)
5333 {
5334 int i, j;
5335
5336 if (de4x5_debug & DEBUG_RX) {
5337 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5338 skb->data, &skb->data[6],
5339 (u_char)skb->data[12],
5340 (u_char)skb->data[13],
5341 len);
5342 for (j=0; len>0;j+=16, len-=16) {
5343 printk(" %03x: ",j);
5344 for (i=0; i<16 && i<len; i++) {
5345 printk("%02x ",(u_char)skb->data[i+j]);
5346 }
5347 printk("\n");
5348 }
5349 }
5350 }
5351
5352 /*
5353 ** Perform IOCTL call functions here. Some are privileged operations and the
5354 ** effective uid is checked in those cases. In the normal course of events
5355 ** this function is only used for my testing.
5356 */
5357 static int
5358 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5359 {
5360 struct de4x5_private *lp = netdev_priv(dev);
5361 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5362 u_long iobase = dev->base_addr;
5363 int i, j, status = 0;
5364 s32 omr;
5365 union {
5366 u8 addr[144];
5367 u16 sval[72];
5368 u32 lval[36];
5369 } tmp;
5370 u_long flags = 0;
5371
5372 switch(ioc->cmd) {
5373 case DE4X5_GET_HWADDR: /* Get the hardware address */
5374 ioc->len = ETH_ALEN;
5375 for (i=0; i<ETH_ALEN; i++) {
5376 tmp.addr[i] = dev->dev_addr[i];
5377 }
5378 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5379 break;
5380
5381 case DE4X5_SET_HWADDR: /* Set the hardware address */
5382 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5383 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5384 if (netif_queue_stopped(dev))
5385 return -EBUSY;
5386 netif_stop_queue(dev);
5387 for (i=0; i<ETH_ALEN; i++) {
5388 dev->dev_addr[i] = tmp.addr[i];
5389 }
5390 build_setup_frame(dev, PHYS_ADDR_ONLY);
5391 /* Set up the descriptor and give ownership to the card */
5392 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5393 SETUP_FRAME_LEN, (struct sk_buff *)1);
5394 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5395 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5396 netif_wake_queue(dev); /* Unlock the TX ring */
5397 break;
5398
5399 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5400 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5401 printk("%s: Boo!\n", dev->name);
5402 break;
5403
5404 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5405 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5406 omr = inl(DE4X5_OMR);
5407 omr |= OMR_PM;
5408 outl(omr, DE4X5_OMR);
5409 break;
5410
5411 case DE4X5_GET_STATS: /* Get the driver statistics */
5412 {
5413 struct pkt_stats statbuf;
5414 ioc->len = sizeof(statbuf);
5415 spin_lock_irqsave(&lp->lock, flags);
5416 memcpy(&statbuf, &lp->pktStats, ioc->len);
5417 spin_unlock_irqrestore(&lp->lock, flags);
5418 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5419 return -EFAULT;
5420 break;
5421 }
5422 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5423 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5424 spin_lock_irqsave(&lp->lock, flags);
5425 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5426 spin_unlock_irqrestore(&lp->lock, flags);
5427 break;
5428
5429 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5430 tmp.addr[0] = inl(DE4X5_OMR);
5431 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5432 break;
5433
5434 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5435 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5436 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5437 outl(tmp.addr[0], DE4X5_OMR);
5438 break;
5439
5440 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5441 j = 0;
5442 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5443 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5444 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5445 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5446 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5447 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5448 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5449 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5450 ioc->len = j;
5451 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5452 return -EFAULT;
5453 break;
5454
5455 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5456 /*
5457 case DE4X5_DUMP:
5458 j = 0;
5459 tmp.addr[j++] = dev->irq;
5460 for (i=0; i<ETH_ALEN; i++) {
5461 tmp.addr[j++] = dev->dev_addr[i];
5462 }
5463 tmp.addr[j++] = lp->rxRingSize;
5464 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5465 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5466
5467 for (i=0;i<lp->rxRingSize-1;i++){
5468 if (i < 3) {
5469 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5470 }
5471 }
5472 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5473 for (i=0;i<lp->txRingSize-1;i++){
5474 if (i < 3) {
5475 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5476 }
5477 }
5478 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5479
5480 for (i=0;i<lp->rxRingSize-1;i++){
5481 if (i < 3) {
5482 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5483 }
5484 }
5485 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5486 for (i=0;i<lp->txRingSize-1;i++){
5487 if (i < 3) {
5488 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5489 }
5490 }
5491 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5492
5493 for (i=0;i<lp->rxRingSize;i++){
5494 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5495 }
5496 for (i=0;i<lp->txRingSize;i++){
5497 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5498 }
5499
5500 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5501 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5502 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5503 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5504 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5505 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5506 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5507 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5508 tmp.lval[j>>2] = lp->chipset; j+=4;
5509 if (lp->chipset == DC21140) {
5510 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5511 } else {
5512 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5513 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5514 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5515 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5516 }
5517 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5518 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5519 tmp.lval[j>>2] = lp->active; j+=4;
5520 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5521 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5522 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5523 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5524 if (lp->phy[lp->active].id != BROADCOM_T4) {
5525 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5526 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5527 }
5528 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5529 if (lp->phy[lp->active].id != BROADCOM_T4) {
5530 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5531 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5532 } else {
5533 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5534 }
5535 }
5536
5537 tmp.addr[j++] = lp->txRingSize;
5538 tmp.addr[j++] = netif_queue_stopped(dev);
5539
5540 ioc->len = j;
5541 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5542 break;
5543
5544 */
5545 default:
5546 return -EOPNOTSUPP;
5547 }
5548
5549 return status;
5550 }
5551
5552 static int __init de4x5_module_init (void)
5553 {
5554 int err = 0;
5555
5556 #ifdef CONFIG_PCI
5557 err = pci_register_driver(&de4x5_pci_driver);
5558 #endif
5559 #ifdef CONFIG_EISA
5560 err |= eisa_driver_register (&de4x5_eisa_driver);
5561 #endif
5562
5563 return err;
5564 }
5565
5566 static void __exit de4x5_module_exit (void)
5567 {
5568 #ifdef CONFIG_PCI
5569 pci_unregister_driver (&de4x5_pci_driver);
5570 #endif
5571 #ifdef CONFIG_EISA
5572 eisa_driver_unregister (&de4x5_eisa_driver);
5573 #endif
5574 }
5575
5576 module_init (de4x5_module_init);
5577 module_exit (de4x5_module_exit);
Linux with added FPC-III support