drivers/net/ethernet/ezchip/nps_enet.c

   1 /*
   2  * Copyright(c) 2015 EZchip Technologies.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_platform.h>
  23 #include "nps_enet.h"
  24
  25 #define DRV_NAME                        "nps_mgt_enet"
  26
  27 static inline bool nps_enet_is_tx_pending(struct nps_enet_priv *priv)
  28 {
  29         u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
  30         u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
  31
  32         return (!tx_ctrl_ct && priv->tx_skb);
  33 }
  34
  35 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
  36 {
  37         struct nps_enet_priv *priv = netdev_priv(ndev);
  38         u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
  39
  40         /* Empty Rx FIFO buffer by reading all words */
  41         for (i = 0; i < len; i++)
  42                 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
  43 }
  44
  45 static void nps_enet_read_rx_fifo(struct net_device *ndev,
  46                                   unsigned char *dst, u32 length)
  47 {
  48         struct nps_enet_priv *priv = netdev_priv(ndev);
  49         s32 i, last = length & (sizeof(u32) - 1);
  50         u32 *reg = (u32 *)dst, len = length / sizeof(u32);
  51         bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
  52
  53         /* In case dst is not aligned we need an intermediate buffer */
  54         if (dst_is_aligned) {
  55                 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
  56                 reg += len;
  57         } else { /* !dst_is_aligned */
  58                 for (i = 0; i < len; i++, reg++) {
  59                         u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
  60
  61                         put_unaligned_be32(buf, reg);
  62                 }
  63         }
  64         /* copy last bytes (if any) */
  65         if (last) {
  66                 u32 buf;
  67
  68                 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
  69                 memcpy((u8 *)reg, &buf, last);
  70         }
  71 }
  72
  73 static u32 nps_enet_rx_handler(struct net_device *ndev)
  74 {
  75         u32 frame_len, err = 0;
  76         u32 work_done = 0;
  77         struct nps_enet_priv *priv = netdev_priv(ndev);
  78         struct sk_buff *skb;
  79         u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
  80         u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
  81         u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
  82         u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
  83
  84         frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
  85
  86         /* Check if we got RX */
  87         if (!rx_ctrl_cr)
  88                 return work_done;
  89
  90         /* If we got here there is a work for us */
  91         work_done++;
  92
  93         /* Check Rx error */
  94         if (rx_ctrl_er) {
  95                 ndev->stats.rx_errors++;
  96                 err = 1;
  97         }
  98
  99         /* Check Rx CRC error */
 100         if (rx_ctrl_crc) {
 101                 ndev->stats.rx_crc_errors++;
 102                 ndev->stats.rx_dropped++;
 103                 err = 1;
 104         }
 105
 106         /* Check Frame length Min 64b */
 107         if (unlikely(frame_len < ETH_ZLEN)) {
 108                 ndev->stats.rx_length_errors++;
 109                 ndev->stats.rx_dropped++;
 110                 err = 1;
 111         }
 112
 113         if (err)
 114                 goto rx_irq_clean;
 115
 116         /* Skb allocation */
 117         skb = netdev_alloc_skb_ip_align(ndev, frame_len);
 118         if (unlikely(!skb)) {
 119                 ndev->stats.rx_errors++;
 120                 ndev->stats.rx_dropped++;
 121                 goto rx_irq_clean;
 122         }
 123
 124         /* Copy frame from Rx fifo into the skb */
 125         nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
 126
 127         skb_put(skb, frame_len);
 128         skb->protocol = eth_type_trans(skb, ndev);
 129         skb->ip_summed = CHECKSUM_UNNECESSARY;
 130
 131         ndev->stats.rx_packets++;
 132         ndev->stats.rx_bytes += frame_len;
 133         netif_receive_skb(skb);
 134
 135         goto rx_irq_frame_done;
 136
 137 rx_irq_clean:
 138         /* Clean Rx fifo */
 139         nps_enet_clean_rx_fifo(ndev, frame_len);
 140
 141 rx_irq_frame_done:
 142         /* Ack Rx ctrl register */
 143         nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
 144
 145         return work_done;
 146 }
 147
 148 static void nps_enet_tx_handler(struct net_device *ndev)
 149 {
 150         struct nps_enet_priv *priv = netdev_priv(ndev);
 151         u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
 152         u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
 153         u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
 154
 155         /* Check if we got TX */
 156         if (!nps_enet_is_tx_pending(priv))
 157                 return;
 158
 159         /* Ack Tx ctrl register */
 160         nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
 161
 162         /* Check Tx transmit error */
 163         if (unlikely(tx_ctrl_et)) {
 164                 ndev->stats.tx_errors++;
 165         } else {
 166                 ndev->stats.tx_packets++;
 167                 ndev->stats.tx_bytes += tx_ctrl_nt;
 168         }
 169
 170         dev_kfree_skb(priv->tx_skb);
 171         priv->tx_skb = NULL;
 172
 173         if (netif_queue_stopped(ndev))
 174                 netif_wake_queue(ndev);
 175 }
 176
 177 /**
 178  * nps_enet_poll - NAPI poll handler.
 179  * @napi:       Pointer to napi_struct structure.
 180  * @budget:     How many frames to process on one call.
 181  *
 182  * returns:     Number of processed frames
 183  */
 184 static int nps_enet_poll(struct napi_struct *napi, int budget)
 185 {
 186         struct net_device *ndev = napi->dev;
 187         struct nps_enet_priv *priv = netdev_priv(ndev);
 188         u32 work_done;
 189
 190         nps_enet_tx_handler(ndev);
 191         work_done = nps_enet_rx_handler(ndev);
 192         if ((work_done < budget) && napi_complete_done(napi, work_done)) {
 193                 u32 buf_int_enable_value = 0;
 194
 195                 /* set tx_done and rx_rdy bits */
 196                 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
 197                 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
 198
 199                 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
 200                                  buf_int_enable_value);
 201
 202                 /* in case we will get a tx interrupt while interrupts
 203                  * are masked, we will lose it since the tx is edge interrupt.
 204                  * specifically, while executing the code section above,
 205                  * between nps_enet_tx_handler and the interrupts enable, all
 206                  * tx requests will be stuck until we will get an rx interrupt.
 207                  * the two code lines below will solve this situation by
 208                  * re-adding ourselves to the poll list.
 209                  */
 210                 if (nps_enet_is_tx_pending(priv)) {
 211                         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
 212                         napi_reschedule(napi);
 213                 }
 214         }
 215
 216         return work_done;
 217 }
 218
 219 /**
 220  * nps_enet_irq_handler - Global interrupt handler for ENET.
 221  * @irq:                irq number.
 222  * @dev_instance:       device instance.
 223  *
 224  * returns: IRQ_HANDLED for all cases.
 225  *
 226  * EZchip ENET has 2 interrupt causes, and depending on bits raised in
 227  * CTRL registers we may tell what is a reason for interrupt to fire up.
 228  * We got one for RX and the other for TX (completion).
 229  */
 230 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
 231 {
 232         struct net_device *ndev = dev_instance;
 233         struct nps_enet_priv *priv = netdev_priv(ndev);
 234         u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
 235         u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
 236
 237         if (nps_enet_is_tx_pending(priv) || rx_ctrl_cr)
 238                 if (likely(napi_schedule_prep(&priv->napi))) {
 239                         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
 240                         __napi_schedule(&priv->napi);
 241                 }
 242
 243         return IRQ_HANDLED;
 244 }
 245
 246 static void nps_enet_set_hw_mac_address(struct net_device *ndev)
 247 {
 248         struct nps_enet_priv *priv = netdev_priv(ndev);
 249         u32 ge_mac_cfg_1_value = 0;
 250         u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
 251
 252         /* set MAC address in HW */
 253         ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
 254         ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
 255         ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
 256         ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
 257         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
 258                  | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
 259         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
 260                  | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
 261
 262         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
 263                          ge_mac_cfg_1_value);
 264
 265         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
 266                          *ge_mac_cfg_2_value);
 267 }
 268
 269 /**
 270  * nps_enet_hw_reset - Reset the network device.
 271  * @ndev:       Pointer to the network device.
 272  *
 273  * This function reset the PCS and TX fifo.
 274  * The programming model is to set the relevant reset bits
 275  * wait for some time for this to propagate and then unset
 276  * the reset bits. This way we ensure that reset procedure
 277  * is done successfully by device.
 278  */
 279 static void nps_enet_hw_reset(struct net_device *ndev)
 280 {
 281         struct nps_enet_priv *priv = netdev_priv(ndev);
 282         u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
 283
 284         /* Pcs reset sequence*/
 285         ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
 286         nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
 287         usleep_range(10, 20);
 288         ge_rst_value = 0;
 289         nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
 290
 291         /* Tx fifo reset sequence */
 292         phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
 293         phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
 294         nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
 295                          phase_fifo_ctl_value);
 296         usleep_range(10, 20);
 297         phase_fifo_ctl_value = 0;
 298         nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
 299                          phase_fifo_ctl_value);
 300 }
 301
 302 static void nps_enet_hw_enable_control(struct net_device *ndev)
 303 {
 304         struct nps_enet_priv *priv = netdev_priv(ndev);
 305         u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
 306         u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
 307         u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
 308         s32 max_frame_length;
 309
 310         /* Enable Rx and Tx statistics */
 311         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
 312                  | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
 313
 314         /* Discard packets with different MAC address */
 315         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 316                  | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
 317
 318         /* Discard multicast packets */
 319         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 320                  | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
 321
 322         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
 323                          *ge_mac_cfg_2_value);
 324
 325         /* Discard Packets bigger than max frame length */
 326         max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
 327         if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
 328                 *ge_mac_cfg_3_value =
 329                          (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
 330                          | max_frame_length << CFG_3_MAX_LEN_SHIFT;
 331         }
 332
 333         /* Enable interrupts */
 334         buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
 335         buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
 336         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
 337                          buf_int_enable_value);
 338
 339         /* Write device MAC address to HW */
 340         nps_enet_set_hw_mac_address(ndev);
 341
 342         /* Rx and Tx HW features */
 343         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
 344         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
 345         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
 346
 347         /* IFG configuration */
 348         ge_mac_cfg_0_value |=
 349                  NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
 350         ge_mac_cfg_0_value |=
 351                  NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
 352
 353         /* preamble configuration */
 354         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
 355         ge_mac_cfg_0_value |=
 356                  NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
 357
 358         /* enable flow control frames */
 359         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
 360         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
 361         ge_mac_cfg_0_value |=
 362                  NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
 363         *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
 364                  | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
 365
 366         /* Enable Rx and Tx */
 367         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
 368         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
 369
 370         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
 371                          *ge_mac_cfg_3_value);
 372         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
 373                          ge_mac_cfg_0_value);
 374 }
 375
 376 static void nps_enet_hw_disable_control(struct net_device *ndev)
 377 {
 378         struct nps_enet_priv *priv = netdev_priv(ndev);
 379
 380         /* Disable interrupts */
 381         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
 382
 383         /* Disable Rx and Tx */
 384         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
 385 }
 386
 387 static void nps_enet_send_frame(struct net_device *ndev,
 388                                 struct sk_buff *skb)
 389 {
 390         struct nps_enet_priv *priv = netdev_priv(ndev);
 391         u32 tx_ctrl_value = 0;
 392         short length = skb->len;
 393         u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
 394         u32 *src = (void *)skb->data;
 395         bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
 396
 397         /* In case src is not aligned we need an intermediate buffer */
 398         if (src_is_aligned)
 399                 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
 400         else /* !src_is_aligned */
 401                 for (i = 0; i < len; i++, src++)
 402                         nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
 403                                          get_unaligned_be32(src));
 404
 405         /* Write the length of the Frame */
 406         tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
 407
 408         tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
 409         /* Send Frame */
 410         nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
 411 }
 412
 413 /**
 414  * nps_enet_set_mac_address - Set the MAC address for this device.
 415  * @ndev:       Pointer to net_device structure.
 416  * @p:          6 byte Address to be written as MAC address.
 417  *
 418  * This function copies the HW address from the sockaddr structure to the
 419  * net_device structure and updates the address in HW.
 420  *
 421  * returns:     -EBUSY if the net device is busy or 0 if the address is set
 422  *              successfully.
 423  */
 424 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
 425 {
 426         struct sockaddr *addr = p;
 427         s32 res;
 428
 429         if (netif_running(ndev))
 430                 return -EBUSY;
 431
 432         res = eth_mac_addr(ndev, p);
 433         if (!res) {
 434                 ether_addr_copy(ndev->dev_addr, addr->sa_data);
 435                 nps_enet_set_hw_mac_address(ndev);
 436         }
 437
 438         return res;
 439 }
 440
 441 /**
 442  * nps_enet_set_rx_mode - Change the receive filtering mode.
 443  * @ndev:       Pointer to the network device.
 444  *
 445  * This function enables/disables promiscuous mode
 446  */
 447 static void nps_enet_set_rx_mode(struct net_device *ndev)
 448 {
 449         struct nps_enet_priv *priv = netdev_priv(ndev);
 450         u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
 451
 452         if (ndev->flags & IFF_PROMISC) {
 453                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 454                          | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
 455                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 456                          | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
 457
 458         } else {
 459                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 460                          | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
 461                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 462                          | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
 463         }
 464
 465         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
 466 }
 467
 468 /**
 469  * nps_enet_open - Open the network device.
 470  * @ndev:       Pointer to the network device.
 471  *
 472  * returns: 0, on success or non-zero error value on failure.
 473  *
 474  * This function sets the MAC address, requests and enables an IRQ
 475  * for the ENET device and starts the Tx queue.
 476  */
 477 static s32 nps_enet_open(struct net_device *ndev)
 478 {
 479         struct nps_enet_priv *priv = netdev_priv(ndev);
 480         s32 err;
 481
 482         /* Reset private variables */
 483         priv->tx_skb = NULL;
 484         priv->ge_mac_cfg_2_value = 0;
 485         priv->ge_mac_cfg_3_value = 0;
 486
 487         /* ge_mac_cfg_3 default values */
 488         priv->ge_mac_cfg_3_value |=
 489                  NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
 490
 491         priv->ge_mac_cfg_3_value |=
 492                  NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
 493
 494         /* Disable HW device */
 495         nps_enet_hw_disable_control(ndev);
 496
 497         /* irq Rx allocation */
 498         err = request_irq(priv->irq, nps_enet_irq_handler,
 499                           0, "enet-rx-tx", ndev);
 500         if (err)
 501                 return err;
 502
 503         napi_enable(&priv->napi);
 504
 505         /* Enable HW device */
 506         nps_enet_hw_reset(ndev);
 507         nps_enet_hw_enable_control(ndev);
 508
 509         netif_start_queue(ndev);
 510
 511         return 0;
 512 }
 513
 514 /**
 515  * nps_enet_stop - Close the network device.
 516  * @ndev:       Pointer to the network device.
 517  *
 518  * This function stops the Tx queue, disables interrupts for the ENET device.
 519  */
 520 static s32 nps_enet_stop(struct net_device *ndev)
 521 {
 522         struct nps_enet_priv *priv = netdev_priv(ndev);
 523
 524         napi_disable(&priv->napi);
 525         netif_stop_queue(ndev);
 526         nps_enet_hw_disable_control(ndev);
 527         free_irq(priv->irq, ndev);
 528
 529         return 0;
 530 }
 531
 532 /**
 533  * nps_enet_start_xmit - Starts the data transmission.
 534  * @skb:        sk_buff pointer that contains data to be Transmitted.
 535  * @ndev:       Pointer to net_device structure.
 536  *
 537  * returns: NETDEV_TX_OK, on success
 538  *              NETDEV_TX_BUSY, if any of the descriptors are not free.
 539  *
 540  * This function is invoked from upper layers to initiate transmission.
 541  */
 542 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
 543                                        struct net_device *ndev)
 544 {
 545         struct nps_enet_priv *priv = netdev_priv(ndev);
 546
 547         /* This driver handles one frame at a time  */
 548         netif_stop_queue(ndev);
 549
 550         priv->tx_skb = skb;
 551
 552         /* make sure tx_skb is actually written to the memory
 553          * before the HW is informed and the IRQ is fired.
 554          */
 555         wmb();
 556
 557         nps_enet_send_frame(ndev, skb);
 558
 559         return NETDEV_TX_OK;
 560 }
 561
 562 #ifdef CONFIG_NET_POLL_CONTROLLER
 563 static void nps_enet_poll_controller(struct net_device *ndev)
 564 {
 565         disable_irq(ndev->irq);
 566         nps_enet_irq_handler(ndev->irq, ndev);
 567         enable_irq(ndev->irq);
 568 }
 569 #endif
 570
 571 static const struct net_device_ops nps_netdev_ops = {
 572         .ndo_open               = nps_enet_open,
 573         .ndo_stop               = nps_enet_stop,
 574         .ndo_start_xmit         = nps_enet_start_xmit,
 575         .ndo_set_mac_address    = nps_enet_set_mac_address,
 576         .ndo_set_rx_mode        = nps_enet_set_rx_mode,
 577 #ifdef CONFIG_NET_POLL_CONTROLLER
 578         .ndo_poll_controller    = nps_enet_poll_controller,
 579 #endif
 580 };
 581
 582 static s32 nps_enet_probe(struct platform_device *pdev)
 583 {
 584         struct device *dev = &pdev->dev;
 585         struct net_device *ndev;
 586         struct nps_enet_priv *priv;
 587         s32 err = 0;
 588         const char *mac_addr;
 589         struct resource *res_regs;
 590
 591         if (!dev->of_node)
 592                 return -ENODEV;
 593
 594         ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
 595         if (!ndev)
 596                 return -ENOMEM;
 597
 598         platform_set_drvdata(pdev, ndev);
 599         SET_NETDEV_DEV(ndev, dev);
 600         priv = netdev_priv(ndev);
 601
 602         /* The EZ NET specific entries in the device structure. */
 603         ndev->netdev_ops = &nps_netdev_ops;
 604         ndev->watchdog_timeo = (400 * HZ / 1000);
 605         /* FIXME :: no multicast support yet */
 606         ndev->flags &= ~IFF_MULTICAST;
 607
 608         res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 609         priv->regs_base = devm_ioremap_resource(dev, res_regs);
 610         if (IS_ERR(priv->regs_base)) {
 611                 err = PTR_ERR(priv->regs_base);
 612                 goto out_netdev;
 613         }
 614         dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
 615
 616         /* set kernel MAC address to dev */
 617         mac_addr = of_get_mac_address(dev->of_node);
 618         if (mac_addr)
 619                 ether_addr_copy(ndev->dev_addr, mac_addr);
 620         else
 621                 eth_hw_addr_random(ndev);
 622
 623         /* Get IRQ number */
 624         priv->irq = platform_get_irq(pdev, 0);
 625         if (!priv->irq) {
 626                 dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n");
 627                 err = -ENODEV;
 628                 goto out_netdev;
 629         }
 630
 631         netif_napi_add(ndev, &priv->napi, nps_enet_poll,
 632                        NPS_ENET_NAPI_POLL_WEIGHT);
 633
 634         /* Register the driver. Should be the last thing in probe */
 635         err = register_netdev(ndev);
 636         if (err) {
 637                 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
 638                         ndev->name, (s32)err);
 639                 goto out_netif_api;
 640         }
 641
 642         dev_info(dev, "(rx/tx=%d)\n", priv->irq);
 643         return 0;
 644
 645 out_netif_api:
 646         netif_napi_del(&priv->napi);
 647 out_netdev:
 648         if (err)
 649                 free_netdev(ndev);
 650
 651         return err;
 652 }
 653
 654 static s32 nps_enet_remove(struct platform_device *pdev)
 655 {
 656         struct net_device *ndev = platform_get_drvdata(pdev);
 657         struct nps_enet_priv *priv = netdev_priv(ndev);
 658
 659         unregister_netdev(ndev);
 660         free_netdev(ndev);
 661         netif_napi_del(&priv->napi);
 662
 663         return 0;
 664 }
 665
 666 static const struct of_device_id nps_enet_dt_ids[] = {
 667         { .compatible = "ezchip,nps-mgt-enet" },
 668         { /* Sentinel */ }
 669 };
 670 MODULE_DEVICE_TABLE(of, nps_enet_dt_ids);
 671
 672 static struct platform_driver nps_enet_driver = {
 673         .probe = nps_enet_probe,
 674         .remove = nps_enet_remove,
 675         .driver = {
 676                 .name = DRV_NAME,
 677                 .of_match_table  = nps_enet_dt_ids,
 678         },
 679 };
 680
 681 module_platform_driver(nps_enet_driver);
 682
 683 MODULE_AUTHOR("EZchip Semiconductor");
 684 MODULE_LICENSE("GPL v2");