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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / fealnx.c
blob766636a7c25e23167e5185cbe6f2c6bd6d9da043
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.52"
29 #define DRV_RELDATE "Sep-11-2006"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/init.h>
83 #include <linux/mii.h>
84 #include <linux/ethtool.h>
85 #include <linux/crc32.h>
86 #include <linux/delay.h>
87 #include <linux/bitops.h>
88
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/io.h>
91 #include <linux/uaccess.h>
92 #include <asm/byteorder.h>
93
94 /* These identify the driver base version and may not be removed. */
95 static const char version[] =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104
105 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106 /* This is only in the support-all-kernels source code. */
107
108 #define RUN_AT(x) (jiffies + (x))
109
110 MODULE_AUTHOR("Myson or whoever");
111 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112 MODULE_LICENSE("GPL");
113 module_param(max_interrupt_work, int, 0);
114 module_param(debug, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(multicast_filter_limit, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
119 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
120 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
121 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
122 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
123 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
124 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
125
126 enum {
127 MIN_REGION_SIZE = 136,
128 };
129
130 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
131 enum chip_capability_flags {
132 HAS_MII_XCVR,
133 HAS_CHIP_XCVR,
134 };
135
136 /* 89/6/13 add, */
137 /* for different PHY */
138 enum phy_type_flags {
139 MysonPHY = 1,
140 AhdocPHY = 2,
141 SeeqPHY = 3,
142 MarvellPHY = 4,
143 Myson981 = 5,
144 LevelOnePHY = 6,
145 OtherPHY = 10,
146 };
147
148 struct chip_info {
149 char *chip_name;
150 int flags;
151 };
152
153 static const struct chip_info skel_netdrv_tbl[] = {
154 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157 };
158
159 /* Offsets to the Command and Status Registers. */
160 enum fealnx_offsets {
161 PAR0 = 0x0, /* physical address 0-3 */
162 PAR1 = 0x04, /* physical address 4-5 */
163 MAR0 = 0x08, /* multicast address 0-3 */
164 MAR1 = 0x0C, /* multicast address 4-7 */
165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
167 TCRRCR = 0x18, /* receive & transmit configuration */
168 BCR = 0x1C, /* bus command */
169 TXPDR = 0x20, /* transmit polling demand */
170 RXPDR = 0x24, /* receive polling demand */
171 RXCWP = 0x28, /* receive current word pointer */
172 TXLBA = 0x2C, /* transmit list base address */
173 RXLBA = 0x30, /* receive list base address */
174 ISR = 0x34, /* interrupt status */
175 IMR = 0x38, /* interrupt mask */
176 FTH = 0x3C, /* flow control high/low threshold */
177 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178 TALLY = 0x44, /* tally counters for crc and mpa */
179 TSR = 0x48, /* tally counter for transmit status */
180 BMCRSR = 0x4c, /* basic mode control and status */
181 PHYIDENTIFIER = 0x50, /* phy identifier */
182 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183 partner ability */
184 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186 };
187
188 /* Bits in the interrupt status/enable registers. */
189 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190 enum intr_status_bits {
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
193 LSCStatus = 0x00008000, /* link status change */
194 ANCStatus = 0x00004000, /* autonegotiation completed */
195 FBE = 0x00002000, /* fatal bus error */
196 FBEMask = 0x00001800, /* mask bit12-11 */
197 ParityErr = 0x00000000, /* parity error */
198 TargetErr = 0x00001000, /* target abort */
199 MasterErr = 0x00000800, /* master error */
200 TUNF = 0x00000400, /* transmit underflow */
201 ROVF = 0x00000200, /* receive overflow */
202 ETI = 0x00000100, /* transmit early int */
203 ERI = 0x00000080, /* receive early int */
204 CNTOVF = 0x00000040, /* counter overflow */
205 RBU = 0x00000020, /* receive buffer unavailable */
206 TBU = 0x00000010, /* transmit buffer unavilable */
207 TI = 0x00000008, /* transmit interrupt */
208 RI = 0x00000004, /* receive interrupt */
209 RxErr = 0x00000002, /* receive error */
210 };
211
212 /* Bits in the NetworkConfig register, W for writing, R for reading */
213 /* FIXME: some names are invented by me. Marked with (name?) */
214 /* If you have docs and know bit names, please fix 'em */
215 enum rx_mode_bits {
216 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217 CR_W_FD = 0x00100000, /* full duplex */
218 CR_W_PS10 = 0x00080000, /* 10 mbit */
219 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222 CR_W_RXMODEMASK = 0x000000e0,
223 CR_W_PROM = 0x00000080, /* promiscuous mode */
224 CR_W_AB = 0x00000040, /* accept broadcast */
225 CR_W_AM = 0x00000020, /* accept mutlicast */
226 CR_W_ARP = 0x00000008, /* receive runt pkt */
227 CR_W_ALP = 0x00000004, /* receive long pkt */
228 CR_W_SEP = 0x00000002, /* receive error pkt */
229 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230
231 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232 CR_R_FD = 0x00100000, /* full duplex detected */
233 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235 };
236
237 /* The Tulip Rx and Tx buffer descriptors. */
238 struct fealnx_desc {
239 s32 status;
240 s32 control;
241 u32 buffer;
242 u32 next_desc;
243 struct fealnx_desc *next_desc_logical;
244 struct sk_buff *skbuff;
245 u32 reserved1;
246 u32 reserved2;
247 };
248
249 /* Bits in network_desc.status */
250 enum rx_desc_status_bits {
251 RXOWN = 0x80000000, /* own bit */
252 FLNGMASK = 0x0fff0000, /* frame length */
253 FLNGShift = 16,
254 MARSTATUS = 0x00004000, /* multicast address received */
255 BARSTATUS = 0x00002000, /* broadcast address received */
256 PHYSTATUS = 0x00001000, /* physical address received */
257 RXFSD = 0x00000800, /* first descriptor */
258 RXLSD = 0x00000400, /* last descriptor */
259 ErrorSummary = 0x80, /* error summary */
260 RUNT = 0x40, /* runt packet received */
261 LONG = 0x20, /* long packet received */
262 FAE = 0x10, /* frame align error */
263 CRC = 0x08, /* crc error */
264 RXER = 0x04, /* receive error */
265 };
266
267 enum rx_desc_control_bits {
268 RXIC = 0x00800000, /* interrupt control */
269 RBSShift = 0,
270 };
271
272 enum tx_desc_status_bits {
273 TXOWN = 0x80000000, /* own bit */
274 JABTO = 0x00004000, /* jabber timeout */
275 CSL = 0x00002000, /* carrier sense lost */
276 LC = 0x00001000, /* late collision */
277 EC = 0x00000800, /* excessive collision */
278 UDF = 0x00000400, /* fifo underflow */
279 DFR = 0x00000200, /* deferred */
280 HF = 0x00000100, /* heartbeat fail */
281 NCRMask = 0x000000ff, /* collision retry count */
282 NCRShift = 0,
283 };
284
285 enum tx_desc_control_bits {
286 TXIC = 0x80000000, /* interrupt control */
287 ETIControl = 0x40000000, /* early transmit interrupt */
288 TXLD = 0x20000000, /* last descriptor */
289 TXFD = 0x10000000, /* first descriptor */
290 CRCEnable = 0x08000000, /* crc control */
291 PADEnable = 0x04000000, /* padding control */
292 RetryTxLC = 0x02000000, /* retry late collision */
293 PKTSMask = 0x3ff800, /* packet size bit21-11 */
294 PKTSShift = 11,
295 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296 TBSShift = 0,
297 };
298
299 /* BootROM/EEPROM/MII Management Register */
300 #define MASK_MIIR_MII_READ 0x00000000
301 #define MASK_MIIR_MII_WRITE 0x00000008
302 #define MASK_MIIR_MII_MDO 0x00000004
303 #define MASK_MIIR_MII_MDI 0x00000002
304 #define MASK_MIIR_MII_MDC 0x00000001
305
306 /* ST+OP+PHYAD+REGAD+TA */
307 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309
310 /* ------------------------------------------------------------------------- */
311 /* Constants for Myson PHY */
312 /* ------------------------------------------------------------------------- */
313 #define MysonPHYID 0xd0000302
314 /* 89-7-27 add, (begin) */
315 #define MysonPHYID0 0x0302
316 #define StatusRegister 18
317 #define SPEED100 0x0400 // bit10
318 #define FULLMODE 0x0800 // bit11
319 /* 89-7-27 add, (end) */
320
321 /* ------------------------------------------------------------------------- */
322 /* Constants for Seeq 80225 PHY */
323 /* ------------------------------------------------------------------------- */
324 #define SeeqPHYID0 0x0016
325
326 #define MIIRegister18 18
327 #define SPD_DET_100 0x80
328 #define DPLX_DET_FULL 0x40
329
330 /* ------------------------------------------------------------------------- */
331 /* Constants for Ahdoc 101 PHY */
332 /* ------------------------------------------------------------------------- */
333 #define AhdocPHYID0 0x0022
334
335 #define DiagnosticReg 18
336 #define DPLX_FULL 0x0800
337 #define Speed_100 0x0400
338
339 /* 89/6/13 add, */
340 /* -------------------------------------------------------------------------- */
341 /* Constants */
342 /* -------------------------------------------------------------------------- */
343 #define MarvellPHYID0 0x0141
344 #define LevelOnePHYID0 0x0013
345
346 #define MII1000BaseTControlReg 9
347 #define MII1000BaseTStatusReg 10
348 #define SpecificReg 17
349
350 /* for 1000BaseT Control Register */
351 #define PHYAbletoPerform1000FullDuplex 0x0200
352 #define PHYAbletoPerform1000HalfDuplex 0x0100
353 #define PHY1000AbilityMask 0x300
354
355 // for phy specific status register, marvell phy.
356 #define SpeedMask 0x0c000
357 #define Speed_1000M 0x08000
358 #define Speed_100M 0x4000
359 #define Speed_10M 0
360 #define Full_Duplex 0x2000
361
362 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
363 #define LXT1000_100M 0x08000
364 #define LXT1000_1000M 0x0c000
365 #define LXT1000_Full 0x200
366 // 89/12/29 add, for phy specific status register, levelone phy, (end)
367
368 /* for 3-in-1 case, BMCRSR register */
369 #define LinkIsUp2 0x00040000
370
371 /* for PHY */
372 #define LinkIsUp 0x0004
373
374
375 struct netdev_private {
376 /* Descriptor rings first for alignment. */
377 struct fealnx_desc *rx_ring;
378 struct fealnx_desc *tx_ring;
379
380 dma_addr_t rx_ring_dma;
381 dma_addr_t tx_ring_dma;
382
383 spinlock_t lock;
384
385 /* Media monitoring timer. */
386 struct timer_list timer;
387
388 /* Reset timer */
389 struct timer_list reset_timer;
390 int reset_timer_armed;
391 unsigned long crvalue_sv;
392 unsigned long imrvalue_sv;
393
394 /* Frequently used values: keep some adjacent for cache effect. */
395 int flags;
396 struct pci_dev *pci_dev;
397 unsigned long crvalue;
398 unsigned long bcrvalue;
399 unsigned long imrvalue;
400 struct fealnx_desc *cur_rx;
401 struct fealnx_desc *lack_rxbuf;
402 int really_rx_count;
403 struct fealnx_desc *cur_tx;
404 struct fealnx_desc *cur_tx_copy;
405 int really_tx_count;
406 int free_tx_count;
407 unsigned int rx_buf_sz; /* Based on MTU+slack. */
408
409 /* These values are keep track of the transceiver/media in use. */
410 unsigned int linkok;
411 unsigned int line_speed;
412 unsigned int duplexmode;
413 unsigned int default_port:4; /* Last dev->if_port value. */
414 unsigned int PHYType;
415
416 /* MII transceiver section. */
417 int mii_cnt; /* MII device addresses. */
418 unsigned char phys[2]; /* MII device addresses. */
419 struct mii_if_info mii;
420 void __iomem *mem;
421 };
422
423
424 static int mdio_read(struct net_device *dev, int phy_id, int location);
425 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
426 static int netdev_open(struct net_device *dev);
427 static void getlinktype(struct net_device *dev);
428 static void getlinkstatus(struct net_device *dev);
429 static void netdev_timer(unsigned long data);
430 static void reset_timer(unsigned long data);
431 static void fealnx_tx_timeout(struct net_device *dev);
432 static void init_ring(struct net_device *dev);
433 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
434 static irqreturn_t intr_handler(int irq, void *dev_instance);
435 static int netdev_rx(struct net_device *dev);
436 static void set_rx_mode(struct net_device *dev);
437 static void __set_rx_mode(struct net_device *dev);
438 static struct net_device_stats *get_stats(struct net_device *dev);
439 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
440 static const struct ethtool_ops netdev_ethtool_ops;
441 static int netdev_close(struct net_device *dev);
442 static void reset_rx_descriptors(struct net_device *dev);
443 static void reset_tx_descriptors(struct net_device *dev);
444
445 static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
446 {
447 int delay = 0x1000;
448 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
449 while (--delay) {
450 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
451 break;
452 }
453 }
454
455
456 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
457 {
458 int delay = 0x1000;
459 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
460 while (--delay) {
461 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
462 == (CR_R_RXSTOP+CR_R_TXSTOP) )
463 break;
464 }
465 }
466
467 static const struct net_device_ops netdev_ops = {
468 .ndo_open = netdev_open,
469 .ndo_stop = netdev_close,
470 .ndo_start_xmit = start_tx,
471 .ndo_get_stats = get_stats,
472 .ndo_set_rx_mode = set_rx_mode,
473 .ndo_do_ioctl = mii_ioctl,
474 .ndo_tx_timeout = fealnx_tx_timeout,
475 .ndo_set_mac_address = eth_mac_addr,
476 .ndo_validate_addr = eth_validate_addr,
477 };
478
479 static int fealnx_init_one(struct pci_dev *pdev,
480 const struct pci_device_id *ent)
481 {
482 struct netdev_private *np;
483 int i, option, err, irq;
484 static int card_idx = -1;
485 char boardname[12];
486 void __iomem *ioaddr;
487 unsigned long len;
488 unsigned int chip_id = ent->driver_data;
489 struct net_device *dev;
490 void *ring_space;
491 dma_addr_t ring_dma;
492 #ifdef USE_IO_OPS
493 int bar = 0;
494 #else
495 int bar = 1;
496 #endif
497
498 /* when built into the kernel, we only print version if device is found */
499 #ifndef MODULE
500 static int printed_version;
501 if (!printed_version++)
502 printk(version);
503 #endif
504
505 card_idx++;
506 sprintf(boardname, "fealnx%d", card_idx);
507
508 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
509
510 i = pci_enable_device(pdev);
511 if (i) return i;
512 pci_set_master(pdev);
513
514 len = pci_resource_len(pdev, bar);
515 if (len < MIN_REGION_SIZE) {
516 dev_err(&pdev->dev,
517 "region size %ld too small, aborting\n", len);
518 return -ENODEV;
519 }
520
521 i = pci_request_regions(pdev, boardname);
522 if (i)
523 return i;
524
525 irq = pdev->irq;
526
527 ioaddr = pci_iomap(pdev, bar, len);
528 if (!ioaddr) {
529 err = -ENOMEM;
530 goto err_out_res;
531 }
532
533 dev = alloc_etherdev(sizeof(struct netdev_private));
534 if (!dev) {
535 err = -ENOMEM;
536 goto err_out_unmap;
537 }
538 SET_NETDEV_DEV(dev, &pdev->dev);
539
540 /* read ethernet id */
541 for (i = 0; i < 6; ++i)
542 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
543
544 /* Reset the chip to erase previous misconfiguration. */
545 iowrite32(0x00000001, ioaddr + BCR);
546
547 /* Make certain the descriptor lists are aligned. */
548 np = netdev_priv(dev);
549 np->mem = ioaddr;
550 spin_lock_init(&np->lock);
551 np->pci_dev = pdev;
552 np->flags = skel_netdrv_tbl[chip_id].flags;
553 pci_set_drvdata(pdev, dev);
554 np->mii.dev = dev;
555 np->mii.mdio_read = mdio_read;
556 np->mii.mdio_write = mdio_write;
557 np->mii.phy_id_mask = 0x1f;
558 np->mii.reg_num_mask = 0x1f;
559
560 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
561 if (!ring_space) {
562 err = -ENOMEM;
563 goto err_out_free_dev;
564 }
565 np->rx_ring = ring_space;
566 np->rx_ring_dma = ring_dma;
567
568 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
569 if (!ring_space) {
570 err = -ENOMEM;
571 goto err_out_free_rx;
572 }
573 np->tx_ring = ring_space;
574 np->tx_ring_dma = ring_dma;
575
576 /* find the connected MII xcvrs */
577 if (np->flags == HAS_MII_XCVR) {
578 int phy, phy_idx = 0;
579
580 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
581 phy++) {
582 int mii_status = mdio_read(dev, phy, 1);
583
584 if (mii_status != 0xffff && mii_status != 0x0000) {
585 np->phys[phy_idx++] = phy;
586 dev_info(&pdev->dev,
587 "MII PHY found at address %d, status "
588 "0x%4.4x.\n", phy, mii_status);
589 /* get phy type */
590 {
591 unsigned int data;
592
593 data = mdio_read(dev, np->phys[0], 2);
594 if (data == SeeqPHYID0)
595 np->PHYType = SeeqPHY;
596 else if (data == AhdocPHYID0)
597 np->PHYType = AhdocPHY;
598 else if (data == MarvellPHYID0)
599 np->PHYType = MarvellPHY;
600 else if (data == MysonPHYID0)
601 np->PHYType = Myson981;
602 else if (data == LevelOnePHYID0)
603 np->PHYType = LevelOnePHY;
604 else
605 np->PHYType = OtherPHY;
606 }
607 }
608 }
609
610 np->mii_cnt = phy_idx;
611 if (phy_idx == 0)
612 dev_warn(&pdev->dev,
613 "MII PHY not found -- this device may "
614 "not operate correctly.\n");
615 } else {
616 np->phys[0] = 32;
617 /* 89/6/23 add, (begin) */
618 /* get phy type */
619 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
620 np->PHYType = MysonPHY;
621 else
622 np->PHYType = OtherPHY;
623 }
624 np->mii.phy_id = np->phys[0];
625
626 if (dev->mem_start)
627 option = dev->mem_start;
628
629 /* The lower four bits are the media type. */
630 if (option > 0) {
631 if (option & 0x200)
632 np->mii.full_duplex = 1;
633 np->default_port = option & 15;
634 }
635
636 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
637 np->mii.full_duplex = full_duplex[card_idx];
638
639 if (np->mii.full_duplex) {
640 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
641 /* 89/6/13 add, (begin) */
642 // if (np->PHYType==MarvellPHY)
643 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
644 unsigned int data;
645
646 data = mdio_read(dev, np->phys[0], 9);
647 data = (data & 0xfcff) | 0x0200;
648 mdio_write(dev, np->phys[0], 9, data);
649 }
650 /* 89/6/13 add, (end) */
651 if (np->flags == HAS_MII_XCVR)
652 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
653 else
654 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
655 np->mii.force_media = 1;
656 }
657
658 dev->netdev_ops = &netdev_ops;
659 dev->ethtool_ops = &netdev_ethtool_ops;
660 dev->watchdog_timeo = TX_TIMEOUT;
661
662 err = register_netdev(dev);
663 if (err)
664 goto err_out_free_tx;
665
666 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
667 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
668 dev->dev_addr, irq);
669
670 return 0;
671
672 err_out_free_tx:
673 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
674 err_out_free_rx:
675 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
676 err_out_free_dev:
677 free_netdev(dev);
678 err_out_unmap:
679 pci_iounmap(pdev, ioaddr);
680 err_out_res:
681 pci_release_regions(pdev);
682 return err;
683 }
684
685
686 static void fealnx_remove_one(struct pci_dev *pdev)
687 {
688 struct net_device *dev = pci_get_drvdata(pdev);
689
690 if (dev) {
691 struct netdev_private *np = netdev_priv(dev);
692
693 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
694 np->tx_ring_dma);
695 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
696 np->rx_ring_dma);
697 unregister_netdev(dev);
698 pci_iounmap(pdev, np->mem);
699 free_netdev(dev);
700 pci_release_regions(pdev);
701 } else
702 printk(KERN_ERR "fealnx: remove for unknown device\n");
703 }
704
705
706 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
707 {
708 ulong miir;
709 int i;
710 unsigned int mask, data;
711
712 /* enable MII output */
713 miir = (ulong) ioread32(miiport);
714 miir &= 0xfffffff0;
715
716 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
717
718 /* send 32 1's preamble */
719 for (i = 0; i < 32; i++) {
720 /* low MDC; MDO is already high (miir) */
721 miir &= ~MASK_MIIR_MII_MDC;
722 iowrite32(miir, miiport);
723
724 /* high MDC */
725 miir |= MASK_MIIR_MII_MDC;
726 iowrite32(miir, miiport);
727 }
728
729 /* calculate ST+OP+PHYAD+REGAD+TA */
730 data = opcode | (phyad << 7) | (regad << 2);
731
732 /* sent out */
733 mask = 0x8000;
734 while (mask) {
735 /* low MDC, prepare MDO */
736 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
737 if (mask & data)
738 miir |= MASK_MIIR_MII_MDO;
739
740 iowrite32(miir, miiport);
741 /* high MDC */
742 miir |= MASK_MIIR_MII_MDC;
743 iowrite32(miir, miiport);
744 udelay(30);
745
746 /* next */
747 mask >>= 1;
748 if (mask == 0x2 && opcode == OP_READ)
749 miir &= ~MASK_MIIR_MII_WRITE;
750 }
751 return miir;
752 }
753
754
755 static int mdio_read(struct net_device *dev, int phyad, int regad)
756 {
757 struct netdev_private *np = netdev_priv(dev);
758 void __iomem *miiport = np->mem + MANAGEMENT;
759 ulong miir;
760 unsigned int mask, data;
761
762 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
763
764 /* read data */
765 mask = 0x8000;
766 data = 0;
767 while (mask) {
768 /* low MDC */
769 miir &= ~MASK_MIIR_MII_MDC;
770 iowrite32(miir, miiport);
771
772 /* read MDI */
773 miir = ioread32(miiport);
774 if (miir & MASK_MIIR_MII_MDI)
775 data |= mask;
776
777 /* high MDC, and wait */
778 miir |= MASK_MIIR_MII_MDC;
779 iowrite32(miir, miiport);
780 udelay(30);
781
782 /* next */
783 mask >>= 1;
784 }
785
786 /* low MDC */
787 miir &= ~MASK_MIIR_MII_MDC;
788 iowrite32(miir, miiport);
789
790 return data & 0xffff;
791 }
792
793
794 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
795 {
796 struct netdev_private *np = netdev_priv(dev);
797 void __iomem *miiport = np->mem + MANAGEMENT;
798 ulong miir;
799 unsigned int mask;
800
801 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
802
803 /* write data */
804 mask = 0x8000;
805 while (mask) {
806 /* low MDC, prepare MDO */
807 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
808 if (mask & data)
809 miir |= MASK_MIIR_MII_MDO;
810 iowrite32(miir, miiport);
811
812 /* high MDC */
813 miir |= MASK_MIIR_MII_MDC;
814 iowrite32(miir, miiport);
815
816 /* next */
817 mask >>= 1;
818 }
819
820 /* low MDC */
821 miir &= ~MASK_MIIR_MII_MDC;
822 iowrite32(miir, miiport);
823 }
824
825
826 static int netdev_open(struct net_device *dev)
827 {
828 struct netdev_private *np = netdev_priv(dev);
829 void __iomem *ioaddr = np->mem;
830 const int irq = np->pci_dev->irq;
831 int rc, i;
832
833 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
834
835 rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
836 if (rc)
837 return -EAGAIN;
838
839 for (i = 0; i < 3; i++)
840 iowrite16(((unsigned short*)dev->dev_addr)[i],
841 ioaddr + PAR0 + i*2);
842
843 init_ring(dev);
844
845 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
846 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
847
848 /* Initialize other registers. */
849 /* Configure the PCI bus bursts and FIFO thresholds.
850 486: Set 8 longword burst.
851 586: no burst limit.
852 Burst length 5:3
853 0 0 0 1
854 0 0 1 4
855 0 1 0 8
856 0 1 1 16
857 1 0 0 32
858 1 0 1 64
859 1 1 0 128
860 1 1 1 256
861 Wait the specified 50 PCI cycles after a reset by initializing
862 Tx and Rx queues and the address filter list.
863 FIXME (Ueimor): optimistic for alpha + posted writes ? */
864
865 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
866 #ifdef __BIG_ENDIAN
867 np->bcrvalue |= 0x04; /* big-endian */
868 #endif
869
870 #if defined(__i386__) && !defined(MODULE)
871 if (boot_cpu_data.x86 <= 4)
872 np->crvalue = 0xa00;
873 else
874 #endif
875 np->crvalue = 0xe00; /* rx 128 burst length */
876
877
878 // 89/12/29 add,
879 // 90/1/16 modify,
880 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
881 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
882 if (np->pci_dev->device == 0x891) {
883 np->bcrvalue |= 0x200; /* set PROG bit */
884 np->crvalue |= CR_W_ENH; /* set enhanced bit */
885 np->imrvalue |= ETI;
886 }
887 iowrite32(np->bcrvalue, ioaddr + BCR);
888
889 if (dev->if_port == 0)
890 dev->if_port = np->default_port;
891
892 iowrite32(0, ioaddr + RXPDR);
893 // 89/9/1 modify,
894 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
895 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
896 np->mii.full_duplex = np->mii.force_media;
897 getlinkstatus(dev);
898 if (np->linkok)
899 getlinktype(dev);
900 __set_rx_mode(dev);
901
902 netif_start_queue(dev);
903
904 /* Clear and Enable interrupts by setting the interrupt mask. */
905 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
906 iowrite32(np->imrvalue, ioaddr + IMR);
907
908 if (debug)
909 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
910
911 /* Set the timer to check for link beat. */
912 init_timer(&np->timer);
913 np->timer.expires = RUN_AT(3 * HZ);
914 np->timer.data = (unsigned long) dev;
915 np->timer.function = netdev_timer;
916
917 /* timer handler */
918 add_timer(&np->timer);
919
920 init_timer(&np->reset_timer);
921 np->reset_timer.data = (unsigned long) dev;
922 np->reset_timer.function = reset_timer;
923 np->reset_timer_armed = 0;
924 return rc;
925 }
926
927
928 static void getlinkstatus(struct net_device *dev)
929 /* function: Routine will read MII Status Register to get link status. */
930 /* input : dev... pointer to the adapter block. */
931 /* output : none. */
932 {
933 struct netdev_private *np = netdev_priv(dev);
934 unsigned int i, DelayTime = 0x1000;
935
936 np->linkok = 0;
937
938 if (np->PHYType == MysonPHY) {
939 for (i = 0; i < DelayTime; ++i) {
940 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
941 np->linkok = 1;
942 return;
943 }
944 udelay(100);
945 }
946 } else {
947 for (i = 0; i < DelayTime; ++i) {
948 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
949 np->linkok = 1;
950 return;
951 }
952 udelay(100);
953 }
954 }
955 }
956
957
958 static void getlinktype(struct net_device *dev)
959 {
960 struct netdev_private *np = netdev_priv(dev);
961
962 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
963 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
964 np->duplexmode = 2; /* full duplex */
965 else
966 np->duplexmode = 1; /* half duplex */
967 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
968 np->line_speed = 1; /* 10M */
969 else
970 np->line_speed = 2; /* 100M */
971 } else {
972 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
973 unsigned int data;
974
975 data = mdio_read(dev, np->phys[0], MIIRegister18);
976 if (data & SPD_DET_100)
977 np->line_speed = 2; /* 100M */
978 else
979 np->line_speed = 1; /* 10M */
980 if (data & DPLX_DET_FULL)
981 np->duplexmode = 2; /* full duplex mode */
982 else
983 np->duplexmode = 1; /* half duplex mode */
984 } else if (np->PHYType == AhdocPHY) {
985 unsigned int data;
986
987 data = mdio_read(dev, np->phys[0], DiagnosticReg);
988 if (data & Speed_100)
989 np->line_speed = 2; /* 100M */
990 else
991 np->line_speed = 1; /* 10M */
992 if (data & DPLX_FULL)
993 np->duplexmode = 2; /* full duplex mode */
994 else
995 np->duplexmode = 1; /* half duplex mode */
996 }
997 /* 89/6/13 add, (begin) */
998 else if (np->PHYType == MarvellPHY) {
999 unsigned int data;
1000
1001 data = mdio_read(dev, np->phys[0], SpecificReg);
1002 if (data & Full_Duplex)
1003 np->duplexmode = 2; /* full duplex mode */
1004 else
1005 np->duplexmode = 1; /* half duplex mode */
1006 data &= SpeedMask;
1007 if (data == Speed_1000M)
1008 np->line_speed = 3; /* 1000M */
1009 else if (data == Speed_100M)
1010 np->line_speed = 2; /* 100M */
1011 else
1012 np->line_speed = 1; /* 10M */
1013 }
1014 /* 89/6/13 add, (end) */
1015 /* 89/7/27 add, (begin) */
1016 else if (np->PHYType == Myson981) {
1017 unsigned int data;
1018
1019 data = mdio_read(dev, np->phys[0], StatusRegister);
1020
1021 if (data & SPEED100)
1022 np->line_speed = 2;
1023 else
1024 np->line_speed = 1;
1025
1026 if (data & FULLMODE)
1027 np->duplexmode = 2;
1028 else
1029 np->duplexmode = 1;
1030 }
1031 /* 89/7/27 add, (end) */
1032 /* 89/12/29 add */
1033 else if (np->PHYType == LevelOnePHY) {
1034 unsigned int data;
1035
1036 data = mdio_read(dev, np->phys[0], SpecificReg);
1037 if (data & LXT1000_Full)
1038 np->duplexmode = 2; /* full duplex mode */
1039 else
1040 np->duplexmode = 1; /* half duplex mode */
1041 data &= SpeedMask;
1042 if (data == LXT1000_1000M)
1043 np->line_speed = 3; /* 1000M */
1044 else if (data == LXT1000_100M)
1045 np->line_speed = 2; /* 100M */
1046 else
1047 np->line_speed = 1; /* 10M */
1048 }
1049 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1050 if (np->line_speed == 1)
1051 np->crvalue |= CR_W_PS10;
1052 else if (np->line_speed == 3)
1053 np->crvalue |= CR_W_PS1000;
1054 if (np->duplexmode == 2)
1055 np->crvalue |= CR_W_FD;
1056 }
1057 }
1058
1059
1060 /* Take lock before calling this */
1061 static void allocate_rx_buffers(struct net_device *dev)
1062 {
1063 struct netdev_private *np = netdev_priv(dev);
1064
1065 /* allocate skb for rx buffers */
1066 while (np->really_rx_count != RX_RING_SIZE) {
1067 struct sk_buff *skb;
1068
1069 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1070 if (skb == NULL)
1071 break; /* Better luck next round. */
1072
1073 while (np->lack_rxbuf->skbuff)
1074 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1075
1076 np->lack_rxbuf->skbuff = skb;
1077 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1078 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1079 np->lack_rxbuf->status = RXOWN;
1080 ++np->really_rx_count;
1081 }
1082 }
1083
1084
1085 static void netdev_timer(unsigned long data)
1086 {
1087 struct net_device *dev = (struct net_device *) data;
1088 struct netdev_private *np = netdev_priv(dev);
1089 void __iomem *ioaddr = np->mem;
1090 int old_crvalue = np->crvalue;
1091 unsigned int old_linkok = np->linkok;
1092 unsigned long flags;
1093
1094 if (debug)
1095 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1096 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1097 ioread32(ioaddr + TCRRCR));
1098
1099 spin_lock_irqsave(&np->lock, flags);
1100
1101 if (np->flags == HAS_MII_XCVR) {
1102 getlinkstatus(dev);
1103 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1104 getlinktype(dev);
1105 if (np->crvalue != old_crvalue) {
1106 stop_nic_rxtx(ioaddr, np->crvalue);
1107 iowrite32(np->crvalue, ioaddr + TCRRCR);
1108 }
1109 }
1110 }
1111
1112 allocate_rx_buffers(dev);
1113
1114 spin_unlock_irqrestore(&np->lock, flags);
1115
1116 np->timer.expires = RUN_AT(10 * HZ);
1117 add_timer(&np->timer);
1118 }
1119
1120
1121 /* Take lock before calling */
1122 /* Reset chip and disable rx, tx and interrupts */
1123 static void reset_and_disable_rxtx(struct net_device *dev)
1124 {
1125 struct netdev_private *np = netdev_priv(dev);
1126 void __iomem *ioaddr = np->mem;
1127 int delay=51;
1128
1129 /* Reset the chip's Tx and Rx processes. */
1130 stop_nic_rxtx(ioaddr, 0);
1131
1132 /* Disable interrupts by clearing the interrupt mask. */
1133 iowrite32(0, ioaddr + IMR);
1134
1135 /* Reset the chip to erase previous misconfiguration. */
1136 iowrite32(0x00000001, ioaddr + BCR);
1137
1138 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1139 We surely wait too long (address+data phase). Who cares? */
1140 while (--delay) {
1141 ioread32(ioaddr + BCR);
1142 rmb();
1143 }
1144 }
1145
1146
1147 /* Take lock before calling */
1148 /* Restore chip after reset */
1149 static void enable_rxtx(struct net_device *dev)
1150 {
1151 struct netdev_private *np = netdev_priv(dev);
1152 void __iomem *ioaddr = np->mem;
1153
1154 reset_rx_descriptors(dev);
1155
1156 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1157 ioaddr + TXLBA);
1158 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1159 ioaddr + RXLBA);
1160
1161 iowrite32(np->bcrvalue, ioaddr + BCR);
1162
1163 iowrite32(0, ioaddr + RXPDR);
1164 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1165
1166 /* Clear and Enable interrupts by setting the interrupt mask. */
1167 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1168 iowrite32(np->imrvalue, ioaddr + IMR);
1169
1170 iowrite32(0, ioaddr + TXPDR);
1171 }
1172
1173
1174 static void reset_timer(unsigned long data)
1175 {
1176 struct net_device *dev = (struct net_device *) data;
1177 struct netdev_private *np = netdev_priv(dev);
1178 unsigned long flags;
1179
1180 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1181
1182 spin_lock_irqsave(&np->lock, flags);
1183 np->crvalue = np->crvalue_sv;
1184 np->imrvalue = np->imrvalue_sv;
1185
1186 reset_and_disable_rxtx(dev);
1187 /* works for me without this:
1188 reset_tx_descriptors(dev); */
1189 enable_rxtx(dev);
1190 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1191
1192 np->reset_timer_armed = 0;
1193
1194 spin_unlock_irqrestore(&np->lock, flags);
1195 }
1196
1197
1198 static void fealnx_tx_timeout(struct net_device *dev)
1199 {
1200 struct netdev_private *np = netdev_priv(dev);
1201 void __iomem *ioaddr = np->mem;
1202 unsigned long flags;
1203 int i;
1204
1205 printk(KERN_WARNING
1206 "%s: Transmit timed out, status %8.8x, resetting...\n",
1207 dev->name, ioread32(ioaddr + ISR));
1208
1209 {
1210 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1211 for (i = 0; i < RX_RING_SIZE; i++)
1212 printk(KERN_CONT " %8.8x",
1213 (unsigned int) np->rx_ring[i].status);
1214 printk(KERN_CONT "\n");
1215 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1216 for (i = 0; i < TX_RING_SIZE; i++)
1217 printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1218 printk(KERN_CONT "\n");
1219 }
1220
1221 spin_lock_irqsave(&np->lock, flags);
1222
1223 reset_and_disable_rxtx(dev);
1224 reset_tx_descriptors(dev);
1225 enable_rxtx(dev);
1226
1227 spin_unlock_irqrestore(&np->lock, flags);
1228
1229 netif_trans_update(dev); /* prevent tx timeout */
1230 dev->stats.tx_errors++;
1231 netif_wake_queue(dev); /* or .._start_.. ?? */
1232 }
1233
1234
1235 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1236 static void init_ring(struct net_device *dev)
1237 {
1238 struct netdev_private *np = netdev_priv(dev);
1239 int i;
1240
1241 /* initialize rx variables */
1242 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1243 np->cur_rx = &np->rx_ring[0];
1244 np->lack_rxbuf = np->rx_ring;
1245 np->really_rx_count = 0;
1246
1247 /* initial rx descriptors. */
1248 for (i = 0; i < RX_RING_SIZE; i++) {
1249 np->rx_ring[i].status = 0;
1250 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1251 np->rx_ring[i].next_desc = np->rx_ring_dma +
1252 (i + 1)*sizeof(struct fealnx_desc);
1253 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1254 np->rx_ring[i].skbuff = NULL;
1255 }
1256
1257 /* for the last rx descriptor */
1258 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1259 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1260
1261 /* allocate skb for rx buffers */
1262 for (i = 0; i < RX_RING_SIZE; i++) {
1263 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1264
1265 if (skb == NULL) {
1266 np->lack_rxbuf = &np->rx_ring[i];
1267 break;
1268 }
1269
1270 ++np->really_rx_count;
1271 np->rx_ring[i].skbuff = skb;
1272 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1273 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1274 np->rx_ring[i].status = RXOWN;
1275 np->rx_ring[i].control |= RXIC;
1276 }
1277
1278 /* initialize tx variables */
1279 np->cur_tx = &np->tx_ring[0];
1280 np->cur_tx_copy = &np->tx_ring[0];
1281 np->really_tx_count = 0;
1282 np->free_tx_count = TX_RING_SIZE;
1283
1284 for (i = 0; i < TX_RING_SIZE; i++) {
1285 np->tx_ring[i].status = 0;
1286 /* do we need np->tx_ring[i].control = XXX; ?? */
1287 np->tx_ring[i].next_desc = np->tx_ring_dma +
1288 (i + 1)*sizeof(struct fealnx_desc);
1289 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1290 np->tx_ring[i].skbuff = NULL;
1291 }
1292
1293 /* for the last tx descriptor */
1294 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1295 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1296 }
1297
1298
1299 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1300 {
1301 struct netdev_private *np = netdev_priv(dev);
1302 unsigned long flags;
1303
1304 spin_lock_irqsave(&np->lock, flags);
1305
1306 np->cur_tx_copy->skbuff = skb;
1307
1308 #define one_buffer
1309 #define BPT 1022
1310 #if defined(one_buffer)
1311 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1312 skb->len, PCI_DMA_TODEVICE);
1313 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1314 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1315 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1316 // 89/12/29 add,
1317 if (np->pci_dev->device == 0x891)
1318 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1319 np->cur_tx_copy->status = TXOWN;
1320 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1321 --np->free_tx_count;
1322 #elif defined(two_buffer)
1323 if (skb->len > BPT) {
1324 struct fealnx_desc *next;
1325
1326 /* for the first descriptor */
1327 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1328 BPT, PCI_DMA_TODEVICE);
1329 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1330 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1331 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1332
1333 /* for the last descriptor */
1334 next = np->cur_tx_copy->next_desc_logical;
1335 next->skbuff = skb;
1336 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1337 next->control |= (skb->len << PKTSShift); /* pkt size */
1338 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1339 // 89/12/29 add,
1340 if (np->pci_dev->device == 0x891)
1341 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1342 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1343 skb->len - BPT, PCI_DMA_TODEVICE);
1344
1345 next->status = TXOWN;
1346 np->cur_tx_copy->status = TXOWN;
1347
1348 np->cur_tx_copy = next->next_desc_logical;
1349 np->free_tx_count -= 2;
1350 } else {
1351 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1352 skb->len, PCI_DMA_TODEVICE);
1353 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1354 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1355 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1356 // 89/12/29 add,
1357 if (np->pci_dev->device == 0x891)
1358 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1359 np->cur_tx_copy->status = TXOWN;
1360 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1361 --np->free_tx_count;
1362 }
1363 #endif
1364
1365 if (np->free_tx_count < 2)
1366 netif_stop_queue(dev);
1367 ++np->really_tx_count;
1368 iowrite32(0, np->mem + TXPDR);
1369
1370 spin_unlock_irqrestore(&np->lock, flags);
1371 return NETDEV_TX_OK;
1372 }
1373
1374
1375 /* Take lock before calling */
1376 /* Chip probably hosed tx ring. Clean up. */
1377 static void reset_tx_descriptors(struct net_device *dev)
1378 {
1379 struct netdev_private *np = netdev_priv(dev);
1380 struct fealnx_desc *cur;
1381 int i;
1382
1383 /* initialize tx variables */
1384 np->cur_tx = &np->tx_ring[0];
1385 np->cur_tx_copy = &np->tx_ring[0];
1386 np->really_tx_count = 0;
1387 np->free_tx_count = TX_RING_SIZE;
1388
1389 for (i = 0; i < TX_RING_SIZE; i++) {
1390 cur = &np->tx_ring[i];
1391 if (cur->skbuff) {
1392 pci_unmap_single(np->pci_dev, cur->buffer,
1393 cur->skbuff->len, PCI_DMA_TODEVICE);
1394 dev_kfree_skb_any(cur->skbuff);
1395 cur->skbuff = NULL;
1396 }
1397 cur->status = 0;
1398 cur->control = 0; /* needed? */
1399 /* probably not needed. We do it for purely paranoid reasons */
1400 cur->next_desc = np->tx_ring_dma +
1401 (i + 1)*sizeof(struct fealnx_desc);
1402 cur->next_desc_logical = &np->tx_ring[i + 1];
1403 }
1404 /* for the last tx descriptor */
1405 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1406 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1407 }
1408
1409
1410 /* Take lock and stop rx before calling this */
1411 static void reset_rx_descriptors(struct net_device *dev)
1412 {
1413 struct netdev_private *np = netdev_priv(dev);
1414 struct fealnx_desc *cur = np->cur_rx;
1415 int i;
1416
1417 allocate_rx_buffers(dev);
1418
1419 for (i = 0; i < RX_RING_SIZE; i++) {
1420 if (cur->skbuff)
1421 cur->status = RXOWN;
1422 cur = cur->next_desc_logical;
1423 }
1424
1425 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1426 np->mem + RXLBA);
1427 }
1428
1429
1430 /* The interrupt handler does all of the Rx thread work and cleans up
1431 after the Tx thread. */
1432 static irqreturn_t intr_handler(int irq, void *dev_instance)
1433 {
1434 struct net_device *dev = (struct net_device *) dev_instance;
1435 struct netdev_private *np = netdev_priv(dev);
1436 void __iomem *ioaddr = np->mem;
1437 long boguscnt = max_interrupt_work;
1438 unsigned int num_tx = 0;
1439 int handled = 0;
1440
1441 spin_lock(&np->lock);
1442
1443 iowrite32(0, ioaddr + IMR);
1444
1445 do {
1446 u32 intr_status = ioread32(ioaddr + ISR);
1447
1448 /* Acknowledge all of the current interrupt sources ASAP. */
1449 iowrite32(intr_status, ioaddr + ISR);
1450
1451 if (debug)
1452 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1453 intr_status);
1454
1455 if (!(intr_status & np->imrvalue))
1456 break;
1457
1458 handled = 1;
1459
1460 // 90/1/16 delete,
1461 //
1462 // if (intr_status & FBE)
1463 // { /* fatal error */
1464 // stop_nic_tx(ioaddr, 0);
1465 // stop_nic_rx(ioaddr, 0);
1466 // break;
1467 // };
1468
1469 if (intr_status & TUNF)
1470 iowrite32(0, ioaddr + TXPDR);
1471
1472 if (intr_status & CNTOVF) {
1473 /* missed pkts */
1474 dev->stats.rx_missed_errors +=
1475 ioread32(ioaddr + TALLY) & 0x7fff;
1476
1477 /* crc error */
1478 dev->stats.rx_crc_errors +=
1479 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1480 }
1481
1482 if (intr_status & (RI | RBU)) {
1483 if (intr_status & RI)
1484 netdev_rx(dev);
1485 else {
1486 stop_nic_rx(ioaddr, np->crvalue);
1487 reset_rx_descriptors(dev);
1488 iowrite32(np->crvalue, ioaddr + TCRRCR);
1489 }
1490 }
1491
1492 while (np->really_tx_count) {
1493 long tx_status = np->cur_tx->status;
1494 long tx_control = np->cur_tx->control;
1495
1496 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1497 struct fealnx_desc *next;
1498
1499 next = np->cur_tx->next_desc_logical;
1500 tx_status = next->status;
1501 tx_control = next->control;
1502 }
1503
1504 if (tx_status & TXOWN)
1505 break;
1506
1507 if (!(np->crvalue & CR_W_ENH)) {
1508 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1509 dev->stats.tx_errors++;
1510 if (tx_status & EC)
1511 dev->stats.tx_aborted_errors++;
1512 if (tx_status & CSL)
1513 dev->stats.tx_carrier_errors++;
1514 if (tx_status & LC)
1515 dev->stats.tx_window_errors++;
1516 if (tx_status & UDF)
1517 dev->stats.tx_fifo_errors++;
1518 if ((tx_status & HF) && np->mii.full_duplex == 0)
1519 dev->stats.tx_heartbeat_errors++;
1520
1521 } else {
1522 dev->stats.tx_bytes +=
1523 ((tx_control & PKTSMask) >> PKTSShift);
1524
1525 dev->stats.collisions +=
1526 ((tx_status & NCRMask) >> NCRShift);
1527 dev->stats.tx_packets++;
1528 }
1529 } else {
1530 dev->stats.tx_bytes +=
1531 ((tx_control & PKTSMask) >> PKTSShift);
1532 dev->stats.tx_packets++;
1533 }
1534
1535 /* Free the original skb. */
1536 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1537 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1538 dev_kfree_skb_irq(np->cur_tx->skbuff);
1539 np->cur_tx->skbuff = NULL;
1540 --np->really_tx_count;
1541 if (np->cur_tx->control & TXLD) {
1542 np->cur_tx = np->cur_tx->next_desc_logical;
1543 ++np->free_tx_count;
1544 } else {
1545 np->cur_tx = np->cur_tx->next_desc_logical;
1546 np->cur_tx = np->cur_tx->next_desc_logical;
1547 np->free_tx_count += 2;
1548 }
1549 num_tx++;
1550 } /* end of for loop */
1551
1552 if (num_tx && np->free_tx_count >= 2)
1553 netif_wake_queue(dev);
1554
1555 /* read transmit status for enhanced mode only */
1556 if (np->crvalue & CR_W_ENH) {
1557 long data;
1558
1559 data = ioread32(ioaddr + TSR);
1560 dev->stats.tx_errors += (data & 0xff000000) >> 24;
1561 dev->stats.tx_aborted_errors +=
1562 (data & 0xff000000) >> 24;
1563 dev->stats.tx_window_errors +=
1564 (data & 0x00ff0000) >> 16;
1565 dev->stats.collisions += (data & 0x0000ffff);
1566 }
1567
1568 if (--boguscnt < 0) {
1569 printk(KERN_WARNING "%s: Too much work at interrupt, "
1570 "status=0x%4.4x.\n", dev->name, intr_status);
1571 if (!np->reset_timer_armed) {
1572 np->reset_timer_armed = 1;
1573 np->reset_timer.expires = RUN_AT(HZ/2);
1574 add_timer(&np->reset_timer);
1575 stop_nic_rxtx(ioaddr, 0);
1576 netif_stop_queue(dev);
1577 /* or netif_tx_disable(dev); ?? */
1578 /* Prevent other paths from enabling tx,rx,intrs */
1579 np->crvalue_sv = np->crvalue;
1580 np->imrvalue_sv = np->imrvalue;
1581 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1582 np->imrvalue = 0;
1583 }
1584
1585 break;
1586 }
1587 } while (1);
1588
1589 /* read the tally counters */
1590 /* missed pkts */
1591 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1592
1593 /* crc error */
1594 dev->stats.rx_crc_errors +=
1595 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1596
1597 if (debug)
1598 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1599 dev->name, ioread32(ioaddr + ISR));
1600
1601 iowrite32(np->imrvalue, ioaddr + IMR);
1602
1603 spin_unlock(&np->lock);
1604
1605 return IRQ_RETVAL(handled);
1606 }
1607
1608
1609 /* This routine is logically part of the interrupt handler, but separated
1610 for clarity and better register allocation. */
1611 static int netdev_rx(struct net_device *dev)
1612 {
1613 struct netdev_private *np = netdev_priv(dev);
1614 void __iomem *ioaddr = np->mem;
1615
1616 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1617 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1618 s32 rx_status = np->cur_rx->status;
1619
1620 if (np->really_rx_count == 0)
1621 break;
1622
1623 if (debug)
1624 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1625
1626 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1627 (rx_status & ErrorSummary)) {
1628 if (rx_status & ErrorSummary) { /* there was a fatal error */
1629 if (debug)
1630 printk(KERN_DEBUG
1631 "%s: Receive error, Rx status %8.8x.\n",
1632 dev->name, rx_status);
1633
1634 dev->stats.rx_errors++; /* end of a packet. */
1635 if (rx_status & (LONG | RUNT))
1636 dev->stats.rx_length_errors++;
1637 if (rx_status & RXER)
1638 dev->stats.rx_frame_errors++;
1639 if (rx_status & CRC)
1640 dev->stats.rx_crc_errors++;
1641 } else {
1642 int need_to_reset = 0;
1643 int desno = 0;
1644
1645 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1646 struct fealnx_desc *cur;
1647
1648 /* check this packet is received completely? */
1649 cur = np->cur_rx;
1650 while (desno <= np->really_rx_count) {
1651 ++desno;
1652 if ((!(cur->status & RXOWN)) &&
1653 (cur->status & RXLSD))
1654 break;
1655 /* goto next rx descriptor */
1656 cur = cur->next_desc_logical;
1657 }
1658 if (desno > np->really_rx_count)
1659 need_to_reset = 1;
1660 } else /* RXLSD did not find, something error */
1661 need_to_reset = 1;
1662
1663 if (need_to_reset == 0) {
1664 int i;
1665
1666 dev->stats.rx_length_errors++;
1667
1668 /* free all rx descriptors related this long pkt */
1669 for (i = 0; i < desno; ++i) {
1670 if (!np->cur_rx->skbuff) {
1671 printk(KERN_DEBUG
1672 "%s: I'm scared\n", dev->name);
1673 break;
1674 }
1675 np->cur_rx->status = RXOWN;
1676 np->cur_rx = np->cur_rx->next_desc_logical;
1677 }
1678 continue;
1679 } else { /* rx error, need to reset this chip */
1680 stop_nic_rx(ioaddr, np->crvalue);
1681 reset_rx_descriptors(dev);
1682 iowrite32(np->crvalue, ioaddr + TCRRCR);
1683 }
1684 break; /* exit the while loop */
1685 }
1686 } else { /* this received pkt is ok */
1687
1688 struct sk_buff *skb;
1689 /* Omit the four octet CRC from the length. */
1690 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1691
1692 #ifndef final_version
1693 if (debug)
1694 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1695 " status %x.\n", pkt_len, rx_status);
1696 #endif
1697
1698 /* Check if the packet is long enough to accept without copying
1699 to a minimally-sized skbuff. */
1700 if (pkt_len < rx_copybreak &&
1701 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1702 skb_reserve(skb, 2); /* 16 byte align the IP header */
1703 pci_dma_sync_single_for_cpu(np->pci_dev,
1704 np->cur_rx->buffer,
1705 np->rx_buf_sz,
1706 PCI_DMA_FROMDEVICE);
1707 /* Call copy + cksum if available. */
1708
1709 #if ! defined(__alpha__)
1710 skb_copy_to_linear_data(skb,
1711 np->cur_rx->skbuff->data, pkt_len);
1712 skb_put(skb, pkt_len);
1713 #else
1714 memcpy(skb_put(skb, pkt_len),
1715 np->cur_rx->skbuff->data, pkt_len);
1716 #endif
1717 pci_dma_sync_single_for_device(np->pci_dev,
1718 np->cur_rx->buffer,
1719 np->rx_buf_sz,
1720 PCI_DMA_FROMDEVICE);
1721 } else {
1722 pci_unmap_single(np->pci_dev,
1723 np->cur_rx->buffer,
1724 np->rx_buf_sz,
1725 PCI_DMA_FROMDEVICE);
1726 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1727 np->cur_rx->skbuff = NULL;
1728 --np->really_rx_count;
1729 }
1730 skb->protocol = eth_type_trans(skb, dev);
1731 netif_rx(skb);
1732 dev->stats.rx_packets++;
1733 dev->stats.rx_bytes += pkt_len;
1734 }
1735
1736 np->cur_rx = np->cur_rx->next_desc_logical;
1737 } /* end of while loop */
1738
1739 /* allocate skb for rx buffers */
1740 allocate_rx_buffers(dev);
1741
1742 return 0;
1743 }
1744
1745
1746 static struct net_device_stats *get_stats(struct net_device *dev)
1747 {
1748 struct netdev_private *np = netdev_priv(dev);
1749 void __iomem *ioaddr = np->mem;
1750
1751 /* The chip only need report frame silently dropped. */
1752 if (netif_running(dev)) {
1753 dev->stats.rx_missed_errors +=
1754 ioread32(ioaddr + TALLY) & 0x7fff;
1755 dev->stats.rx_crc_errors +=
1756 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1757 }
1758
1759 return &dev->stats;
1760 }
1761
1762
1763 /* for dev->set_multicast_list */
1764 static void set_rx_mode(struct net_device *dev)
1765 {
1766 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1767 unsigned long flags;
1768 spin_lock_irqsave(lp, flags);
1769 __set_rx_mode(dev);
1770 spin_unlock_irqrestore(lp, flags);
1771 }
1772
1773
1774 /* Take lock before calling */
1775 static void __set_rx_mode(struct net_device *dev)
1776 {
1777 struct netdev_private *np = netdev_priv(dev);
1778 void __iomem *ioaddr = np->mem;
1779 u32 mc_filter[2]; /* Multicast hash filter */
1780 u32 rx_mode;
1781
1782 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1783 memset(mc_filter, 0xff, sizeof(mc_filter));
1784 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1785 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1786 (dev->flags & IFF_ALLMULTI)) {
1787 /* Too many to match, or accept all multicasts. */
1788 memset(mc_filter, 0xff, sizeof(mc_filter));
1789 rx_mode = CR_W_AB | CR_W_AM;
1790 } else {
1791 struct netdev_hw_addr *ha;
1792
1793 memset(mc_filter, 0, sizeof(mc_filter));
1794 netdev_for_each_mc_addr(ha, dev) {
1795 unsigned int bit;
1796 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1797 mc_filter[bit >> 5] |= (1 << bit);
1798 }
1799 rx_mode = CR_W_AB | CR_W_AM;
1800 }
1801
1802 stop_nic_rxtx(ioaddr, np->crvalue);
1803
1804 iowrite32(mc_filter[0], ioaddr + MAR0);
1805 iowrite32(mc_filter[1], ioaddr + MAR1);
1806 np->crvalue &= ~CR_W_RXMODEMASK;
1807 np->crvalue |= rx_mode;
1808 iowrite32(np->crvalue, ioaddr + TCRRCR);
1809 }
1810
1811 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1812 {
1813 struct netdev_private *np = netdev_priv(dev);
1814
1815 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1816 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1817 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1818 }
1819
1820 static int netdev_get_link_ksettings(struct net_device *dev,
1821 struct ethtool_link_ksettings *cmd)
1822 {
1823 struct netdev_private *np = netdev_priv(dev);
1824 int rc;
1825
1826 spin_lock_irq(&np->lock);
1827 rc = mii_ethtool_get_link_ksettings(&np->mii, cmd);
1828 spin_unlock_irq(&np->lock);
1829
1830 return rc;
1831 }
1832
1833 static int netdev_set_link_ksettings(struct net_device *dev,
1834 const struct ethtool_link_ksettings *cmd)
1835 {
1836 struct netdev_private *np = netdev_priv(dev);
1837 int rc;
1838
1839 spin_lock_irq(&np->lock);
1840 rc = mii_ethtool_set_link_ksettings(&np->mii, cmd);
1841 spin_unlock_irq(&np->lock);
1842
1843 return rc;
1844 }
1845
1846 static int netdev_nway_reset(struct net_device *dev)
1847 {
1848 struct netdev_private *np = netdev_priv(dev);
1849 return mii_nway_restart(&np->mii);
1850 }
1851
1852 static u32 netdev_get_link(struct net_device *dev)
1853 {
1854 struct netdev_private *np = netdev_priv(dev);
1855 return mii_link_ok(&np->mii);
1856 }
1857
1858 static u32 netdev_get_msglevel(struct net_device *dev)
1859 {
1860 return debug;
1861 }
1862
1863 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1864 {
1865 debug = value;
1866 }
1867
1868 static const struct ethtool_ops netdev_ethtool_ops = {
1869 .get_drvinfo = netdev_get_drvinfo,
1870 .nway_reset = netdev_nway_reset,
1871 .get_link = netdev_get_link,
1872 .get_msglevel = netdev_get_msglevel,
1873 .set_msglevel = netdev_set_msglevel,
1874 .get_link_ksettings = netdev_get_link_ksettings,
1875 .set_link_ksettings = netdev_set_link_ksettings,
1876 };
1877
1878 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1879 {
1880 struct netdev_private *np = netdev_priv(dev);
1881 int rc;
1882
1883 if (!netif_running(dev))
1884 return -EINVAL;
1885
1886 spin_lock_irq(&np->lock);
1887 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1888 spin_unlock_irq(&np->lock);
1889
1890 return rc;
1891 }
1892
1893
1894 static int netdev_close(struct net_device *dev)
1895 {
1896 struct netdev_private *np = netdev_priv(dev);
1897 void __iomem *ioaddr = np->mem;
1898 int i;
1899
1900 netif_stop_queue(dev);
1901
1902 /* Disable interrupts by clearing the interrupt mask. */
1903 iowrite32(0x0000, ioaddr + IMR);
1904
1905 /* Stop the chip's Tx and Rx processes. */
1906 stop_nic_rxtx(ioaddr, 0);
1907
1908 del_timer_sync(&np->timer);
1909 del_timer_sync(&np->reset_timer);
1910
1911 free_irq(np->pci_dev->irq, dev);
1912
1913 /* Free all the skbuffs in the Rx queue. */
1914 for (i = 0; i < RX_RING_SIZE; i++) {
1915 struct sk_buff *skb = np->rx_ring[i].skbuff;
1916
1917 np->rx_ring[i].status = 0;
1918 if (skb) {
1919 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1920 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1921 dev_kfree_skb(skb);
1922 np->rx_ring[i].skbuff = NULL;
1923 }
1924 }
1925
1926 for (i = 0; i < TX_RING_SIZE; i++) {
1927 struct sk_buff *skb = np->tx_ring[i].skbuff;
1928
1929 if (skb) {
1930 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1931 skb->len, PCI_DMA_TODEVICE);
1932 dev_kfree_skb(skb);
1933 np->tx_ring[i].skbuff = NULL;
1934 }
1935 }
1936
1937 return 0;
1938 }
1939
1940 static const struct pci_device_id fealnx_pci_tbl[] = {
1941 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1942 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1943 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1944 {} /* terminate list */
1945 };
1946 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1947
1948
1949 static struct pci_driver fealnx_driver = {
1950 .name = "fealnx",
1951 .id_table = fealnx_pci_tbl,
1952 .probe = fealnx_init_one,
1953 .remove = fealnx_remove_one,
1954 };
1955
1956 static int __init fealnx_init(void)
1957 {
1958 /* when a module, this is printed whether or not devices are found in probe */
1959 #ifdef MODULE
1960 printk(version);
1961 #endif
1962
1963 return pci_register_driver(&fealnx_driver);
1964 }
1965
1966 static void __exit fealnx_exit(void)
1967 {
1968 pci_unregister_driver(&fealnx_driver);
1969 }
1970
1971 module_init(fealnx_init);
1972 module_exit(fealnx_exit);
Linux with added FPC-III support