x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / intel / e1000e / manage.c
blobcc9b3befc2bc0596ea3ae13da69b5afc29fd459d
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 #include "e1000.h"
24 /**
25 * e1000_calculate_checksum - Calculate checksum for buffer
26 * @buffer: pointer to EEPROM
27 * @length: size of EEPROM to calculate a checksum for
29 * Calculates the checksum for some buffer on a specified length. The
30 * checksum calculated is returned.
31 **/
32 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
34 u32 i;
35 u8 sum = 0;
37 if (!buffer)
38 return 0;
40 for (i = 0; i < length; i++)
41 sum += buffer[i];
43 return (u8)(0 - sum);
46 /**
47 * e1000_mng_enable_host_if - Checks host interface is enabled
48 * @hw: pointer to the HW structure
50 * Returns 0 upon success, else -E1000_ERR_HOST_INTERFACE_COMMAND
52 * This function checks whether the HOST IF is enabled for command operation
53 * and also checks whether the previous command is completed. It busy waits
54 * in case of previous command is not completed.
55 **/
56 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
58 u32 hicr;
59 u8 i;
61 if (!hw->mac.arc_subsystem_valid) {
62 e_dbg("ARC subsystem not valid.\n");
63 return -E1000_ERR_HOST_INTERFACE_COMMAND;
66 /* Check that the host interface is enabled. */
67 hicr = er32(HICR);
68 if (!(hicr & E1000_HICR_EN)) {
69 e_dbg("E1000_HOST_EN bit disabled.\n");
70 return -E1000_ERR_HOST_INTERFACE_COMMAND;
72 /* check the previous command is completed */
73 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
74 hicr = er32(HICR);
75 if (!(hicr & E1000_HICR_C))
76 break;
77 mdelay(1);
80 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
81 e_dbg("Previous command timeout failed.\n");
82 return -E1000_ERR_HOST_INTERFACE_COMMAND;
85 return 0;
88 /**
89 * e1000e_check_mng_mode_generic - Generic check management mode
90 * @hw: pointer to the HW structure
92 * Reads the firmware semaphore register and returns true (>0) if
93 * manageability is enabled, else false (0).
94 **/
95 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
97 u32 fwsm = er32(FWSM);
99 return (fwsm & E1000_FWSM_MODE_MASK) ==
100 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
104 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
105 * @hw: pointer to the HW structure
107 * Enables packet filtering on transmit packets if manageability is enabled
108 * and host interface is enabled.
110 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
112 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
113 u32 *buffer = (u32 *)&hw->mng_cookie;
114 u32 offset;
115 s32 ret_val, hdr_csum, csum;
116 u8 i, len;
118 hw->mac.tx_pkt_filtering = true;
120 /* No manageability, no filtering */
121 if (!hw->mac.ops.check_mng_mode(hw)) {
122 hw->mac.tx_pkt_filtering = false;
123 return hw->mac.tx_pkt_filtering;
126 /* If we can't read from the host interface for whatever
127 * reason, disable filtering.
129 ret_val = e1000_mng_enable_host_if(hw);
130 if (ret_val) {
131 hw->mac.tx_pkt_filtering = false;
132 return hw->mac.tx_pkt_filtering;
135 /* Read in the header. Length and offset are in dwords. */
136 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
137 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
138 for (i = 0; i < len; i++)
139 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF,
140 offset + i);
141 hdr_csum = hdr->checksum;
142 hdr->checksum = 0;
143 csum = e1000_calculate_checksum((u8 *)hdr,
144 E1000_MNG_DHCP_COOKIE_LENGTH);
145 /* If either the checksums or signature don't match, then
146 * the cookie area isn't considered valid, in which case we
147 * take the safe route of assuming Tx filtering is enabled.
149 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
150 hw->mac.tx_pkt_filtering = true;
151 return hw->mac.tx_pkt_filtering;
154 /* Cookie area is valid, make the final check for filtering. */
155 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
156 hw->mac.tx_pkt_filtering = false;
158 return hw->mac.tx_pkt_filtering;
162 * e1000_mng_write_cmd_header - Writes manageability command header
163 * @hw: pointer to the HW structure
164 * @hdr: pointer to the host interface command header
166 * Writes the command header after does the checksum calculation.
168 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
169 struct e1000_host_mng_command_header *hdr)
171 u16 i, length = sizeof(struct e1000_host_mng_command_header);
173 /* Write the whole command header structure with new checksum. */
175 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
177 length >>= 2;
178 /* Write the relevant command block into the ram area. */
179 for (i = 0; i < length; i++) {
180 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i));
181 e1e_flush();
184 return 0;
188 * e1000_mng_host_if_write - Write to the manageability host interface
189 * @hw: pointer to the HW structure
190 * @buffer: pointer to the host interface buffer
191 * @length: size of the buffer
192 * @offset: location in the buffer to write to
193 * @sum: sum of the data (not checksum)
195 * This function writes the buffer content at the offset given on the host if.
196 * It also does alignment considerations to do the writes in most efficient
197 * way. Also fills up the sum of the buffer in *buffer parameter.
199 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
200 u16 length, u16 offset, u8 *sum)
202 u8 *tmp;
203 u8 *bufptr = buffer;
204 u32 data = 0;
205 u16 remaining, i, j, prev_bytes;
207 /* sum = only sum of the data and it is not checksum */
209 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
210 return -E1000_ERR_PARAM;
212 tmp = (u8 *)&data;
213 prev_bytes = offset & 0x3;
214 offset >>= 2;
216 if (prev_bytes) {
217 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
218 for (j = prev_bytes; j < sizeof(u32); j++) {
219 *(tmp + j) = *bufptr++;
220 *sum += *(tmp + j);
222 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
223 length -= j - prev_bytes;
224 offset++;
227 remaining = length & 0x3;
228 length -= remaining;
230 /* Calculate length in DWORDs */
231 length >>= 2;
233 /* The device driver writes the relevant command block into the
234 * ram area.
236 for (i = 0; i < length; i++) {
237 for (j = 0; j < sizeof(u32); j++) {
238 *(tmp + j) = *bufptr++;
239 *sum += *(tmp + j);
242 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
244 if (remaining) {
245 for (j = 0; j < sizeof(u32); j++) {
246 if (j < remaining)
247 *(tmp + j) = *bufptr++;
248 else
249 *(tmp + j) = 0;
251 *sum += *(tmp + j);
253 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
256 return 0;
260 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
261 * @hw: pointer to the HW structure
262 * @buffer: pointer to the host interface
263 * @length: size of the buffer
265 * Writes the DHCP information to the host interface.
267 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
269 struct e1000_host_mng_command_header hdr;
270 s32 ret_val;
271 u32 hicr;
273 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
274 hdr.command_length = length;
275 hdr.reserved1 = 0;
276 hdr.reserved2 = 0;
277 hdr.checksum = 0;
279 /* Enable the host interface */
280 ret_val = e1000_mng_enable_host_if(hw);
281 if (ret_val)
282 return ret_val;
284 /* Populate the host interface with the contents of "buffer". */
285 ret_val = e1000_mng_host_if_write(hw, buffer, length,
286 sizeof(hdr), &(hdr.checksum));
287 if (ret_val)
288 return ret_val;
290 /* Write the manageability command header */
291 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
292 if (ret_val)
293 return ret_val;
295 /* Tell the ARC a new command is pending. */
296 hicr = er32(HICR);
297 ew32(HICR, hicr | E1000_HICR_C);
299 return 0;
303 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
304 * @hw: pointer to the HW structure
306 * Verifies the hardware needs to leave interface enabled so that frames can
307 * be directed to and from the management interface.
309 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
311 u32 manc;
312 u32 fwsm, factps;
314 manc = er32(MANC);
316 if (!(manc & E1000_MANC_RCV_TCO_EN))
317 return false;
319 if (hw->mac.has_fwsm) {
320 fwsm = er32(FWSM);
321 factps = er32(FACTPS);
323 if (!(factps & E1000_FACTPS_MNGCG) &&
324 ((fwsm & E1000_FWSM_MODE_MASK) ==
325 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
326 return true;
327 } else if ((hw->mac.type == e1000_82574) ||
328 (hw->mac.type == e1000_82583)) {
329 u16 data;
330 s32 ret_val;
332 factps = er32(FACTPS);
333 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
334 if (ret_val)
335 return false;
337 if (!(factps & E1000_FACTPS_MNGCG) &&
338 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
339 (e1000_mng_mode_pt << 13)))
340 return true;
341 } else if ((manc & E1000_MANC_SMBUS_EN) &&
342 !(manc & E1000_MANC_ASF_EN)) {
343 return true;
346 return false;