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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
blobe55b2602f37166d7eea6442fa3bc5797e97d470c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35
36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
51
52 /**
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
55 * @byte: byte to send
56 *
57 * Returns an error code on error.
58 **/
59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
60 {
61 s32 status;
62
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
64 if (status)
65 return status;
66 return ixgbe_get_i2c_ack(hw);
67 }
68
69 /**
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
73 *
74 * Returns an error code on error.
75 **/
76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
77 {
78 s32 status;
79
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
81 if (status)
82 return status;
83 /* ACK */
84 return ixgbe_clock_out_i2c_bit(hw, false);
85 }
86
87 /**
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
89 * @add1: addend 1
90 * @add2: addend 2
91 *
92 * Returns one's complement 8-bit sum.
93 **/
94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
95 {
96 u16 sum = add1 + add2;
97
98 sum = (sum & 0xFF) + (sum >> 8);
99 return sum & 0xFF;
100 }
101
102 /**
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
109 *
110 * Returns an error code on error.
111 */
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
113 u16 reg, u16 *val, bool lock)
114 {
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
116 int max_retry = 3;
117 int retry = 0;
118 u8 csum_byte;
119 u8 high_bits;
120 u8 low_bits;
121 u8 reg_high;
122 u8 csum;
123
124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 csum = ~csum;
127 do {
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
130 ixgbe_i2c_start(hw);
131 /* Device Address and write indication */
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 goto fail;
134 /* Write bits 14:8 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 goto fail;
137 /* Write bits 7:0 */
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 goto fail;
140 /* Write csum */
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 goto fail;
143 /* Re-start condition */
144 ixgbe_i2c_start(hw);
145 /* Device Address and read indication */
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 goto fail;
148 /* Get upper bits */
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 goto fail;
151 /* Get low bits */
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 goto fail;
154 /* Get csum */
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
156 goto fail;
157 /* NACK */
158 if (ixgbe_clock_out_i2c_bit(hw, false))
159 goto fail;
160 ixgbe_i2c_stop(hw);
161 if (lock)
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
164 return 0;
165
166 fail:
167 ixgbe_i2c_bus_clear(hw);
168 if (lock)
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
170 retry++;
171 if (retry < max_retry)
172 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
173 else
174 hw_dbg(hw, "I2C byte read combined error.\n");
175 } while (retry < max_retry);
176
177 return IXGBE_ERR_I2C;
178 }
179
180 /**
181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
182 * @hw: pointer to the hardware structure
183 * @addr: I2C bus address to write to
184 * @reg: I2C device register to write to
185 * @val: value to write
186 * @lock: true if to take and release semaphore
187 *
188 * Returns an error code on error.
189 */
190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
191 u16 reg, u16 val, bool lock)
192 {
193 u32 swfw_mask = hw->phy.phy_semaphore_mask;
194 int max_retry = 1;
195 int retry = 0;
196 u8 reg_high;
197 u8 csum;
198
199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
203 csum = ~csum;
204 do {
205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
206 return IXGBE_ERR_SWFW_SYNC;
207 ixgbe_i2c_start(hw);
208 /* Device Address and write indication */
209 if (ixgbe_out_i2c_byte_ack(hw, addr))
210 goto fail;
211 /* Write bits 14:8 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
213 goto fail;
214 /* Write bits 7:0 */
215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
216 goto fail;
217 /* Write data 15:8 */
218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
219 goto fail;
220 /* Write data 7:0 */
221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
222 goto fail;
223 /* Write csum */
224 if (ixgbe_out_i2c_byte_ack(hw, csum))
225 goto fail;
226 ixgbe_i2c_stop(hw);
227 if (lock)
228 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
229 return 0;
230
231 fail:
232 ixgbe_i2c_bus_clear(hw);
233 if (lock)
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
235 retry++;
236 if (retry < max_retry)
237 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
238 else
239 hw_dbg(hw, "I2C byte write combined error.\n");
240 } while (retry < max_retry);
241
242 return IXGBE_ERR_I2C;
243 }
244
245 /**
246 * ixgbe_probe_phy - Probe a single address for a PHY
247 * @hw: pointer to hardware structure
248 * @phy_addr: PHY address to probe
249 *
250 * Returns true if PHY found
251 **/
252 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
253 {
254 u16 ext_ability = 0;
255
256 hw->phy.mdio.prtad = phy_addr;
257 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
258 return false;
259
260 if (ixgbe_get_phy_id(hw))
261 return false;
262
263 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
264
265 if (hw->phy.type == ixgbe_phy_unknown) {
266 hw->phy.ops.read_reg(hw,
267 MDIO_PMA_EXTABLE,
268 MDIO_MMD_PMAPMD,
269 &ext_ability);
270 if (ext_ability &
271 (MDIO_PMA_EXTABLE_10GBT |
272 MDIO_PMA_EXTABLE_1000BT))
273 hw->phy.type = ixgbe_phy_cu_unknown;
274 else
275 hw->phy.type = ixgbe_phy_generic;
276 }
277
278 return true;
279 }
280
281 /**
282 * ixgbe_identify_phy_generic - Get physical layer module
283 * @hw: pointer to hardware structure
284 *
285 * Determines the physical layer module found on the current adapter.
286 **/
287 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
288 {
289 u32 phy_addr;
290 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
291
292 if (!hw->phy.phy_semaphore_mask) {
293 if (hw->bus.lan_id)
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
295 else
296 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
297 }
298
299 if (hw->phy.type != ixgbe_phy_unknown)
300 return 0;
301
302 if (hw->phy.nw_mng_if_sel) {
303 phy_addr = (hw->phy.nw_mng_if_sel &
304 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
305 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
306 if (ixgbe_probe_phy(hw, phy_addr))
307 return 0;
308 else
309 return IXGBE_ERR_PHY_ADDR_INVALID;
310 }
311
312 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
313 if (ixgbe_probe_phy(hw, phy_addr)) {
314 status = 0;
315 break;
316 }
317 }
318
319 /* Certain media types do not have a phy so an address will not
320 * be found and the code will take this path. Caller has to
321 * decide if it is an error or not.
322 */
323 if (status)
324 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
325
326 return status;
327 }
328
329 /**
330 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
331 * @hw: pointer to the hardware structure
332 *
333 * This function checks the MMNGC.MNG_VETO bit to see if there are
334 * any constraints on link from manageability. For MAC's that don't
335 * have this bit just return false since the link can not be blocked
336 * via this method.
337 **/
338 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
339 {
340 u32 mmngc;
341
342 /* If we don't have this bit, it can't be blocking */
343 if (hw->mac.type == ixgbe_mac_82598EB)
344 return false;
345
346 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
347 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
348 hw_dbg(hw, "MNG_VETO bit detected.\n");
349 return true;
350 }
351
352 return false;
353 }
354
355 /**
356 * ixgbe_get_phy_id - Get the phy type
357 * @hw: pointer to hardware structure
358 *
359 **/
360 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
361 {
362 s32 status;
363 u16 phy_id_high = 0;
364 u16 phy_id_low = 0;
365
366 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
367 &phy_id_high);
368
369 if (!status) {
370 hw->phy.id = (u32)(phy_id_high << 16);
371 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
372 &phy_id_low);
373 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
374 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
375 }
376 return status;
377 }
378
379 /**
380 * ixgbe_get_phy_type_from_id - Get the phy type
381 * @hw: pointer to hardware structure
382 *
383 **/
384 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
385 {
386 enum ixgbe_phy_type phy_type;
387
388 switch (phy_id) {
389 case TN1010_PHY_ID:
390 phy_type = ixgbe_phy_tn;
391 break;
392 case X550_PHY_ID2:
393 case X550_PHY_ID3:
394 case X540_PHY_ID:
395 phy_type = ixgbe_phy_aq;
396 break;
397 case QT2022_PHY_ID:
398 phy_type = ixgbe_phy_qt;
399 break;
400 case ATH_PHY_ID:
401 phy_type = ixgbe_phy_nl;
402 break;
403 case X557_PHY_ID:
404 case X557_PHY_ID2:
405 phy_type = ixgbe_phy_x550em_ext_t;
406 break;
407 default:
408 phy_type = ixgbe_phy_unknown;
409 break;
410 }
411
412 return phy_type;
413 }
414
415 /**
416 * ixgbe_reset_phy_generic - Performs a PHY reset
417 * @hw: pointer to hardware structure
418 **/
419 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
420 {
421 u32 i;
422 u16 ctrl = 0;
423 s32 status = 0;
424
425 if (hw->phy.type == ixgbe_phy_unknown)
426 status = ixgbe_identify_phy_generic(hw);
427
428 if (status != 0 || hw->phy.type == ixgbe_phy_none)
429 return status;
430
431 /* Don't reset PHY if it's shut down due to overtemp. */
432 if (!hw->phy.reset_if_overtemp &&
433 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
434 return 0;
435
436 /* Blocked by MNG FW so bail */
437 if (ixgbe_check_reset_blocked(hw))
438 return 0;
439
440 /*
441 * Perform soft PHY reset to the PHY_XS.
442 * This will cause a soft reset to the PHY
443 */
444 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
445 MDIO_MMD_PHYXS,
446 MDIO_CTRL1_RESET);
447
448 /*
449 * Poll for reset bit to self-clear indicating reset is complete.
450 * Some PHYs could take up to 3 seconds to complete and need about
451 * 1.7 usec delay after the reset is complete.
452 */
453 for (i = 0; i < 30; i++) {
454 msleep(100);
455 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
456 status = hw->phy.ops.read_reg(hw,
457 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
458 MDIO_MMD_PMAPMD, &ctrl);
459 if (status)
460 return status;
461
462 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
463 udelay(2);
464 break;
465 }
466 } else {
467 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
468 MDIO_MMD_PHYXS, &ctrl);
469 if (status)
470 return status;
471
472 if (!(ctrl & MDIO_CTRL1_RESET)) {
473 udelay(2);
474 break;
475 }
476 }
477 }
478
479 if (ctrl & MDIO_CTRL1_RESET) {
480 hw_dbg(hw, "PHY reset polling failed to complete.\n");
481 return IXGBE_ERR_RESET_FAILED;
482 }
483
484 return 0;
485 }
486
487 /**
488 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
489 * the SWFW lock
490 * @hw: pointer to hardware structure
491 * @reg_addr: 32 bit address of PHY register to read
492 * @phy_data: Pointer to read data from PHY register
493 **/
494 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
495 u16 *phy_data)
496 {
497 u32 i, data, command;
498
499 /* Setup and write the address cycle command */
500 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
501 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
502 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
503 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
504
505 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
506
507 /* Check every 10 usec to see if the address cycle completed.
508 * The MDI Command bit will clear when the operation is
509 * complete
510 */
511 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
512 udelay(10);
513
514 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
515 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
516 break;
517 }
518
519
520 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
521 hw_dbg(hw, "PHY address command did not complete.\n");
522 return IXGBE_ERR_PHY;
523 }
524
525 /* Address cycle complete, setup and write the read
526 * command
527 */
528 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
529 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
530 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
531 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
532
533 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
534
535 /* Check every 10 usec to see if the address cycle
536 * completed. The MDI Command bit will clear when the
537 * operation is complete
538 */
539 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
540 udelay(10);
541
542 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
543 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
544 break;
545 }
546
547 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
548 hw_dbg(hw, "PHY read command didn't complete\n");
549 return IXGBE_ERR_PHY;
550 }
551
552 /* Read operation is complete. Get the data
553 * from MSRWD
554 */
555 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
556 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
557 *phy_data = (u16)(data);
558
559 return 0;
560 }
561
562 /**
563 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
564 * using the SWFW lock - this function is needed in most cases
565 * @hw: pointer to hardware structure
566 * @reg_addr: 32 bit address of PHY register to read
567 * @phy_data: Pointer to read data from PHY register
568 **/
569 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
570 u32 device_type, u16 *phy_data)
571 {
572 s32 status;
573 u32 gssr = hw->phy.phy_semaphore_mask;
574
575 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
576 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
577 phy_data);
578 hw->mac.ops.release_swfw_sync(hw, gssr);
579 } else {
580 return IXGBE_ERR_SWFW_SYNC;
581 }
582
583 return status;
584 }
585
586 /**
587 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
588 * without SWFW lock
589 * @hw: pointer to hardware structure
590 * @reg_addr: 32 bit PHY register to write
591 * @device_type: 5 bit device type
592 * @phy_data: Data to write to the PHY register
593 **/
594 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
595 u32 device_type, u16 phy_data)
596 {
597 u32 i, command;
598
599 /* Put the data in the MDI single read and write data register*/
600 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
601
602 /* Setup and write the address cycle command */
603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
604 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
605 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
606 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
607
608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
609
610 /*
611 * Check every 10 usec to see if the address cycle completed.
612 * The MDI Command bit will clear when the operation is
613 * complete
614 */
615 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
616 udelay(10);
617
618 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
619 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
620 break;
621 }
622
623 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
624 hw_dbg(hw, "PHY address cmd didn't complete\n");
625 return IXGBE_ERR_PHY;
626 }
627
628 /*
629 * Address cycle complete, setup and write the write
630 * command
631 */
632 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
633 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
634 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
635 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
636
637 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
638
639 /* Check every 10 usec to see if the address cycle
640 * completed. The MDI Command bit will clear when the
641 * operation is complete
642 */
643 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
644 udelay(10);
645
646 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
647 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
648 break;
649 }
650
651 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
652 hw_dbg(hw, "PHY write cmd didn't complete\n");
653 return IXGBE_ERR_PHY;
654 }
655
656 return 0;
657 }
658
659 /**
660 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
661 * using SWFW lock- this function is needed in most cases
662 * @hw: pointer to hardware structure
663 * @reg_addr: 32 bit PHY register to write
664 * @device_type: 5 bit device type
665 * @phy_data: Data to write to the PHY register
666 **/
667 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
668 u32 device_type, u16 phy_data)
669 {
670 s32 status;
671 u32 gssr = hw->phy.phy_semaphore_mask;
672
673 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
674 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
675 phy_data);
676 hw->mac.ops.release_swfw_sync(hw, gssr);
677 } else {
678 return IXGBE_ERR_SWFW_SYNC;
679 }
680
681 return status;
682 }
683
684 /**
685 * ixgbe_setup_phy_link_generic - Set and restart autoneg
686 * @hw: pointer to hardware structure
687 *
688 * Restart autonegotiation and PHY and waits for completion.
689 **/
690 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
691 {
692 s32 status = 0;
693 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
694 bool autoneg = false;
695 ixgbe_link_speed speed;
696
697 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
698
699 /* Set or unset auto-negotiation 10G advertisement */
700 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
701
702 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
703 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
704 (speed & IXGBE_LINK_SPEED_10GB_FULL))
705 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
706
707 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
708
709 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
710 MDIO_MMD_AN, &autoneg_reg);
711
712 if (hw->mac.type == ixgbe_mac_X550) {
713 /* Set or unset auto-negotiation 5G advertisement */
714 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
715 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
716 (speed & IXGBE_LINK_SPEED_5GB_FULL))
717 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
718
719 /* Set or unset auto-negotiation 2.5G advertisement */
720 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
721 if ((hw->phy.autoneg_advertised &
722 IXGBE_LINK_SPEED_2_5GB_FULL) &&
723 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
724 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
725 }
726
727 /* Set or unset auto-negotiation 1G advertisement */
728 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
729 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
730 (speed & IXGBE_LINK_SPEED_1GB_FULL))
731 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
732
733 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
734 MDIO_MMD_AN, autoneg_reg);
735
736 /* Set or unset auto-negotiation 100M advertisement */
737 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
738
739 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
740 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
741 (speed & IXGBE_LINK_SPEED_100_FULL))
742 autoneg_reg |= ADVERTISE_100FULL;
743
744 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
745
746 /* Blocked by MNG FW so don't reset PHY */
747 if (ixgbe_check_reset_blocked(hw))
748 return 0;
749
750 /* Restart PHY autonegotiation and wait for completion */
751 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
752 MDIO_MMD_AN, &autoneg_reg);
753
754 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
755
756 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
757 MDIO_MMD_AN, autoneg_reg);
758
759 return status;
760 }
761
762 /**
763 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
764 * @hw: pointer to hardware structure
765 * @speed: new link speed
766 **/
767 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
768 ixgbe_link_speed speed,
769 bool autoneg_wait_to_complete)
770 {
771 /* Clear autoneg_advertised and set new values based on input link
772 * speed.
773 */
774 hw->phy.autoneg_advertised = 0;
775
776 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
777 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
778
779 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
780 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
781
782 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
783 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
784
785 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
786 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
787
788 if (speed & IXGBE_LINK_SPEED_100_FULL)
789 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
790
791 if (speed & IXGBE_LINK_SPEED_10_FULL)
792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
793
794 /* Setup link based on the new speed settings */
795 hw->phy.ops.setup_link(hw);
796
797 return 0;
798 }
799
800 /**
801 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
802 * @hw: pointer to hardware structure
803 *
804 * Determines the supported link capabilities by reading the PHY auto
805 * negotiation register.
806 */
807 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
808 {
809 u16 speed_ability;
810 s32 status;
811
812 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
813 &speed_ability);
814 if (status)
815 return status;
816
817 if (speed_ability & MDIO_SPEED_10G)
818 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
819 if (speed_ability & MDIO_PMA_SPEED_1000)
820 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
821 if (speed_ability & MDIO_PMA_SPEED_100)
822 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
823
824 switch (hw->mac.type) {
825 case ixgbe_mac_X550:
826 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
827 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
828 break;
829 case ixgbe_mac_X550EM_x:
830 case ixgbe_mac_x550em_a:
831 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
832 break;
833 default:
834 break;
835 }
836
837 return 0;
838 }
839
840 /**
841 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
842 * @hw: pointer to hardware structure
843 * @speed: pointer to link speed
844 * @autoneg: boolean auto-negotiation value
845 */
846 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
847 ixgbe_link_speed *speed,
848 bool *autoneg)
849 {
850 s32 status = 0;
851
852 *autoneg = true;
853 if (!hw->phy.speeds_supported)
854 status = ixgbe_get_copper_speeds_supported(hw);
855
856 *speed = hw->phy.speeds_supported;
857 return status;
858 }
859
860 /**
861 * ixgbe_check_phy_link_tnx - Determine link and speed status
862 * @hw: pointer to hardware structure
863 *
864 * Reads the VS1 register to determine if link is up and the current speed for
865 * the PHY.
866 **/
867 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
868 bool *link_up)
869 {
870 s32 status;
871 u32 time_out;
872 u32 max_time_out = 10;
873 u16 phy_link = 0;
874 u16 phy_speed = 0;
875 u16 phy_data = 0;
876
877 /* Initialize speed and link to default case */
878 *link_up = false;
879 *speed = IXGBE_LINK_SPEED_10GB_FULL;
880
881 /*
882 * Check current speed and link status of the PHY register.
883 * This is a vendor specific register and may have to
884 * be changed for other copper PHYs.
885 */
886 for (time_out = 0; time_out < max_time_out; time_out++) {
887 udelay(10);
888 status = hw->phy.ops.read_reg(hw,
889 MDIO_STAT1,
890 MDIO_MMD_VEND1,
891 &phy_data);
892 phy_link = phy_data &
893 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
894 phy_speed = phy_data &
895 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
896 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
897 *link_up = true;
898 if (phy_speed ==
899 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
900 *speed = IXGBE_LINK_SPEED_1GB_FULL;
901 break;
902 }
903 }
904
905 return status;
906 }
907
908 /**
909 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
910 * @hw: pointer to hardware structure
911 *
912 * Restart autonegotiation and PHY and waits for completion.
913 * This function always returns success, this is nessary since
914 * it is called via a function pointer that could call other
915 * functions that could return an error.
916 **/
917 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
918 {
919 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
920 bool autoneg = false;
921 ixgbe_link_speed speed;
922
923 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
924
925 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
926 /* Set or unset auto-negotiation 10G advertisement */
927 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
928 MDIO_MMD_AN,
929 &autoneg_reg);
930
931 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
932 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
933 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
934
935 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
936 MDIO_MMD_AN,
937 autoneg_reg);
938 }
939
940 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
941 /* Set or unset auto-negotiation 1G advertisement */
942 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
943 MDIO_MMD_AN,
944 &autoneg_reg);
945
946 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
947 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
948 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
949
950 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
951 MDIO_MMD_AN,
952 autoneg_reg);
953 }
954
955 if (speed & IXGBE_LINK_SPEED_100_FULL) {
956 /* Set or unset auto-negotiation 100M advertisement */
957 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
958 MDIO_MMD_AN,
959 &autoneg_reg);
960
961 autoneg_reg &= ~(ADVERTISE_100FULL |
962 ADVERTISE_100HALF);
963 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
964 autoneg_reg |= ADVERTISE_100FULL;
965
966 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
967 MDIO_MMD_AN,
968 autoneg_reg);
969 }
970
971 /* Blocked by MNG FW so don't reset PHY */
972 if (ixgbe_check_reset_blocked(hw))
973 return 0;
974
975 /* Restart PHY autonegotiation and wait for completion */
976 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
977 MDIO_MMD_AN, &autoneg_reg);
978
979 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
980
981 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
982 MDIO_MMD_AN, autoneg_reg);
983 return 0;
984 }
985
986 /**
987 * ixgbe_reset_phy_nl - Performs a PHY reset
988 * @hw: pointer to hardware structure
989 **/
990 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
991 {
992 u16 phy_offset, control, eword, edata, block_crc;
993 bool end_data = false;
994 u16 list_offset, data_offset;
995 u16 phy_data = 0;
996 s32 ret_val;
997 u32 i;
998
999 /* Blocked by MNG FW so bail */
1000 if (ixgbe_check_reset_blocked(hw))
1001 return 0;
1002
1003 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1004
1005 /* reset the PHY and poll for completion */
1006 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1007 (phy_data | MDIO_CTRL1_RESET));
1008
1009 for (i = 0; i < 100; i++) {
1010 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1011 &phy_data);
1012 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1013 break;
1014 usleep_range(10000, 20000);
1015 }
1016
1017 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1018 hw_dbg(hw, "PHY reset did not complete.\n");
1019 return IXGBE_ERR_PHY;
1020 }
1021
1022 /* Get init offsets */
1023 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1024 &data_offset);
1025 if (ret_val)
1026 return ret_val;
1027
1028 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1029 data_offset++;
1030 while (!end_data) {
1031 /*
1032 * Read control word from PHY init contents offset
1033 */
1034 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1035 if (ret_val)
1036 goto err_eeprom;
1037 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1038 IXGBE_CONTROL_SHIFT_NL;
1039 edata = eword & IXGBE_DATA_MASK_NL;
1040 switch (control) {
1041 case IXGBE_DELAY_NL:
1042 data_offset++;
1043 hw_dbg(hw, "DELAY: %d MS\n", edata);
1044 usleep_range(edata * 1000, edata * 2000);
1045 break;
1046 case IXGBE_DATA_NL:
1047 hw_dbg(hw, "DATA:\n");
1048 data_offset++;
1049 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1050 &phy_offset);
1051 if (ret_val)
1052 goto err_eeprom;
1053 for (i = 0; i < edata; i++) {
1054 ret_val = hw->eeprom.ops.read(hw, data_offset,
1055 &eword);
1056 if (ret_val)
1057 goto err_eeprom;
1058 hw->phy.ops.write_reg(hw, phy_offset,
1059 MDIO_MMD_PMAPMD, eword);
1060 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1061 phy_offset);
1062 data_offset++;
1063 phy_offset++;
1064 }
1065 break;
1066 case IXGBE_CONTROL_NL:
1067 data_offset++;
1068 hw_dbg(hw, "CONTROL:\n");
1069 if (edata == IXGBE_CONTROL_EOL_NL) {
1070 hw_dbg(hw, "EOL\n");
1071 end_data = true;
1072 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1073 hw_dbg(hw, "SOL\n");
1074 } else {
1075 hw_dbg(hw, "Bad control value\n");
1076 return IXGBE_ERR_PHY;
1077 }
1078 break;
1079 default:
1080 hw_dbg(hw, "Bad control type\n");
1081 return IXGBE_ERR_PHY;
1082 }
1083 }
1084
1085 return ret_val;
1086
1087 err_eeprom:
1088 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1089 return IXGBE_ERR_PHY;
1090 }
1091
1092 /**
1093 * ixgbe_identify_module_generic - Identifies module type
1094 * @hw: pointer to hardware structure
1095 *
1096 * Determines HW type and calls appropriate function.
1097 **/
1098 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1099 {
1100 switch (hw->mac.ops.get_media_type(hw)) {
1101 case ixgbe_media_type_fiber:
1102 return ixgbe_identify_sfp_module_generic(hw);
1103 case ixgbe_media_type_fiber_qsfp:
1104 return ixgbe_identify_qsfp_module_generic(hw);
1105 default:
1106 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1107 return IXGBE_ERR_SFP_NOT_PRESENT;
1108 }
1109
1110 return IXGBE_ERR_SFP_NOT_PRESENT;
1111 }
1112
1113 /**
1114 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1115 * @hw: pointer to hardware structure
1116 *
1117 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1118 **/
1119 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1120 {
1121 struct ixgbe_adapter *adapter = hw->back;
1122 s32 status;
1123 u32 vendor_oui = 0;
1124 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1125 u8 identifier = 0;
1126 u8 comp_codes_1g = 0;
1127 u8 comp_codes_10g = 0;
1128 u8 oui_bytes[3] = {0, 0, 0};
1129 u8 cable_tech = 0;
1130 u8 cable_spec = 0;
1131 u16 enforce_sfp = 0;
1132
1133 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1134 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1135 return IXGBE_ERR_SFP_NOT_PRESENT;
1136 }
1137
1138 /* LAN ID is needed for sfp_type determination */
1139 hw->mac.ops.set_lan_id(hw);
1140
1141 status = hw->phy.ops.read_i2c_eeprom(hw,
1142 IXGBE_SFF_IDENTIFIER,
1143 &identifier);
1144
1145 if (status)
1146 goto err_read_i2c_eeprom;
1147
1148 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1149 hw->phy.type = ixgbe_phy_sfp_unsupported;
1150 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1151 }
1152 status = hw->phy.ops.read_i2c_eeprom(hw,
1153 IXGBE_SFF_1GBE_COMP_CODES,
1154 &comp_codes_1g);
1155
1156 if (status)
1157 goto err_read_i2c_eeprom;
1158
1159 status = hw->phy.ops.read_i2c_eeprom(hw,
1160 IXGBE_SFF_10GBE_COMP_CODES,
1161 &comp_codes_10g);
1162
1163 if (status)
1164 goto err_read_i2c_eeprom;
1165 status = hw->phy.ops.read_i2c_eeprom(hw,
1166 IXGBE_SFF_CABLE_TECHNOLOGY,
1167 &cable_tech);
1168
1169 if (status)
1170 goto err_read_i2c_eeprom;
1171
1172 /* ID Module
1173 * =========
1174 * 0 SFP_DA_CU
1175 * 1 SFP_SR
1176 * 2 SFP_LR
1177 * 3 SFP_DA_CORE0 - 82599-specific
1178 * 4 SFP_DA_CORE1 - 82599-specific
1179 * 5 SFP_SR/LR_CORE0 - 82599-specific
1180 * 6 SFP_SR/LR_CORE1 - 82599-specific
1181 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1182 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1183 * 9 SFP_1g_cu_CORE0 - 82599-specific
1184 * 10 SFP_1g_cu_CORE1 - 82599-specific
1185 * 11 SFP_1g_sx_CORE0 - 82599-specific
1186 * 12 SFP_1g_sx_CORE1 - 82599-specific
1187 */
1188 if (hw->mac.type == ixgbe_mac_82598EB) {
1189 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1190 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1191 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1192 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1193 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1194 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1195 else
1196 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1197 } else {
1198 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1199 if (hw->bus.lan_id == 0)
1200 hw->phy.sfp_type =
1201 ixgbe_sfp_type_da_cu_core0;
1202 else
1203 hw->phy.sfp_type =
1204 ixgbe_sfp_type_da_cu_core1;
1205 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1206 hw->phy.ops.read_i2c_eeprom(
1207 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1208 &cable_spec);
1209 if (cable_spec &
1210 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1211 if (hw->bus.lan_id == 0)
1212 hw->phy.sfp_type =
1213 ixgbe_sfp_type_da_act_lmt_core0;
1214 else
1215 hw->phy.sfp_type =
1216 ixgbe_sfp_type_da_act_lmt_core1;
1217 } else {
1218 hw->phy.sfp_type =
1219 ixgbe_sfp_type_unknown;
1220 }
1221 } else if (comp_codes_10g &
1222 (IXGBE_SFF_10GBASESR_CAPABLE |
1223 IXGBE_SFF_10GBASELR_CAPABLE)) {
1224 if (hw->bus.lan_id == 0)
1225 hw->phy.sfp_type =
1226 ixgbe_sfp_type_srlr_core0;
1227 else
1228 hw->phy.sfp_type =
1229 ixgbe_sfp_type_srlr_core1;
1230 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1231 if (hw->bus.lan_id == 0)
1232 hw->phy.sfp_type =
1233 ixgbe_sfp_type_1g_cu_core0;
1234 else
1235 hw->phy.sfp_type =
1236 ixgbe_sfp_type_1g_cu_core1;
1237 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1238 if (hw->bus.lan_id == 0)
1239 hw->phy.sfp_type =
1240 ixgbe_sfp_type_1g_sx_core0;
1241 else
1242 hw->phy.sfp_type =
1243 ixgbe_sfp_type_1g_sx_core1;
1244 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1245 if (hw->bus.lan_id == 0)
1246 hw->phy.sfp_type =
1247 ixgbe_sfp_type_1g_lx_core0;
1248 else
1249 hw->phy.sfp_type =
1250 ixgbe_sfp_type_1g_lx_core1;
1251 } else {
1252 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1253 }
1254 }
1255
1256 if (hw->phy.sfp_type != stored_sfp_type)
1257 hw->phy.sfp_setup_needed = true;
1258
1259 /* Determine if the SFP+ PHY is dual speed or not. */
1260 hw->phy.multispeed_fiber = false;
1261 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1262 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1263 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1264 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1265 hw->phy.multispeed_fiber = true;
1266
1267 /* Determine PHY vendor */
1268 if (hw->phy.type != ixgbe_phy_nl) {
1269 hw->phy.id = identifier;
1270 status = hw->phy.ops.read_i2c_eeprom(hw,
1271 IXGBE_SFF_VENDOR_OUI_BYTE0,
1272 &oui_bytes[0]);
1273
1274 if (status != 0)
1275 goto err_read_i2c_eeprom;
1276
1277 status = hw->phy.ops.read_i2c_eeprom(hw,
1278 IXGBE_SFF_VENDOR_OUI_BYTE1,
1279 &oui_bytes[1]);
1280
1281 if (status != 0)
1282 goto err_read_i2c_eeprom;
1283
1284 status = hw->phy.ops.read_i2c_eeprom(hw,
1285 IXGBE_SFF_VENDOR_OUI_BYTE2,
1286 &oui_bytes[2]);
1287
1288 if (status != 0)
1289 goto err_read_i2c_eeprom;
1290
1291 vendor_oui =
1292 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1293 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1294 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1295
1296 switch (vendor_oui) {
1297 case IXGBE_SFF_VENDOR_OUI_TYCO:
1298 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1299 hw->phy.type =
1300 ixgbe_phy_sfp_passive_tyco;
1301 break;
1302 case IXGBE_SFF_VENDOR_OUI_FTL:
1303 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1304 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1305 else
1306 hw->phy.type = ixgbe_phy_sfp_ftl;
1307 break;
1308 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1309 hw->phy.type = ixgbe_phy_sfp_avago;
1310 break;
1311 case IXGBE_SFF_VENDOR_OUI_INTEL:
1312 hw->phy.type = ixgbe_phy_sfp_intel;
1313 break;
1314 default:
1315 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1316 hw->phy.type =
1317 ixgbe_phy_sfp_passive_unknown;
1318 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1319 hw->phy.type =
1320 ixgbe_phy_sfp_active_unknown;
1321 else
1322 hw->phy.type = ixgbe_phy_sfp_unknown;
1323 break;
1324 }
1325 }
1326
1327 /* Allow any DA cable vendor */
1328 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1329 IXGBE_SFF_DA_ACTIVE_CABLE))
1330 return 0;
1331
1332 /* Verify supported 1G SFP modules */
1333 if (comp_codes_10g == 0 &&
1334 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1335 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1336 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1337 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1338 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1339 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1340 hw->phy.type = ixgbe_phy_sfp_unsupported;
1341 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1342 }
1343
1344 /* Anything else 82598-based is supported */
1345 if (hw->mac.type == ixgbe_mac_82598EB)
1346 return 0;
1347
1348 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1349 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1350 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1351 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1352 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1353 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1354 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1355 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1356 /* Make sure we're a supported PHY type */
1357 if (hw->phy.type == ixgbe_phy_sfp_intel)
1358 return 0;
1359 if (hw->allow_unsupported_sfp) {
1360 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1361 return 0;
1362 }
1363 hw_dbg(hw, "SFP+ module not supported\n");
1364 hw->phy.type = ixgbe_phy_sfp_unsupported;
1365 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1366 }
1367 return 0;
1368
1369 err_read_i2c_eeprom:
1370 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1371 if (hw->phy.type != ixgbe_phy_nl) {
1372 hw->phy.id = 0;
1373 hw->phy.type = ixgbe_phy_unknown;
1374 }
1375 return IXGBE_ERR_SFP_NOT_PRESENT;
1376 }
1377
1378 /**
1379 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1380 * @hw: pointer to hardware structure
1381 *
1382 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1383 **/
1384 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1385 {
1386 struct ixgbe_adapter *adapter = hw->back;
1387 s32 status;
1388 u32 vendor_oui = 0;
1389 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1390 u8 identifier = 0;
1391 u8 comp_codes_1g = 0;
1392 u8 comp_codes_10g = 0;
1393 u8 oui_bytes[3] = {0, 0, 0};
1394 u16 enforce_sfp = 0;
1395 u8 connector = 0;
1396 u8 cable_length = 0;
1397 u8 device_tech = 0;
1398 bool active_cable = false;
1399
1400 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1401 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1402 return IXGBE_ERR_SFP_NOT_PRESENT;
1403 }
1404
1405 /* LAN ID is needed for sfp_type determination */
1406 hw->mac.ops.set_lan_id(hw);
1407
1408 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1409 &identifier);
1410
1411 if (status != 0)
1412 goto err_read_i2c_eeprom;
1413
1414 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1415 hw->phy.type = ixgbe_phy_sfp_unsupported;
1416 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1417 }
1418
1419 hw->phy.id = identifier;
1420
1421 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1422 &comp_codes_10g);
1423
1424 if (status != 0)
1425 goto err_read_i2c_eeprom;
1426
1427 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1428 &comp_codes_1g);
1429
1430 if (status != 0)
1431 goto err_read_i2c_eeprom;
1432
1433 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1434 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1435 if (hw->bus.lan_id == 0)
1436 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1437 else
1438 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1439 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1440 IXGBE_SFF_10GBASELR_CAPABLE)) {
1441 if (hw->bus.lan_id == 0)
1442 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1443 else
1444 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1445 } else {
1446 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1447 active_cable = true;
1448
1449 if (!active_cable) {
1450 /* check for active DA cables that pre-date
1451 * SFF-8436 v3.6
1452 */
1453 hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_QSFP_CONNECTOR,
1455 &connector);
1456
1457 hw->phy.ops.read_i2c_eeprom(hw,
1458 IXGBE_SFF_QSFP_CABLE_LENGTH,
1459 &cable_length);
1460
1461 hw->phy.ops.read_i2c_eeprom(hw,
1462 IXGBE_SFF_QSFP_DEVICE_TECH,
1463 &device_tech);
1464
1465 if ((connector ==
1466 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1467 (cable_length > 0) &&
1468 ((device_tech >> 4) ==
1469 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1470 active_cable = true;
1471 }
1472
1473 if (active_cable) {
1474 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1475 if (hw->bus.lan_id == 0)
1476 hw->phy.sfp_type =
1477 ixgbe_sfp_type_da_act_lmt_core0;
1478 else
1479 hw->phy.sfp_type =
1480 ixgbe_sfp_type_da_act_lmt_core1;
1481 } else {
1482 /* unsupported module type */
1483 hw->phy.type = ixgbe_phy_sfp_unsupported;
1484 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1485 }
1486 }
1487
1488 if (hw->phy.sfp_type != stored_sfp_type)
1489 hw->phy.sfp_setup_needed = true;
1490
1491 /* Determine if the QSFP+ PHY is dual speed or not. */
1492 hw->phy.multispeed_fiber = false;
1493 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1494 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1495 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1496 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1497 hw->phy.multispeed_fiber = true;
1498
1499 /* Determine PHY vendor for optical modules */
1500 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1501 IXGBE_SFF_10GBASELR_CAPABLE)) {
1502 status = hw->phy.ops.read_i2c_eeprom(hw,
1503 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1504 &oui_bytes[0]);
1505
1506 if (status != 0)
1507 goto err_read_i2c_eeprom;
1508
1509 status = hw->phy.ops.read_i2c_eeprom(hw,
1510 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1511 &oui_bytes[1]);
1512
1513 if (status != 0)
1514 goto err_read_i2c_eeprom;
1515
1516 status = hw->phy.ops.read_i2c_eeprom(hw,
1517 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1518 &oui_bytes[2]);
1519
1520 if (status != 0)
1521 goto err_read_i2c_eeprom;
1522
1523 vendor_oui =
1524 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1525 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1526 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1527
1528 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1529 hw->phy.type = ixgbe_phy_qsfp_intel;
1530 else
1531 hw->phy.type = ixgbe_phy_qsfp_unknown;
1532
1533 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1534 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1535 /* Make sure we're a supported PHY type */
1536 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1537 return 0;
1538 if (hw->allow_unsupported_sfp) {
1539 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1540 return 0;
1541 }
1542 hw_dbg(hw, "QSFP module not supported\n");
1543 hw->phy.type = ixgbe_phy_sfp_unsupported;
1544 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1545 }
1546 return 0;
1547 }
1548 return 0;
1549
1550 err_read_i2c_eeprom:
1551 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1552 hw->phy.id = 0;
1553 hw->phy.type = ixgbe_phy_unknown;
1554
1555 return IXGBE_ERR_SFP_NOT_PRESENT;
1556 }
1557
1558 /**
1559 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1560 * @hw: pointer to hardware structure
1561 * @list_offset: offset to the SFP ID list
1562 * @data_offset: offset to the SFP data block
1563 *
1564 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1565 * so it returns the offsets to the phy init sequence block.
1566 **/
1567 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1568 u16 *list_offset,
1569 u16 *data_offset)
1570 {
1571 u16 sfp_id;
1572 u16 sfp_type = hw->phy.sfp_type;
1573
1574 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1575 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1576
1577 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1578 return IXGBE_ERR_SFP_NOT_PRESENT;
1579
1580 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1581 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1582 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1583
1584 /*
1585 * Limiting active cables and 1G Phys must be initialized as
1586 * SR modules
1587 */
1588 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1589 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1590 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1591 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1592 sfp_type = ixgbe_sfp_type_srlr_core0;
1593 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1594 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1595 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1596 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1597 sfp_type = ixgbe_sfp_type_srlr_core1;
1598
1599 /* Read offset to PHY init contents */
1600 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1601 hw_err(hw, "eeprom read at %d failed\n",
1602 IXGBE_PHY_INIT_OFFSET_NL);
1603 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1604 }
1605
1606 if ((!*list_offset) || (*list_offset == 0xFFFF))
1607 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1608
1609 /* Shift offset to first ID word */
1610 (*list_offset)++;
1611
1612 /*
1613 * Find the matching SFP ID in the EEPROM
1614 * and program the init sequence
1615 */
1616 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1617 goto err_phy;
1618
1619 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1620 if (sfp_id == sfp_type) {
1621 (*list_offset)++;
1622 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1623 goto err_phy;
1624 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1625 hw_dbg(hw, "SFP+ module not supported\n");
1626 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1627 } else {
1628 break;
1629 }
1630 } else {
1631 (*list_offset) += 2;
1632 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1633 goto err_phy;
1634 }
1635 }
1636
1637 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1638 hw_dbg(hw, "No matching SFP+ module found\n");
1639 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1640 }
1641
1642 return 0;
1643
1644 err_phy:
1645 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1646 return IXGBE_ERR_PHY;
1647 }
1648
1649 /**
1650 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1651 * @hw: pointer to hardware structure
1652 * @byte_offset: EEPROM byte offset to read
1653 * @eeprom_data: value read
1654 *
1655 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1656 **/
1657 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1658 u8 *eeprom_data)
1659 {
1660 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1661 IXGBE_I2C_EEPROM_DEV_ADDR,
1662 eeprom_data);
1663 }
1664
1665 /**
1666 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1667 * @hw: pointer to hardware structure
1668 * @byte_offset: byte offset at address 0xA2
1669 * @eeprom_data: value read
1670 *
1671 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1672 **/
1673 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1674 u8 *sff8472_data)
1675 {
1676 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1677 IXGBE_I2C_EEPROM_DEV_ADDR2,
1678 sff8472_data);
1679 }
1680
1681 /**
1682 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1683 * @hw: pointer to hardware structure
1684 * @byte_offset: EEPROM byte offset to write
1685 * @eeprom_data: value to write
1686 *
1687 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1688 **/
1689 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1690 u8 eeprom_data)
1691 {
1692 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1693 IXGBE_I2C_EEPROM_DEV_ADDR,
1694 eeprom_data);
1695 }
1696
1697 /**
1698 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1699 * @hw: pointer to hardware structure
1700 * @offset: eeprom offset to be read
1701 * @addr: I2C address to be read
1702 */
1703 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1704 {
1705 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1706 offset == IXGBE_SFF_IDENTIFIER &&
1707 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1708 return true;
1709 return false;
1710 }
1711
1712 /**
1713 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1714 * @hw: pointer to hardware structure
1715 * @byte_offset: byte offset to read
1716 * @data: value read
1717 * @lock: true if to take and release semaphore
1718 *
1719 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1720 * a specified device address.
1721 */
1722 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1723 u8 dev_addr, u8 *data, bool lock)
1724 {
1725 s32 status;
1726 u32 max_retry = 10;
1727 u32 retry = 0;
1728 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1729 bool nack = true;
1730
1731 if (hw->mac.type >= ixgbe_mac_X550)
1732 max_retry = 3;
1733 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1734 max_retry = IXGBE_SFP_DETECT_RETRIES;
1735
1736 *data = 0;
1737
1738 do {
1739 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1740 return IXGBE_ERR_SWFW_SYNC;
1741
1742 ixgbe_i2c_start(hw);
1743
1744 /* Device Address and write indication */
1745 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1746 if (status != 0)
1747 goto fail;
1748
1749 status = ixgbe_get_i2c_ack(hw);
1750 if (status != 0)
1751 goto fail;
1752
1753 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1754 if (status != 0)
1755 goto fail;
1756
1757 status = ixgbe_get_i2c_ack(hw);
1758 if (status != 0)
1759 goto fail;
1760
1761 ixgbe_i2c_start(hw);
1762
1763 /* Device Address and read indication */
1764 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1765 if (status != 0)
1766 goto fail;
1767
1768 status = ixgbe_get_i2c_ack(hw);
1769 if (status != 0)
1770 goto fail;
1771
1772 status = ixgbe_clock_in_i2c_byte(hw, data);
1773 if (status != 0)
1774 goto fail;
1775
1776 status = ixgbe_clock_out_i2c_bit(hw, nack);
1777 if (status != 0)
1778 goto fail;
1779
1780 ixgbe_i2c_stop(hw);
1781 if (lock)
1782 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1783 return 0;
1784
1785 fail:
1786 ixgbe_i2c_bus_clear(hw);
1787 if (lock) {
1788 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1789 msleep(100);
1790 }
1791 retry++;
1792 if (retry < max_retry)
1793 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1794 else
1795 hw_dbg(hw, "I2C byte read error.\n");
1796
1797 } while (retry < max_retry);
1798
1799 return status;
1800 }
1801
1802 /**
1803 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1804 * @hw: pointer to hardware structure
1805 * @byte_offset: byte offset to read
1806 * @data: value read
1807 *
1808 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1809 * a specified device address.
1810 */
1811 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1812 u8 dev_addr, u8 *data)
1813 {
1814 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1815 data, true);
1816 }
1817
1818 /**
1819 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
1820 * @hw: pointer to hardware structure
1821 * @byte_offset: byte offset to read
1822 * @data: value read
1823 *
1824 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1825 * a specified device address.
1826 */
1827 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1828 u8 dev_addr, u8 *data)
1829 {
1830 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1831 data, false);
1832 }
1833
1834 /**
1835 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
1836 * @hw: pointer to hardware structure
1837 * @byte_offset: byte offset to write
1838 * @data: value to write
1839 * @lock: true if to take and release semaphore
1840 *
1841 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1842 * a specified device address.
1843 */
1844 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1845 u8 dev_addr, u8 data, bool lock)
1846 {
1847 s32 status;
1848 u32 max_retry = 1;
1849 u32 retry = 0;
1850 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1851
1852 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1853 return IXGBE_ERR_SWFW_SYNC;
1854
1855 do {
1856 ixgbe_i2c_start(hw);
1857
1858 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1859 if (status != 0)
1860 goto fail;
1861
1862 status = ixgbe_get_i2c_ack(hw);
1863 if (status != 0)
1864 goto fail;
1865
1866 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1867 if (status != 0)
1868 goto fail;
1869
1870 status = ixgbe_get_i2c_ack(hw);
1871 if (status != 0)
1872 goto fail;
1873
1874 status = ixgbe_clock_out_i2c_byte(hw, data);
1875 if (status != 0)
1876 goto fail;
1877
1878 status = ixgbe_get_i2c_ack(hw);
1879 if (status != 0)
1880 goto fail;
1881
1882 ixgbe_i2c_stop(hw);
1883 if (lock)
1884 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1885 return 0;
1886
1887 fail:
1888 ixgbe_i2c_bus_clear(hw);
1889 retry++;
1890 if (retry < max_retry)
1891 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1892 else
1893 hw_dbg(hw, "I2C byte write error.\n");
1894 } while (retry < max_retry);
1895
1896 if (lock)
1897 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1898
1899 return status;
1900 }
1901
1902 /**
1903 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1904 * @hw: pointer to hardware structure
1905 * @byte_offset: byte offset to write
1906 * @data: value to write
1907 *
1908 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1909 * a specified device address.
1910 */
1911 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1912 u8 dev_addr, u8 data)
1913 {
1914 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1915 data, true);
1916 }
1917
1918 /**
1919 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
1920 * @hw: pointer to hardware structure
1921 * @byte_offset: byte offset to write
1922 * @data: value to write
1923 *
1924 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1925 * a specified device address.
1926 */
1927 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1928 u8 dev_addr, u8 data)
1929 {
1930 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1931 data, false);
1932 }
1933
1934 /**
1935 * ixgbe_i2c_start - Sets I2C start condition
1936 * @hw: pointer to hardware structure
1937 *
1938 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1939 * Set bit-bang mode on X550 hardware.
1940 **/
1941 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1942 {
1943 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1944
1945 i2cctl |= IXGBE_I2C_BB_EN(hw);
1946
1947 /* Start condition must begin with data and clock high */
1948 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1949 ixgbe_raise_i2c_clk(hw, &i2cctl);
1950
1951 /* Setup time for start condition (4.7us) */
1952 udelay(IXGBE_I2C_T_SU_STA);
1953
1954 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1955
1956 /* Hold time for start condition (4us) */
1957 udelay(IXGBE_I2C_T_HD_STA);
1958
1959 ixgbe_lower_i2c_clk(hw, &i2cctl);
1960
1961 /* Minimum low period of clock is 4.7 us */
1962 udelay(IXGBE_I2C_T_LOW);
1963
1964 }
1965
1966 /**
1967 * ixgbe_i2c_stop - Sets I2C stop condition
1968 * @hw: pointer to hardware structure
1969 *
1970 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1971 * Disables bit-bang mode and negates data output enable on X550
1972 * hardware.
1973 **/
1974 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1975 {
1976 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1977 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
1978 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
1979 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
1980
1981 /* Stop condition must begin with data low and clock high */
1982 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1983 ixgbe_raise_i2c_clk(hw, &i2cctl);
1984
1985 /* Setup time for stop condition (4us) */
1986 udelay(IXGBE_I2C_T_SU_STO);
1987
1988 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1989
1990 /* bus free time between stop and start (4.7us)*/
1991 udelay(IXGBE_I2C_T_BUF);
1992
1993 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
1994 i2cctl &= ~bb_en_bit;
1995 i2cctl |= data_oe_bit | clk_oe_bit;
1996 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
1997 IXGBE_WRITE_FLUSH(hw);
1998 }
1999 }
2000
2001 /**
2002 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2003 * @hw: pointer to hardware structure
2004 * @data: data byte to clock in
2005 *
2006 * Clocks in one byte data via I2C data/clock
2007 **/
2008 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2009 {
2010 s32 i;
2011 bool bit = false;
2012
2013 *data = 0;
2014 for (i = 7; i >= 0; i--) {
2015 ixgbe_clock_in_i2c_bit(hw, &bit);
2016 *data |= bit << i;
2017 }
2018
2019 return 0;
2020 }
2021
2022 /**
2023 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2024 * @hw: pointer to hardware structure
2025 * @data: data byte clocked out
2026 *
2027 * Clocks out one byte data via I2C data/clock
2028 **/
2029 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2030 {
2031 s32 status;
2032 s32 i;
2033 u32 i2cctl;
2034 bool bit = false;
2035
2036 for (i = 7; i >= 0; i--) {
2037 bit = (data >> i) & 0x1;
2038 status = ixgbe_clock_out_i2c_bit(hw, bit);
2039
2040 if (status != 0)
2041 break;
2042 }
2043
2044 /* Release SDA line (set high) */
2045 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2046 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2047 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2048 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2049 IXGBE_WRITE_FLUSH(hw);
2050
2051 return status;
2052 }
2053
2054 /**
2055 * ixgbe_get_i2c_ack - Polls for I2C ACK
2056 * @hw: pointer to hardware structure
2057 *
2058 * Clocks in/out one bit via I2C data/clock
2059 **/
2060 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2061 {
2062 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2063 s32 status = 0;
2064 u32 i = 0;
2065 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2066 u32 timeout = 10;
2067 bool ack = true;
2068
2069 if (data_oe_bit) {
2070 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2071 i2cctl |= data_oe_bit;
2072 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2073 IXGBE_WRITE_FLUSH(hw);
2074 }
2075 ixgbe_raise_i2c_clk(hw, &i2cctl);
2076
2077 /* Minimum high period of clock is 4us */
2078 udelay(IXGBE_I2C_T_HIGH);
2079
2080 /* Poll for ACK. Note that ACK in I2C spec is
2081 * transition from 1 to 0 */
2082 for (i = 0; i < timeout; i++) {
2083 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2084 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2085
2086 udelay(1);
2087 if (ack == 0)
2088 break;
2089 }
2090
2091 if (ack == 1) {
2092 hw_dbg(hw, "I2C ack was not received.\n");
2093 status = IXGBE_ERR_I2C;
2094 }
2095
2096 ixgbe_lower_i2c_clk(hw, &i2cctl);
2097
2098 /* Minimum low period of clock is 4.7 us */
2099 udelay(IXGBE_I2C_T_LOW);
2100
2101 return status;
2102 }
2103
2104 /**
2105 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2106 * @hw: pointer to hardware structure
2107 * @data: read data value
2108 *
2109 * Clocks in one bit via I2C data/clock
2110 **/
2111 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2112 {
2113 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2114 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2115
2116 if (data_oe_bit) {
2117 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2118 i2cctl |= data_oe_bit;
2119 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2120 IXGBE_WRITE_FLUSH(hw);
2121 }
2122 ixgbe_raise_i2c_clk(hw, &i2cctl);
2123
2124 /* Minimum high period of clock is 4us */
2125 udelay(IXGBE_I2C_T_HIGH);
2126
2127 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2128 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2129
2130 ixgbe_lower_i2c_clk(hw, &i2cctl);
2131
2132 /* Minimum low period of clock is 4.7 us */
2133 udelay(IXGBE_I2C_T_LOW);
2134
2135 return 0;
2136 }
2137
2138 /**
2139 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2140 * @hw: pointer to hardware structure
2141 * @data: data value to write
2142 *
2143 * Clocks out one bit via I2C data/clock
2144 **/
2145 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2146 {
2147 s32 status;
2148 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2149
2150 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2151 if (status == 0) {
2152 ixgbe_raise_i2c_clk(hw, &i2cctl);
2153
2154 /* Minimum high period of clock is 4us */
2155 udelay(IXGBE_I2C_T_HIGH);
2156
2157 ixgbe_lower_i2c_clk(hw, &i2cctl);
2158
2159 /* Minimum low period of clock is 4.7 us.
2160 * This also takes care of the data hold time.
2161 */
2162 udelay(IXGBE_I2C_T_LOW);
2163 } else {
2164 hw_dbg(hw, "I2C data was not set to %X\n", data);
2165 return IXGBE_ERR_I2C;
2166 }
2167
2168 return 0;
2169 }
2170 /**
2171 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2172 * @hw: pointer to hardware structure
2173 * @i2cctl: Current value of I2CCTL register
2174 *
2175 * Raises the I2C clock line '0'->'1'
2176 * Negates the I2C clock output enable on X550 hardware.
2177 **/
2178 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2179 {
2180 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2181 u32 i = 0;
2182 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2183 u32 i2cctl_r = 0;
2184
2185 if (clk_oe_bit) {
2186 *i2cctl |= clk_oe_bit;
2187 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2188 }
2189
2190 for (i = 0; i < timeout; i++) {
2191 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2192 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2193 IXGBE_WRITE_FLUSH(hw);
2194 /* SCL rise time (1000ns) */
2195 udelay(IXGBE_I2C_T_RISE);
2196
2197 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2198 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2199 break;
2200 }
2201 }
2202
2203 /**
2204 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2205 * @hw: pointer to hardware structure
2206 * @i2cctl: Current value of I2CCTL register
2207 *
2208 * Lowers the I2C clock line '1'->'0'
2209 * Asserts the I2C clock output enable on X550 hardware.
2210 **/
2211 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2212 {
2213
2214 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2215 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2216
2217 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2218 IXGBE_WRITE_FLUSH(hw);
2219
2220 /* SCL fall time (300ns) */
2221 udelay(IXGBE_I2C_T_FALL);
2222 }
2223
2224 /**
2225 * ixgbe_set_i2c_data - Sets the I2C data bit
2226 * @hw: pointer to hardware structure
2227 * @i2cctl: Current value of I2CCTL register
2228 * @data: I2C data value (0 or 1) to set
2229 *
2230 * Sets the I2C data bit
2231 * Asserts the I2C data output enable on X550 hardware.
2232 **/
2233 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2234 {
2235 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2236
2237 if (data)
2238 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2239 else
2240 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2241 *i2cctl &= ~data_oe_bit;
2242
2243 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2244 IXGBE_WRITE_FLUSH(hw);
2245
2246 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2247 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2248
2249 if (!data) /* Can't verify data in this case */
2250 return 0;
2251 if (data_oe_bit) {
2252 *i2cctl |= data_oe_bit;
2253 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2254 IXGBE_WRITE_FLUSH(hw);
2255 }
2256
2257 /* Verify data was set correctly */
2258 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2259 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2260 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2261 return IXGBE_ERR_I2C;
2262 }
2263
2264 return 0;
2265 }
2266
2267 /**
2268 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2269 * @hw: pointer to hardware structure
2270 * @i2cctl: Current value of I2CCTL register
2271 *
2272 * Returns the I2C data bit value
2273 * Negates the I2C data output enable on X550 hardware.
2274 **/
2275 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2276 {
2277 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2278
2279 if (data_oe_bit) {
2280 *i2cctl |= data_oe_bit;
2281 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2282 IXGBE_WRITE_FLUSH(hw);
2283 udelay(IXGBE_I2C_T_FALL);
2284 }
2285
2286 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2287 return true;
2288 return false;
2289 }
2290
2291 /**
2292 * ixgbe_i2c_bus_clear - Clears the I2C bus
2293 * @hw: pointer to hardware structure
2294 *
2295 * Clears the I2C bus by sending nine clock pulses.
2296 * Used when data line is stuck low.
2297 **/
2298 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2299 {
2300 u32 i2cctl;
2301 u32 i;
2302
2303 ixgbe_i2c_start(hw);
2304 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2305
2306 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2307
2308 for (i = 0; i < 9; i++) {
2309 ixgbe_raise_i2c_clk(hw, &i2cctl);
2310
2311 /* Min high period of clock is 4us */
2312 udelay(IXGBE_I2C_T_HIGH);
2313
2314 ixgbe_lower_i2c_clk(hw, &i2cctl);
2315
2316 /* Min low period of clock is 4.7us*/
2317 udelay(IXGBE_I2C_T_LOW);
2318 }
2319
2320 ixgbe_i2c_start(hw);
2321
2322 /* Put the i2c bus back to default state */
2323 ixgbe_i2c_stop(hw);
2324 }
2325
2326 /**
2327 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2328 * @hw: pointer to hardware structure
2329 *
2330 * Checks if the LASI temp alarm status was triggered due to overtemp
2331 **/
2332 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2333 {
2334 u16 phy_data = 0;
2335
2336 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2337 return 0;
2338
2339 /* Check that the LASI temp alarm status was triggered */
2340 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2341 MDIO_MMD_PMAPMD, &phy_data);
2342
2343 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2344 return 0;
2345
2346 return IXGBE_ERR_OVERTEMP;
2347 }
2348
2349 /** ixgbe_set_copper_phy_power - Control power for copper phy
2350 * @hw: pointer to hardware structure
2351 * @on: true for on, false for off
2352 **/
2353 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2354 {
2355 u32 status;
2356 u16 reg;
2357
2358 /* Bail if we don't have copper phy */
2359 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2360 return 0;
2361
2362 if (!on && ixgbe_mng_present(hw))
2363 return 0;
2364
2365 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2366 if (status)
2367 return status;
2368
2369 if (on) {
2370 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2371 } else {
2372 if (ixgbe_check_reset_blocked(hw))
2373 return 0;
2374 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2375 }
2376
2377 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2378 return status;
2379 }
Linux with added FPC-III support