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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / skge.h
blob3ea151ff9c432ef9b693e26056c40ce083bca5ea
1 /*
2 * Definitions for the new Marvell Yukon / SysKonnect driver.
3 */
4 #ifndef _SKGE_H
5 #define _SKGE_H
6 #include <linux/interrupt.h>
7
8 /* PCI config registers */
9 #define PCI_DEV_REG1 0x40
10 #define PCI_PHY_COMA 0x8000000
11 #define PCI_VIO 0x2000000
12
13 #define PCI_DEV_REG2 0x44
14 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
15 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
16
17 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
18 PCI_STATUS_SIG_SYSTEM_ERROR | \
19 PCI_STATUS_REC_MASTER_ABORT | \
20 PCI_STATUS_REC_TARGET_ABORT | \
21 PCI_STATUS_PARITY)
22
23 enum csr_regs {
24 B0_RAP = 0x0000,
25 B0_CTST = 0x0004,
26 B0_LED = 0x0006,
27 B0_POWER_CTRL = 0x0007,
28 B0_ISRC = 0x0008,
29 B0_IMSK = 0x000c,
30 B0_HWE_ISRC = 0x0010,
31 B0_HWE_IMSK = 0x0014,
32 B0_SP_ISRC = 0x0018,
33 B0_XM1_IMSK = 0x0020,
34 B0_XM1_ISRC = 0x0028,
35 B0_XM1_PHY_ADDR = 0x0030,
36 B0_XM1_PHY_DATA = 0x0034,
37 B0_XM2_IMSK = 0x0040,
38 B0_XM2_ISRC = 0x0048,
39 B0_XM2_PHY_ADDR = 0x0050,
40 B0_XM2_PHY_DATA = 0x0054,
41 B0_R1_CSR = 0x0060,
42 B0_R2_CSR = 0x0064,
43 B0_XS1_CSR = 0x0068,
44 B0_XA1_CSR = 0x006c,
45 B0_XS2_CSR = 0x0070,
46 B0_XA2_CSR = 0x0074,
47
48 B2_MAC_1 = 0x0100,
49 B2_MAC_2 = 0x0108,
50 B2_MAC_3 = 0x0110,
51 B2_CONN_TYP = 0x0118,
52 B2_PMD_TYP = 0x0119,
53 B2_MAC_CFG = 0x011a,
54 B2_CHIP_ID = 0x011b,
55 B2_E_0 = 0x011c,
56 B2_E_1 = 0x011d,
57 B2_E_2 = 0x011e,
58 B2_E_3 = 0x011f,
59 B2_FAR = 0x0120,
60 B2_FDP = 0x0124,
61 B2_LD_CTRL = 0x0128,
62 B2_LD_TEST = 0x0129,
63 B2_TI_INI = 0x0130,
64 B2_TI_VAL = 0x0134,
65 B2_TI_CTRL = 0x0138,
66 B2_TI_TEST = 0x0139,
67 B2_IRQM_INI = 0x0140,
68 B2_IRQM_VAL = 0x0144,
69 B2_IRQM_CTRL = 0x0148,
70 B2_IRQM_TEST = 0x0149,
71 B2_IRQM_MSK = 0x014c,
72 B2_IRQM_HWE_MSK = 0x0150,
73 B2_TST_CTRL1 = 0x0158,
74 B2_TST_CTRL2 = 0x0159,
75 B2_GP_IO = 0x015c,
76 B2_I2C_CTRL = 0x0160,
77 B2_I2C_DATA = 0x0164,
78 B2_I2C_IRQ = 0x0168,
79 B2_I2C_SW = 0x016c,
80 B2_BSC_INI = 0x0170,
81 B2_BSC_VAL = 0x0174,
82 B2_BSC_CTRL = 0x0178,
83 B2_BSC_STAT = 0x0179,
84 B2_BSC_TST = 0x017a,
85
86 B3_RAM_ADDR = 0x0180,
87 B3_RAM_DATA_LO = 0x0184,
88 B3_RAM_DATA_HI = 0x0188,
89 B3_RI_WTO_R1 = 0x0190,
90 B3_RI_WTO_XA1 = 0x0191,
91 B3_RI_WTO_XS1 = 0x0192,
92 B3_RI_RTO_R1 = 0x0193,
93 B3_RI_RTO_XA1 = 0x0194,
94 B3_RI_RTO_XS1 = 0x0195,
95 B3_RI_WTO_R2 = 0x0196,
96 B3_RI_WTO_XA2 = 0x0197,
97 B3_RI_WTO_XS2 = 0x0198,
98 B3_RI_RTO_R2 = 0x0199,
99 B3_RI_RTO_XA2 = 0x019a,
100 B3_RI_RTO_XS2 = 0x019b,
101 B3_RI_TO_VAL = 0x019c,
102 B3_RI_CTRL = 0x01a0,
103 B3_RI_TEST = 0x01a2,
104 B3_MA_TOINI_RX1 = 0x01b0,
105 B3_MA_TOINI_RX2 = 0x01b1,
106 B3_MA_TOINI_TX1 = 0x01b2,
107 B3_MA_TOINI_TX2 = 0x01b3,
108 B3_MA_TOVAL_RX1 = 0x01b4,
109 B3_MA_TOVAL_RX2 = 0x01b5,
110 B3_MA_TOVAL_TX1 = 0x01b6,
111 B3_MA_TOVAL_TX2 = 0x01b7,
112 B3_MA_TO_CTRL = 0x01b8,
113 B3_MA_TO_TEST = 0x01ba,
114 B3_MA_RCINI_RX1 = 0x01c0,
115 B3_MA_RCINI_RX2 = 0x01c1,
116 B3_MA_RCINI_TX1 = 0x01c2,
117 B3_MA_RCINI_TX2 = 0x01c3,
118 B3_MA_RCVAL_RX1 = 0x01c4,
119 B3_MA_RCVAL_RX2 = 0x01c5,
120 B3_MA_RCVAL_TX1 = 0x01c6,
121 B3_MA_RCVAL_TX2 = 0x01c7,
122 B3_MA_RC_CTRL = 0x01c8,
123 B3_MA_RC_TEST = 0x01ca,
124 B3_PA_TOINI_RX1 = 0x01d0,
125 B3_PA_TOINI_RX2 = 0x01d4,
126 B3_PA_TOINI_TX1 = 0x01d8,
127 B3_PA_TOINI_TX2 = 0x01dc,
128 B3_PA_TOVAL_RX1 = 0x01e0,
129 B3_PA_TOVAL_RX2 = 0x01e4,
130 B3_PA_TOVAL_TX1 = 0x01e8,
131 B3_PA_TOVAL_TX2 = 0x01ec,
132 B3_PA_CTRL = 0x01f0,
133 B3_PA_TEST = 0x01f2,
134 };
135
136 /* B0_CTST 16 bit Control/Status register */
137 enum {
138 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
139 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
140 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
141 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
142 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
143 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
144 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
145 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
146 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
147 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 CS_MRST_CLR = 1<<3, /* Clear Master reset */
149 CS_MRST_SET = 1<<2, /* Set Master reset */
150 CS_RST_CLR = 1<<1, /* Clear Software reset */
151 CS_RST_SET = 1, /* Set Software reset */
152
153 /* B0_LED 8 Bit LED register */
154 /* Bit 7.. 2: reserved */
155 LED_STAT_ON = 1<<1, /* Status LED on */
156 LED_STAT_OFF = 1, /* Status LED off */
157
158 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
159 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
160 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
161 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
162 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
163 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
164 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
165 PC_VCC_ON = 1<<1, /* Switch VCC On */
166 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
167 };
168
169 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
170 enum {
171 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
172 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
173 /* Bit 30: reserved */
174 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
175 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
176 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
177 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
178 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
179 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
180 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
181 /* IRQ from PHY (YUKON only) */
182 IS_TIMINT = 1<<22, /* IRQ from Timer */
183 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
184 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
185 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
186 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
187 /* Receive Queue 1 */
188 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
189 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
190 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
191 /* Receive Queue 2 */
192 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
193 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
194 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
195 /* Synchronous Transmit Queue 1 */
196 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
197 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
198 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
199 /* Asynchronous Transmit Queue 1 */
200 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
201 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
202 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
203 /* Synchronous Transmit Queue 2 */
204 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
205 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
206 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
207 /* Asynchronous Transmit Queue 2 */
208 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
209 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
210 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
211
212 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
213 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
214
215 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
216 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
217 };
218
219
220 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
221 enum {
222 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
223 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
224 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
225 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
226 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
227 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
228 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
229 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
230 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
231 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
232 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
233 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
234 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
235 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
236
237 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
238 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
239 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
240 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
241 };
242
243 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
244 enum {
245 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
246 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
247 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
248 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
249 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
250 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
251 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
252 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
253 };
254
255 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
256 enum {
257 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
258 /* Bit 3.. 2: reserved */
259 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
260 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
261 };
262
263 /* B2_CHIP_ID 8 bit Chip Identification Number */
264 enum {
265 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
266 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
267 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
268 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
269 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
270 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
271 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
272
273 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
274 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
275 };
276
277 /* B2_TI_CTRL 8 bit Timer control */
278 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
279 enum {
280 TIM_START = 1<<2, /* Start Timer */
281 TIM_STOP = 1<<1, /* Stop Timer */
282 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
283 };
284
285 /* B2_TI_TEST 8 Bit Timer Test */
286 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
287 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
288 enum {
289 TIM_T_ON = 1<<2, /* Test mode on */
290 TIM_T_OFF = 1<<1, /* Test mode off */
291 TIM_T_STEP = 1<<0, /* Test step */
292 };
293
294 /* B2_GP_IO 32 bit General Purpose I/O Register */
295 enum {
296 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
297 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
298 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
299 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
300 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
301 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
302 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
303 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
304 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
305 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
306
307 GP_IO_9 = 1<<9, /* IO_9 pin */
308 GP_IO_8 = 1<<8, /* IO_8 pin */
309 GP_IO_7 = 1<<7, /* IO_7 pin */
310 GP_IO_6 = 1<<6, /* IO_6 pin */
311 GP_IO_5 = 1<<5, /* IO_5 pin */
312 GP_IO_4 = 1<<4, /* IO_4 pin */
313 GP_IO_3 = 1<<3, /* IO_3 pin */
314 GP_IO_2 = 1<<2, /* IO_2 pin */
315 GP_IO_1 = 1<<1, /* IO_1 pin */
316 GP_IO_0 = 1<<0, /* IO_0 pin */
317 };
318
319 /* Descriptor Bit Definition */
320 /* TxCtrl Transmit Buffer Control Field */
321 /* RxCtrl Receive Buffer Control Field */
322 enum {
323 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
324 BMU_STF = 1<<30, /* Start of Frame */
325 BMU_EOF = 1<<29, /* End of Frame */
326 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
327 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
328 /* TxCtrl specific bits */
329 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
330 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
331 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
332 /* RxCtrl specific bits */
333 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
334 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
335 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
336 /* Bit 23..16: BMU Check Opcodes */
337 BMU_CHECK = 0x55<<16, /* Default BMU check */
338 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
339 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
340 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
341 };
342
343 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
344 enum {
345 BSC_START = 1<<1, /* Start Blink Source Counter */
346 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
347 };
348
349 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
350 enum {
351 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
352 };
353
354 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
355 enum {
356 BSC_T_ON = 1<<2, /* Test mode on */
357 BSC_T_OFF = 1<<1, /* Test mode off */
358 BSC_T_STEP = 1<<0, /* Test step */
359 };
360
361 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
362 /* Bit 31..19: reserved */
363 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
364 /* RAM Interface Registers */
365
366 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
367 enum {
368 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
369 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
370
371 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
372 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
373 };
374
375 /* MAC Arbiter Registers */
376 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
377 enum {
378 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
379 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
380 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
381 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
382
383 };
384
385 /* Timeout values */
386 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
387 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
388 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
389 #define SK_RI_TO_53 36 /* RAM interface timeout */
390
391 /* Packet Arbiter Registers */
392 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
393 enum {
394 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
395 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
396 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
397 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
398 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
399 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
400 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
401 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
402 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
403 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
404 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
405 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
406 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
407 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
408 };
409
410 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
411 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
412
413
414 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
415 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
416 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
417 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
418 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
419
420 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
421
422 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
423 enum {
424 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
425 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
426 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
427 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
428 TXA_START_RC = 1<<3, /* Start sync Rate Control */
429 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
430 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
431 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
432 };
433
434 /*
435 * Bank 4 - 5
436 */
437 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
438 enum {
439 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
440 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
441 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
442 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
443 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
444 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
445 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
446 };
447
448
449 enum {
450 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
451 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
452 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
453 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
454 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
455 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
456 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
457 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
458 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
459 };
460
461 /* Queue Register Offsets, use Q_ADDR() to access */
462 enum {
463 B8_Q_REGS = 0x0400, /* base of Queue registers */
464 Q_D = 0x00, /* 8*32 bit Current Descriptor */
465 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
466 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
467 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
468 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
469 Q_BC = 0x30, /* 32 bit Current Byte Counter */
470 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
471 Q_F = 0x38, /* 32 bit Flag Register */
472 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
473 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
474 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
475 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
476 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
477 Q_T2 = 0x40, /* 32 bit Test Register 2 */
478 Q_T3 = 0x44, /* 32 bit Test Register 3 */
479
480 };
481 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
482
483 /* RAM Buffer Register Offsets */
484 enum {
485
486 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
487 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
488 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
489 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
490 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
491 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
492 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
493 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
494 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
495 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
496 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
497 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
498 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
499 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
500 };
501
502 /* Receive and Transmit Queues */
503 enum {
504 Q_R1 = 0x0000, /* Receive Queue 1 */
505 Q_R2 = 0x0080, /* Receive Queue 2 */
506 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
507 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
508 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
509 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
510 };
511
512 /* Different MAC Types */
513 enum {
514 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
515 SK_MAC_GMAC = 1, /* Marvell GMAC */
516 };
517
518 /* Different PHY Types */
519 enum {
520 SK_PHY_XMAC = 0,/* integrated in XMAC II */
521 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
522 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
523 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
524 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
525 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
526 };
527
528 /* PHY addresses (bits 12..8 of PHY address reg) */
529 enum {
530 PHY_ADDR_XMAC = 0<<8,
531 PHY_ADDR_BCOM = 1<<8,
532
533 /* GPHY address (bits 15..11 of SMI control reg) */
534 PHY_ADDR_MARV = 0,
535 };
536
537 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
538
539 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
540 enum {
541 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
542 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
543
544 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
545 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
546 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
547 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
548 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
549 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
550 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
551 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
552 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
553
554 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
555 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
556 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
557 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
558
559 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
560 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
561 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
562 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
563 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
564 };
565
566 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
567 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
568 enum {
569 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
570 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
571 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
572 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
573 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
574 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
575 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
576 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
577 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
578 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
579 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
580 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
581 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
582 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
583 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
584 };
585
586 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
587 enum {
588 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
589
590 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
591 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
592
593 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
594 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
595
596 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
597 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
598 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
599 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
600
601 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
602 };
603
604
605 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
606 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
607 enum {
608 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
609 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
610 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
611 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
612 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
613 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
614 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
615 };
616
617 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
618 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
619 enum {
620 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
621 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
622 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
623
624 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
625 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
626 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
627 };
628
629 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
630 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
631 enum {
632 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
633 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
634 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
635 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
636 };
637
638
639 /* Link LED Counter Registers (GENESIS only) */
640
641 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
642 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
643 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
644 enum {
645 LED_START = 1<<2, /* Start Timer */
646 LED_STOP = 1<<1, /* Stop Timer */
647 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
648 };
649
650 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
651 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
652 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
653 enum {
654 LED_T_ON = 1<<2, /* LED Counter Test mode On */
655 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
656 LED_T_STEP = 1<<0, /* LED Counter Step */
657 };
658
659 /* LNK_LED_REG 8 bit Link LED Register */
660 enum {
661 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
662 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
663 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
664 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
665 LED_REG_ON = 1<<1, /* switch LED on */
666 LED_REG_OFF = 1<<0, /* switch LED off */
667 };
668
669 /* Receive GMAC FIFO (YUKON) */
670 enum {
671 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
672 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
673 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
674 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
675 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
676 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
677 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
678 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
679 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
680 };
681
682
683 /* TXA_TEST 8 bit Tx Arbiter Test Register */
684 enum {
685 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
686 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
687 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
688 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
689 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
690 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
691 };
692
693 /* TXA_STAT 8 bit Tx Arbiter Status Register */
694 enum {
695 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
696 };
697
698
699 /* Q_BC 32 bit Current Byte Counter */
700
701 /* BMU Control Status Registers */
702 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
703 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
704 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
705 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
706 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
707 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
708 /* Q_CSR 32 bit BMU Control/Status Register */
709
710 enum {
711 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
712
713 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
714 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
715 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
716 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
717 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
718 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
719 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
720 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
721 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
722 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
723 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
724 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
725 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
726 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
727 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
728 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
729 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
730 CSR_START = 1<<4, /* Start Rx/Tx Queue */
731 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
732 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
733 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
734 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
735 };
736
737 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
738 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
739 CSR_TRANS_RST)
740 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
741 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
742 CSR_TRANS_RUN)
743
744 /* Q_F 32 bit Flag Register */
745 enum {
746 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
747 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
748 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
749 F_WM_REACHED = 1<<25, /* Watermark reached */
750
751 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
752 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
753 };
754
755 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
756 /* RB_START 32 bit RAM Buffer Start Address */
757 /* RB_END 32 bit RAM Buffer End Address */
758 /* RB_WP 32 bit RAM Buffer Write Pointer */
759 /* RB_RP 32 bit RAM Buffer Read Pointer */
760 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
761 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
762 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
763 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
764 /* RB_PC 32 bit RAM Buffer Packet Counter */
765 /* RB_LEV 32 bit RAM Buffer Level Register */
766
767 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
768 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
769 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
770
771 /* RB_CTRL 8 bit RAM Buffer Control Register */
772 enum {
773 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
774 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
775 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
776 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
777 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
778 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
779 };
780
781 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
782 enum {
783 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
784 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
785 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
786 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
787 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
788 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
789 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
790 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
791
792 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
793 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
794 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
795
796 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
797 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
798 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
799 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
800 };
801
802 /* Counter and Timer constants, for a host clock of 62.5 MHz */
803 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
804 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
805
806 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
807
808 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
809 /* 215 ms at 78.12 MHz */
810
811 #define SK_FACT_62 100 /* is given in percent */
812 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
813 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
814
815
816 /* Transmit GMAC FIFO (YUKON only) */
817 enum {
818 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
819 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
820 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
821
822 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
823 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
824 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
825
826 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
827 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
828 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
829
830 /* Descriptor Poll Timer Registers */
831 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
832 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
833 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
834
835 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
836
837 /* Time Stamp Timer Registers (YUKON only) */
838 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
839 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
840 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
841 };
842
843
844 enum {
845 LINKLED_OFF = 0x01,
846 LINKLED_ON = 0x02,
847 LINKLED_LINKSYNC_OFF = 0x04,
848 LINKLED_LINKSYNC_ON = 0x08,
849 LINKLED_BLINK_OFF = 0x10,
850 LINKLED_BLINK_ON = 0x20,
851 };
852
853 /* GMAC and GPHY Control Registers (YUKON only) */
854 enum {
855 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
856 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
857 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
858 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
859 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
860
861 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
862
863 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
864
865 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
866 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
867 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
868 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
869 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
870
871 /* WOL Pattern Length Registers (YUKON only) */
872
873 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
874 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
875
876 /* WOL Pattern Counter Registers (YUKON only) */
877
878 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
879 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
880 };
881 #define WOL_REGS(port, x) (x + (port)*0x80)
882
883 enum {
884 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
885 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
886 };
887 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
888
889 enum {
890 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
891 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
892 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
893 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
894 };
895
896 /*
897 * Receive Frame Status Encoding
898 */
899 enum {
900 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
901 XMR_FS_LEN_SHIFT = 18,
902 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
903 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
904 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
905 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
906 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
907
908 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
909 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
910 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
911 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
912 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
913 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
914 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
915 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
916 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
917 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
918 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
919 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
920
921 /*
922 * XMR_FS_ERR will be set if
923 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
924 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
925 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
926 * XMR_FS_ERR unless the corresponding bit in the Receive Command
927 * Register is set.
928 */
929 };
930
931 /*
932 ,* XMAC-PHY Registers, indirect addressed over the XMAC
933 */
934 enum {
935 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
936 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
937 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
938 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
939 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
940 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
941 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
942 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
943 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
944
945 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
946 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
947 };
948 /*
949 * Broadcom-PHY Registers, indirect addressed over XMAC
950 */
951 enum {
952 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
953 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
954 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
955 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
956 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
957 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
958 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
959 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
960 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
961 /* Broadcom-specific registers */
962 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
963 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
964 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
965 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
966 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
967 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
968 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
969 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
970
971 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
972 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
973 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
974 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
975 };
976
977 /*
978 * Marvel-PHY Registers, indirect addressed over GMAC
979 */
980 enum {
981 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
982 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
983 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
984 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
985 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
986 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
987 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
988 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
989 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
990 /* Marvel-specific registers */
991 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
992 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
993 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
994 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
995 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
996 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
997 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
998 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
999 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1000 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1001 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1002 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1003 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1004 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1005 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1006 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1007 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1008 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1009
1010 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1011 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1012 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1013 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1014 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1015 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1016 };
1017
1018 enum {
1019 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1020 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1021 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1022 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1023 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1024 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1025 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1026 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1027 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1028 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1029 };
1030
1031 enum {
1032 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1033 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1034 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1035 };
1036
1037 enum {
1038 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1039
1040 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1041 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1042 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
1043 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1044 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1045 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1046 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1047 };
1048
1049 enum {
1050 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1051 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1052 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1053 };
1054
1055 /* different Broadcom PHY Ids */
1056 enum {
1057 PHY_BCOM_ID1_A1 = 0x6041,
1058 PHY_BCOM_ID1_B2 = 0x6043,
1059 PHY_BCOM_ID1_C0 = 0x6044,
1060 PHY_BCOM_ID1_C5 = 0x6047,
1061 };
1062
1063 /* different Marvell PHY Ids */
1064 enum {
1065 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1066 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1067 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1068 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1069 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1070 };
1071
1072 /* Advertisement register bits */
1073 enum {
1074 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1075 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1076 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1077
1078 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1079 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1080 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1081 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1082 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1083 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1084 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1085 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1086 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1087 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1088 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1089 PHY_AN_100HALF | PHY_AN_100FULL,
1090 };
1091
1092 /* Xmac Specific */
1093 enum {
1094 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1095 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1096 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1097
1098 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1099 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1100 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1101 };
1102
1103 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1104 enum {
1105 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1106 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1107 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1108 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1109 };
1110
1111
1112 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1113 enum {
1114 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1115 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1116 };
1117
1118 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1119 enum {
1120 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1121 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1122 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1123 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1124 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1125 };
1126
1127 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1128 enum {
1129 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1130 X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1131 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1132 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1133 };
1134
1135 /* Broadcom-Specific */
1136 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1137 enum {
1138 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1139 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1140 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1141 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1142 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1143 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1144 };
1145
1146 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1147 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1148 enum {
1149 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1150 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1151 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1152 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1153 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1154 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1155 /* Bit 9..8: reserved */
1156 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1157 };
1158
1159 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1160 enum {
1161 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1162 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1163 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1164 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1165 };
1166
1167 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1168 enum {
1169 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1170 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1171 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1172 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1173 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1174 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1175 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1176 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1177 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1178 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1179 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1180 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1181 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1182 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1183 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1184 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1185 };
1186
1187 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1188 enum {
1189 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1190 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1191 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1192 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1193 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1194 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1195 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1196 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1197 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1198 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1199 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1200 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1201 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1202 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1203 };
1204
1205 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1206 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1207 enum {
1208 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1209
1210 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1211 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1212 };
1213
1214
1215 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1216 enum {
1217 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1218
1219 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1220 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1221 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1222
1223 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1224 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1225 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1226 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1227 /* Bit 11: reserved */
1228 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1229 /* Bit 9.. 8: reserved */
1230 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1231 /* Bit 6: reserved */
1232 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1233 /* Bit 4: reserved */
1234 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1235 };
1236
1237 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1238 enum {
1239 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1240 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1241 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1242 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1243 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1244 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1245 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1246 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1247 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1248 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1249 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1250 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1251 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1252 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1253 };
1254 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1255
1256 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1257 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1258 enum {
1259 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1260 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1261 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1262 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1263 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1264 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1265 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1266 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1267 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1268 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1269 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1270 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1271 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1272 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1273 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1274 };
1275 #define PHY_B_DEF_MSK \
1276 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1277 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1278
1279 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1280 enum {
1281 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1282 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1283 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1284 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1285 };
1286 /*
1287 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1288 */
1289 enum {
1290 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1291 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1292 };
1293
1294 /** Marvell-Specific */
1295 enum {
1296 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1297 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1298 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1299
1300 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1301 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1302 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1303 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1304 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1305 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1306 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1307 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1308 };
1309
1310 /* special defines for FIBER (88E1011S only) */
1311 enum {
1312 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1313 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1314 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1315 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1316 };
1317
1318 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1319 enum {
1320 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1321 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1322 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1323 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1324 };
1325
1326 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1327 enum {
1328 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1329 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1330 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1331 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1332 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1333 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1334 };
1335
1336 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1337 enum {
1338 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1339 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1340 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1341 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1342 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1343 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1344 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1345 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1346 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1347 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1348 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1349 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1350 };
1351
1352 enum {
1353 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1354 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1355 };
1356
1357 enum {
1358 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1359 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1360 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1361 };
1362
1363 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1364 enum {
1365 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1366 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1367 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1368 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1369 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1370
1371 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1372 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1373
1374 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1375 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1376 };
1377
1378 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1379 enum {
1380 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1381 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1382 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1383 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1384 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1385 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1386 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1387 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1388 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1389 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1390 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1391 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1392 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1393 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1394 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1395 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1396 };
1397
1398 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1399
1400 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1401 enum {
1402 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1403 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1404 };
1405
1406 enum {
1407 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1408 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1409 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1410 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1411 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1412 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1413 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1414 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1415 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1416 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1417 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1418 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1419
1420 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1421 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1422 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1423
1424 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1425 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1426
1427 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1428 };
1429
1430 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1431 enum {
1432 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1433 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1434
1435 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1436 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1437 /* (88E1011 only) */
1438 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1439 /* (88E1011 only) */
1440 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1441 /* (88E1111 only) */
1442 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1443 /* !!! Errata in spec. (1 = disable) */
1444 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1445 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1446 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1447 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1448 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1449 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1450
1451 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1452 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1453 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1454
1455 #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1456 /* 100=5x; 101=6x; 110=7x; 111=8x */
1457 enum {
1458 MAC_TX_CLK_0_MHZ = 2,
1459 MAC_TX_CLK_2_5_MHZ = 6,
1460 MAC_TX_CLK_25_MHZ = 7,
1461 };
1462
1463 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1464 enum {
1465 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1466 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1467 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1468 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1469 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1470 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1471 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1472 /* (88E1111 only) */
1473 };
1474 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1475 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1476
1477 enum {
1478 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1479 /* (88E1011 only) */
1480 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1481 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1482 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1483 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1484 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1485 };
1486
1487 enum {
1488 PULS_NO_STR = 0, /* no pulse stretching */
1489 PULS_21MS = 1, /* 21 ms to 42 ms */
1490 PULS_42MS = 2, /* 42 ms to 84 ms */
1491 PULS_84MS = 3, /* 84 ms to 170 ms */
1492 PULS_170MS = 4, /* 170 ms to 340 ms */
1493 PULS_340MS = 5, /* 340 ms to 670 ms */
1494 PULS_670MS = 6, /* 670 ms to 1.3 s */
1495 PULS_1300MS = 7, /* 1.3 s to 2.7 s */
1496 };
1497
1498
1499 enum {
1500 BLINK_42MS = 0, /* 42 ms */
1501 BLINK_84MS = 1, /* 84 ms */
1502 BLINK_170MS = 2, /* 170 ms */
1503 BLINK_340MS = 3, /* 340 ms */
1504 BLINK_670MS = 4, /* 670 ms */
1505 };
1506
1507 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1508 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1509 /* Bit 13..12: reserved */
1510 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1511 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1512 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1513 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1514 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1515 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1516
1517 enum {
1518 MO_LED_NORM = 0,
1519 MO_LED_BLINK = 1,
1520 MO_LED_OFF = 2,
1521 MO_LED_ON = 3,
1522 };
1523
1524 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1525 enum {
1526 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1527 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1528 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1529 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1530 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1531 };
1532
1533 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1534 enum {
1535 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1536 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1537 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1538 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1539 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1540 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1541 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1542 /* (88E1111 only) */
1543 /* Bit 9.. 4: reserved (88E1011 only) */
1544 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1545 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1546 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1547 };
1548
1549 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1550 enum {
1551 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1552 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1553 /* (88E1111 only) */
1554 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1555 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1556 /* (88E1111 only) */
1557 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1558 };
1559
1560 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1561 enum {
1562 CABD_STAT_NORMAL= 0,
1563 CABD_STAT_SHORT = 1,
1564 CABD_STAT_OPEN = 2,
1565 CABD_STAT_FAIL = 3,
1566 };
1567
1568 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1569 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1570 /* Bit 15..12: reserved (used internally) */
1571 enum {
1572 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1573 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1574 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1575 };
1576
1577 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1578 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1579 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1580
1581 enum {
1582 LED_PAR_CTRL_COLX = 0x00,
1583 LED_PAR_CTRL_ERROR = 0x01,
1584 LED_PAR_CTRL_DUPLEX = 0x02,
1585 LED_PAR_CTRL_DP_COL = 0x03,
1586 LED_PAR_CTRL_SPEED = 0x04,
1587 LED_PAR_CTRL_LINK = 0x05,
1588 LED_PAR_CTRL_TX = 0x06,
1589 LED_PAR_CTRL_RX = 0x07,
1590 LED_PAR_CTRL_ACT = 0x08,
1591 LED_PAR_CTRL_LNK_RX = 0x09,
1592 LED_PAR_CTRL_LNK_AC = 0x0a,
1593 LED_PAR_CTRL_ACT_BL = 0x0b,
1594 LED_PAR_CTRL_TX_BL = 0x0c,
1595 LED_PAR_CTRL_RX_BL = 0x0d,
1596 LED_PAR_CTRL_COL_BL = 0x0e,
1597 LED_PAR_CTRL_INACT = 0x0f
1598 };
1599
1600 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1601 enum {
1602 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1603 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1604 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1605 };
1606
1607
1608 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1609 enum {
1610 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1611 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1612 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1613 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1614 };
1615
1616 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1617 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1618 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1619 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1620
1621 /* GMAC registers */
1622 /* Port Registers */
1623 enum {
1624 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1625 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1626 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1627 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1628 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1629 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1630 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1631 /* Source Address Registers */
1632 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1633 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1634 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1635 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1636 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1637 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1638
1639 /* Multicast Address Hash Registers */
1640 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1641 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1642 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1643 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1644
1645 /* Interrupt Source Registers */
1646 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1647 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1648 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1649
1650 /* Interrupt Mask Registers */
1651 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1652 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1653 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1654
1655 /* Serial Management Interface (SMI) Registers */
1656 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1657 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1658 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1659 };
1660
1661 /* MIB Counters */
1662 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1663 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1664
1665 /*
1666 * MIB Counters base address definitions (low word) -
1667 * use offset 4 for access to high word (32 bit r/o)
1668 */
1669 enum {
1670 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1671 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1672 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1673 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1674 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1675 /* GM_MIB_CNT_BASE + 40: reserved */
1676 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1677 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1678 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1679 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1680 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1681 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1682 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1683 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1684 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1685 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1686 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1687 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1688 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1689 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1690 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1691 /* GM_MIB_CNT_BASE + 168: reserved */
1692 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1693 /* GM_MIB_CNT_BASE + 184: reserved */
1694 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1695 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1696 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1697 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1698 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1699 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1700 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1701 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1702 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1703 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1704 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1705 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1706 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1707
1708 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1709 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1710 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1711 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1712 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1713 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1714 };
1715
1716 /* GMAC Bit Definitions */
1717 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1718 enum {
1719 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1720 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1721 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1722 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1723 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1724 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1725 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
1726 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
1727
1728 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1729 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1730 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1731 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1732 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1733 };
1734
1735 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1736 enum {
1737 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1738 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1739 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1740 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1741 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1742 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1743 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1744 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1745 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1746 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1747 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1748 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1749 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1750 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1751 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1752 };
1753
1754 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1755 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1756
1757 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1758 enum {
1759 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1760 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1761 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1762 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1763 };
1764
1765 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1766 #define TX_COL_DEF 0x04 /* late collision after 64 byte */
1767
1768 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1769 enum {
1770 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1771 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1772 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1773 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1774 };
1775
1776 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1777 enum {
1778 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1779 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1780 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1781
1782 TX_JAM_LEN_DEF = 0x03,
1783 TX_JAM_IPG_DEF = 0x0b,
1784 TX_IPG_JAM_DEF = 0x1c,
1785 };
1786
1787 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1788 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1789 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1790
1791
1792 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1793 enum {
1794 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1795 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1796 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1797 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1798 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1799 };
1800
1801 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1802 #define DATA_BLIND_DEF 0x04
1803
1804 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1805 #define IPG_DATA_DEF 0x1e
1806
1807 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1808 enum {
1809 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1810 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1811 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1812 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1813 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1814 };
1815
1816 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1817 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1818
1819 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1820 enum {
1821 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1822 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1823 };
1824
1825 /* Receive Frame Status Encoding */
1826 enum {
1827 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1828 GMR_FS_LEN_SHIFT = 16,
1829 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1830 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1831 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1832 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1833 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1834 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1835 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1836 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1837 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1838 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1839 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1840
1841 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1842 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1843
1844 /*
1845 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1846 */
1847 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1848 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1849 GMR_FS_JABBER,
1850 /* Rx GMAC FIFO Flush Mask (default) */
1851 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1852 GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
1853 };
1854
1855 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1856 enum {
1857 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1858 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1859 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1860
1861 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1862 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1863 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1864 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1865 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1866 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1867 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1868 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1869 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1870 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1871 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1872
1873 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1874 };
1875
1876
1877 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1878 enum {
1879 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1880 GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1881 GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
1882
1883 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1884 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1885 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1886 };
1887
1888 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1889 enum {
1890 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1891 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1892 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1893 };
1894
1895 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1896 enum {
1897 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1898 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1899 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1900 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1901 GMC_PAUSE_ON = 1<<3, /* Pause On */
1902 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1903 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1904 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1905 };
1906
1907 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1908 enum {
1909 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1910 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1911 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1912 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1913 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1914 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1915 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1916 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1917 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1918 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1919 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1920 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1921 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1922 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1923 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1924 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1925 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1926 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1927 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1928 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1929 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1930 /* Bits 7..2: reserved */
1931 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1932 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1933 };
1934
1935 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1936 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1937 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1938
1939 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1940 #define GPC_FRC10MBIT_HALF 0
1941 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1942 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1943 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1944
1945 /* auto-negotiation with limited advertised speeds */
1946 /* mix only with master/slave settings (for copper) */
1947 #define GPC_ADV_1000_HALF GPC_ANEG_2
1948 #define GPC_ADV_1000_FULL GPC_ANEG_3
1949 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1950
1951 /* master/slave settings */
1952 /* only for copper with 1000 Mbps */
1953 #define GPC_FORCE_MASTER 0
1954 #define GPC_FORCE_SLAVE GPC_ANEG_0
1955 #define GPC_PREF_MASTER GPC_ANEG_1
1956 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
1957
1958 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1959 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1960 enum {
1961 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1962 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1963 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1964 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1965 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1966 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1967
1968 #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
1969
1970 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1971 /* Bits 15.. 2: reserved */
1972 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1973 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1974
1975
1976 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1977 WOL_CTL_LINK_CHG_OCC = 1<<15,
1978 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1979 WOL_CTL_PATTERN_OCC = 1<<13,
1980 WOL_CTL_CLEAR_RESULT = 1<<12,
1981 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1982 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1983 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1984 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1985 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1986 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1987 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1988 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1989 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1990 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1991 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1992 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1993 };
1994
1995 #define WOL_CTL_DEFAULT \
1996 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1997 WOL_CTL_DIS_PME_ON_PATTERN | \
1998 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1999 WOL_CTL_DIS_LINK_CHG_UNIT | \
2000 WOL_CTL_DIS_PATTERN_UNIT | \
2001 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2002
2003 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2004 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2005
2006
2007 /* XMAC II registers */
2008 enum {
2009 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2010 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2011 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2012 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2013 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2014 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2015 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2016 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2017 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2018 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2019 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2020 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2021 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2022 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2023 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2024 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2025 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2026 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2027 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2028 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2029 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2030 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2031 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2032 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2033 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2034
2035 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2036 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2037 };
2038
2039 enum {
2040 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2041 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2042 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2043 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2044 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2045 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2046 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2047 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2048 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2049 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2050 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2051 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2052 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2053 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2054 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2055 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2056 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2057 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2058 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2059 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2060 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2061 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2062 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2063 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2064 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2065 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2066 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2067 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2068 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2069 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2070 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2071 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2072 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2073 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2074 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2075 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2076 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2077 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2078 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2079 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2080 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2081 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2082 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2083 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2084 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2085 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2086 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2087 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2088 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2089 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2090 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2091 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2092 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2093 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2094 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2095 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2096 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2097 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2098 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2099 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2100 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2101 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2102 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2103 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2104 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2105 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2106 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2107 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2108 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2109 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2110 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2111 };
2112
2113 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2114 enum {
2115 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2116 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2117 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2118 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2119 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2120 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2121 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2122 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2123 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2124 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2125 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2126 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2127 };
2128
2129
2130 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2131 enum {
2132 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2133 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2134 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2135 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2136 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2137 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2138 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2139 };
2140
2141 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2142 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2143
2144
2145 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2146 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2147
2148
2149 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2150 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2151
2152
2153 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2154 enum {
2155 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2156 /* inrange error packets */
2157 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2158 /* jumbo packets */
2159 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2160 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2161 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2162 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2163 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2164 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2165 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2166 };
2167
2168
2169 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2170 enum {
2171 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2172 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2173 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2174 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2175 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2176 };
2177
2178
2179 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2180 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2181 enum {
2182 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2183 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2184 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2185 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2186 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2187 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2188 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2189 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2190 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2191 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2192 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2193 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2194 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2195 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2196 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2197
2198 XM_IMSK_DISABLE = 0xffff,
2199 };
2200
2201 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2202 enum {
2203 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2204 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2205 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2206 };
2207
2208
2209 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2210 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2211 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2212
2213 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2214 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2215 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2216 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2217
2218
2219 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2220 enum {
2221 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2222 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2223 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2224 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2225 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2226 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2227 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2228 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2229 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2230 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2231 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
2232 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2233 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2234 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2235 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2236 };
2237
2238 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2239 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2240 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2241
2242
2243 /* XM_DEV_ID 32 bit r/o Device ID Register */
2244 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2245 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2246
2247
2248 /* XM_MODE 32 bit r/w Mode Register */
2249 enum {
2250 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2251 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2252 /* extern generated */
2253 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2254 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2255 /* intern generated */
2256 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2257 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2258 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2259 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2260 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2261 /* intern generated */
2262 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2263 /* intern generated */
2264 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2265 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2266 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2267 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2268 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2269 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2270 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2271 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2272 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2273 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2274 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2275 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2276 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2277 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2278 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2279 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2280 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2281 };
2282
2283 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2284 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2285 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2286
2287 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2288 enum {
2289 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2290 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2291 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2292 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2293 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2294 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2295 };
2296
2297
2298 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2299 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2300 enum {
2301 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2302 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2303 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2304 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2305 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2306 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2307 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2308 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2309 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2310 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2311 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2312 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2313 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2314 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2315 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2316 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2317 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2318 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2319 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2320 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2321 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2322 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2323 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2324 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2325 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2326 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2327 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2328 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2329 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2330 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2331 };
2332
2333 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2334
2335 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2336 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2337 enum {
2338 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2339 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2340 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2341 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2342 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2343 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2344 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2345 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2346 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2347 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2348 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2349 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2350 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2351 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2352 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2353 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2354 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2355 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2356 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2357 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2358 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2359 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2360 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2361 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2362 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2363 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2364 };
2365
2366 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2367
2368 struct skge_rx_desc {
2369 u32 control;
2370 u32 next_offset;
2371 u32 dma_lo;
2372 u32 dma_hi;
2373 u32 status;
2374 u32 timestamp;
2375 u16 csum2;
2376 u16 csum1;
2377 u16 csum2_start;
2378 u16 csum1_start;
2379 };
2380
2381 struct skge_tx_desc {
2382 u32 control;
2383 u32 next_offset;
2384 u32 dma_lo;
2385 u32 dma_hi;
2386 u32 status;
2387 u32 csum_offs;
2388 u16 csum_write;
2389 u16 csum_start;
2390 u32 rsvd;
2391 };
2392
2393 struct skge_element {
2394 struct skge_element *next;
2395 void *desc;
2396 struct sk_buff *skb;
2397 DEFINE_DMA_UNMAP_ADDR(mapaddr);
2398 DEFINE_DMA_UNMAP_LEN(maplen);
2399 };
2400
2401 struct skge_ring {
2402 struct skge_element *to_clean;
2403 struct skge_element *to_use;
2404 struct skge_element *start;
2405 unsigned long count;
2406 };
2407
2408
2409 struct skge_hw {
2410 void __iomem *regs;
2411 struct pci_dev *pdev;
2412 spinlock_t hw_lock;
2413 u32 intr_mask;
2414 struct net_device *dev[2];
2415
2416 u8 chip_id;
2417 u8 chip_rev;
2418 u8 copper;
2419 u8 ports;
2420 u8 phy_type;
2421
2422 u32 ram_size;
2423 u32 ram_offset;
2424 u16 phy_addr;
2425 spinlock_t phy_lock;
2426 struct tasklet_struct phy_task;
2427
2428 char irq_name[0]; /* skge@pci:000:04:00.0 */
2429 };
2430
2431 enum pause_control {
2432 FLOW_MODE_NONE = 1, /* No Flow-Control */
2433 FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
2434 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2435 FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
2436 * just the remote station may send PAUSE
2437 */
2438 };
2439
2440 enum pause_status {
2441 FLOW_STAT_INDETERMINATED=0, /* indeterminated */
2442 FLOW_STAT_NONE, /* No Flow Control */
2443 FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
2444 FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
2445 FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
2446 };
2447
2448
2449 struct skge_port {
2450 struct skge_hw *hw;
2451 struct net_device *netdev;
2452 struct napi_struct napi;
2453 int port;
2454 u32 msg_enable;
2455
2456 struct skge_ring tx_ring;
2457
2458 struct skge_ring rx_ring ____cacheline_aligned_in_smp;
2459 unsigned int rx_buf_size;
2460
2461 struct timer_list link_timer;
2462 enum pause_control flow_control;
2463 enum pause_status flow_status;
2464 u8 blink_on;
2465 u8 wol;
2466 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2467 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2468 u16 speed; /* SPEED_1000, SPEED_100, ... */
2469 u32 advertising;
2470
2471 void *mem; /* PCI memory for rings */
2472 dma_addr_t dma;
2473 unsigned long mem_size;
2474 #ifdef CONFIG_SKGE_DEBUG
2475 struct dentry *debugfs;
2476 #endif
2477 };
2478
2479
2480 /* Register accessor for memory mapped device */
2481 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2482 {
2483 return readl(hw->regs + reg);
2484 }
2485
2486 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2487 {
2488 return readw(hw->regs + reg);
2489 }
2490
2491 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2492 {
2493 return readb(hw->regs + reg);
2494 }
2495
2496 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2497 {
2498 writel(val, hw->regs + reg);
2499 }
2500
2501 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2502 {
2503 writew(val, hw->regs + reg);
2504 }
2505
2506 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2507 {
2508 writeb(val, hw->regs + reg);
2509 }
2510
2511 /* MAC Related Registers inside the device. */
2512 #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2513 #define SK_XMAC_REG(port, reg) \
2514 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2515
2516 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2517 {
2518 u32 v;
2519 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2520 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2521 return v;
2522 }
2523
2524 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2525 {
2526 return skge_read16(hw, SK_XMAC_REG(port,reg));
2527 }
2528
2529 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2530 {
2531 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2532 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2533 }
2534
2535 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2536 {
2537 skge_write16(hw, SK_XMAC_REG(port,r), v);
2538 }
2539
2540 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2541 const u8 *hash)
2542 {
2543 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2544 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2545 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2546 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2547 }
2548
2549 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2550 const u8 *addr)
2551 {
2552 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2553 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2554 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2555 }
2556
2557 #define SK_GMAC_REG(port,reg) \
2558 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2559
2560 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2561 {
2562 return skge_read16(hw, SK_GMAC_REG(port,reg));
2563 }
2564
2565 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2566 {
2567 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2568 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2569 }
2570
2571 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2572 {
2573 skge_write16(hw, SK_GMAC_REG(port,r), v);
2574 }
2575
2576 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2577 const u8 *addr)
2578 {
2579 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2580 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2581 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2582 }
2583
2584 #endif
Linux with added FPC-III support