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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
blob93949139e62cf92a7e593b36d6a7399edbd1b6e6
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25
26 #include "mtk_eth_soc.h"
27
28 static int mtk_msg_level = -1;
29 module_param_named(msg_level, mtk_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32 #define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
34
35 /* strings used by ethtool */
36 static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
38 u32 offset;
39 } mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
52 };
53
54 static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2", "trgpll"
56 };
57
58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59 {
60 __raw_writel(val, eth->base + reg);
61 }
62
63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64 {
65 return __raw_readl(eth->base + reg);
66 }
67
68 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
69 {
70 unsigned long t_start = jiffies;
71
72 while (1) {
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
74 return 0;
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
76 break;
77 usleep_range(10, 20);
78 }
79
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
81 return -1;
82 }
83
84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
86 {
87 if (mtk_mdio_busy_wait(eth))
88 return -1;
89
90 write_data &= 0xffff;
91
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
95 MTK_PHY_IAC);
96
97 if (mtk_mdio_busy_wait(eth))
98 return -1;
99
100 return 0;
101 }
102
103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
104 {
105 u32 d;
106
107 if (mtk_mdio_busy_wait(eth))
108 return 0xffff;
109
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
113 MTK_PHY_IAC);
114
115 if (mtk_mdio_busy_wait(eth))
116 return 0xffff;
117
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
119
120 return d;
121 }
122
123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
125 {
126 struct mtk_eth *eth = bus->priv;
127
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
129 }
130
131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
132 {
133 struct mtk_eth *eth = bus->priv;
134
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
136 }
137
138 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
139 {
140 u32 val;
141 int ret;
142
143 val = (speed == SPEED_1000) ?
144 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
145 mtk_w32(eth, val, INTF_MODE);
146
147 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
148 ETHSYS_TRGMII_CLK_SEL362_5,
149 ETHSYS_TRGMII_CLK_SEL362_5);
150
151 val = (speed == SPEED_1000) ? 250000000 : 500000000;
152 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
153 if (ret)
154 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
155
156 val = (speed == SPEED_1000) ?
157 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
158 mtk_w32(eth, val, TRGMII_RCK_CTRL);
159
160 val = (speed == SPEED_1000) ?
161 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
162 mtk_w32(eth, val, TRGMII_TCK_CTRL);
163 }
164
165 static void mtk_phy_link_adjust(struct net_device *dev)
166 {
167 struct mtk_mac *mac = netdev_priv(dev);
168 u16 lcl_adv = 0, rmt_adv = 0;
169 u8 flowctrl;
170 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
171 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
172 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
173 MAC_MCR_BACKPR_EN;
174
175 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
176 return;
177
178 switch (dev->phydev->speed) {
179 case SPEED_1000:
180 mcr |= MAC_MCR_SPEED_1000;
181 break;
182 case SPEED_100:
183 mcr |= MAC_MCR_SPEED_100;
184 break;
185 };
186
187 if (mac->id == 0 && !mac->trgmii)
188 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
189
190 if (dev->phydev->link)
191 mcr |= MAC_MCR_FORCE_LINK;
192
193 if (dev->phydev->duplex) {
194 mcr |= MAC_MCR_FORCE_DPX;
195
196 if (dev->phydev->pause)
197 rmt_adv = LPA_PAUSE_CAP;
198 if (dev->phydev->asym_pause)
199 rmt_adv |= LPA_PAUSE_ASYM;
200
201 if (dev->phydev->advertising & ADVERTISED_Pause)
202 lcl_adv |= ADVERTISE_PAUSE_CAP;
203 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
204 lcl_adv |= ADVERTISE_PAUSE_ASYM;
205
206 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
207
208 if (flowctrl & FLOW_CTRL_TX)
209 mcr |= MAC_MCR_FORCE_TX_FC;
210 if (flowctrl & FLOW_CTRL_RX)
211 mcr |= MAC_MCR_FORCE_RX_FC;
212
213 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
214 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
215 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
216 }
217
218 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
219
220 if (dev->phydev->link)
221 netif_carrier_on(dev);
222 else
223 netif_carrier_off(dev);
224 }
225
226 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
227 struct device_node *phy_node)
228 {
229 struct phy_device *phydev;
230 int phy_mode;
231
232 phy_mode = of_get_phy_mode(phy_node);
233 if (phy_mode < 0) {
234 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
235 return -EINVAL;
236 }
237
238 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
239 mtk_phy_link_adjust, 0, phy_mode);
240 if (!phydev) {
241 dev_err(eth->dev, "could not connect to PHY\n");
242 return -ENODEV;
243 }
244
245 dev_info(eth->dev,
246 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
247 mac->id, phydev_name(phydev), phydev->phy_id,
248 phydev->drv->name);
249
250 return 0;
251 }
252
253 static int mtk_phy_connect(struct net_device *dev)
254 {
255 struct mtk_mac *mac = netdev_priv(dev);
256 struct mtk_eth *eth;
257 struct device_node *np;
258 u32 val;
259
260 eth = mac->hw;
261 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
262 if (!np && of_phy_is_fixed_link(mac->of_node))
263 if (!of_phy_register_fixed_link(mac->of_node))
264 np = of_node_get(mac->of_node);
265 if (!np)
266 return -ENODEV;
267
268 switch (of_get_phy_mode(np)) {
269 case PHY_INTERFACE_MODE_TRGMII:
270 mac->trgmii = true;
271 case PHY_INTERFACE_MODE_RGMII_TXID:
272 case PHY_INTERFACE_MODE_RGMII_RXID:
273 case PHY_INTERFACE_MODE_RGMII_ID:
274 case PHY_INTERFACE_MODE_RGMII:
275 mac->ge_mode = 0;
276 break;
277 case PHY_INTERFACE_MODE_MII:
278 mac->ge_mode = 1;
279 break;
280 case PHY_INTERFACE_MODE_REVMII:
281 mac->ge_mode = 2;
282 break;
283 case PHY_INTERFACE_MODE_RMII:
284 if (!mac->id)
285 goto err_phy;
286 mac->ge_mode = 3;
287 break;
288 default:
289 goto err_phy;
290 }
291
292 /* put the gmac into the right mode */
293 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
294 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
295 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
296 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
297
298 /* couple phydev to net_device */
299 if (mtk_phy_connect_node(eth, mac, np))
300 goto err_phy;
301
302 dev->phydev->autoneg = AUTONEG_ENABLE;
303 dev->phydev->speed = 0;
304 dev->phydev->duplex = 0;
305
306 if (of_phy_is_fixed_link(mac->of_node))
307 dev->phydev->supported |=
308 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
309
310 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
311 SUPPORTED_Asym_Pause;
312 dev->phydev->advertising = dev->phydev->supported |
313 ADVERTISED_Autoneg;
314 phy_start_aneg(dev->phydev);
315
316 of_node_put(np);
317
318 return 0;
319
320 err_phy:
321 if (of_phy_is_fixed_link(mac->of_node))
322 of_phy_deregister_fixed_link(mac->of_node);
323 of_node_put(np);
324 dev_err(eth->dev, "%s: invalid phy\n", __func__);
325 return -EINVAL;
326 }
327
328 static int mtk_mdio_init(struct mtk_eth *eth)
329 {
330 struct device_node *mii_np;
331 int ret;
332
333 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
334 if (!mii_np) {
335 dev_err(eth->dev, "no %s child node found", "mdio-bus");
336 return -ENODEV;
337 }
338
339 if (!of_device_is_available(mii_np)) {
340 ret = -ENODEV;
341 goto err_put_node;
342 }
343
344 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
345 if (!eth->mii_bus) {
346 ret = -ENOMEM;
347 goto err_put_node;
348 }
349
350 eth->mii_bus->name = "mdio";
351 eth->mii_bus->read = mtk_mdio_read;
352 eth->mii_bus->write = mtk_mdio_write;
353 eth->mii_bus->priv = eth;
354 eth->mii_bus->parent = eth->dev;
355
356 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
357 ret = of_mdiobus_register(eth->mii_bus, mii_np);
358
359 err_put_node:
360 of_node_put(mii_np);
361 return ret;
362 }
363
364 static void mtk_mdio_cleanup(struct mtk_eth *eth)
365 {
366 if (!eth->mii_bus)
367 return;
368
369 mdiobus_unregister(eth->mii_bus);
370 }
371
372 static inline void mtk_irq_disable(struct mtk_eth *eth,
373 unsigned reg, u32 mask)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&eth->irq_lock, flags);
379 val = mtk_r32(eth, reg);
380 mtk_w32(eth, val & ~mask, reg);
381 spin_unlock_irqrestore(&eth->irq_lock, flags);
382 }
383
384 static inline void mtk_irq_enable(struct mtk_eth *eth,
385 unsigned reg, u32 mask)
386 {
387 unsigned long flags;
388 u32 val;
389
390 spin_lock_irqsave(&eth->irq_lock, flags);
391 val = mtk_r32(eth, reg);
392 mtk_w32(eth, val | mask, reg);
393 spin_unlock_irqrestore(&eth->irq_lock, flags);
394 }
395
396 static int mtk_set_mac_address(struct net_device *dev, void *p)
397 {
398 int ret = eth_mac_addr(dev, p);
399 struct mtk_mac *mac = netdev_priv(dev);
400 const char *macaddr = dev->dev_addr;
401
402 if (ret)
403 return ret;
404
405 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
406 return -EBUSY;
407
408 spin_lock_bh(&mac->hw->page_lock);
409 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
410 MTK_GDMA_MAC_ADRH(mac->id));
411 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
412 (macaddr[4] << 8) | macaddr[5],
413 MTK_GDMA_MAC_ADRL(mac->id));
414 spin_unlock_bh(&mac->hw->page_lock);
415
416 return 0;
417 }
418
419 void mtk_stats_update_mac(struct mtk_mac *mac)
420 {
421 struct mtk_hw_stats *hw_stats = mac->hw_stats;
422 unsigned int base = MTK_GDM1_TX_GBCNT;
423 u64 stats;
424
425 base += hw_stats->reg_offset;
426
427 u64_stats_update_begin(&hw_stats->syncp);
428
429 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
430 stats = mtk_r32(mac->hw, base + 0x04);
431 if (stats)
432 hw_stats->rx_bytes += (stats << 32);
433 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
434 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
435 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
436 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
437 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
438 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
439 hw_stats->rx_flow_control_packets +=
440 mtk_r32(mac->hw, base + 0x24);
441 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
442 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
443 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
444 stats = mtk_r32(mac->hw, base + 0x34);
445 if (stats)
446 hw_stats->tx_bytes += (stats << 32);
447 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
448 u64_stats_update_end(&hw_stats->syncp);
449 }
450
451 static void mtk_stats_update(struct mtk_eth *eth)
452 {
453 int i;
454
455 for (i = 0; i < MTK_MAC_COUNT; i++) {
456 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
457 continue;
458 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
459 mtk_stats_update_mac(eth->mac[i]);
460 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
461 }
462 }
463 }
464
465 static void mtk_get_stats64(struct net_device *dev,
466 struct rtnl_link_stats64 *storage)
467 {
468 struct mtk_mac *mac = netdev_priv(dev);
469 struct mtk_hw_stats *hw_stats = mac->hw_stats;
470 unsigned int start;
471
472 if (netif_running(dev) && netif_device_present(dev)) {
473 if (spin_trylock(&hw_stats->stats_lock)) {
474 mtk_stats_update_mac(mac);
475 spin_unlock(&hw_stats->stats_lock);
476 }
477 }
478
479 do {
480 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
481 storage->rx_packets = hw_stats->rx_packets;
482 storage->tx_packets = hw_stats->tx_packets;
483 storage->rx_bytes = hw_stats->rx_bytes;
484 storage->tx_bytes = hw_stats->tx_bytes;
485 storage->collisions = hw_stats->tx_collisions;
486 storage->rx_length_errors = hw_stats->rx_short_errors +
487 hw_stats->rx_long_errors;
488 storage->rx_over_errors = hw_stats->rx_overflow;
489 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
490 storage->rx_errors = hw_stats->rx_checksum_errors;
491 storage->tx_aborted_errors = hw_stats->tx_skip;
492 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
493
494 storage->tx_errors = dev->stats.tx_errors;
495 storage->rx_dropped = dev->stats.rx_dropped;
496 storage->tx_dropped = dev->stats.tx_dropped;
497 }
498
499 static inline int mtk_max_frag_size(int mtu)
500 {
501 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
502 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
503 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
504
505 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
506 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
507 }
508
509 static inline int mtk_max_buf_size(int frag_size)
510 {
511 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
512 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
513
514 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
515
516 return buf_size;
517 }
518
519 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
520 struct mtk_rx_dma *dma_rxd)
521 {
522 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
523 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
524 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
525 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
526 }
527
528 /* the qdma core needs scratch memory to be setup */
529 static int mtk_init_fq_dma(struct mtk_eth *eth)
530 {
531 dma_addr_t phy_ring_tail;
532 int cnt = MTK_DMA_SIZE;
533 dma_addr_t dma_addr;
534 int i;
535
536 eth->scratch_ring = dma_alloc_coherent(eth->dev,
537 cnt * sizeof(struct mtk_tx_dma),
538 &eth->phy_scratch_ring,
539 GFP_ATOMIC | __GFP_ZERO);
540 if (unlikely(!eth->scratch_ring))
541 return -ENOMEM;
542
543 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
544 GFP_KERNEL);
545 if (unlikely(!eth->scratch_head))
546 return -ENOMEM;
547
548 dma_addr = dma_map_single(eth->dev,
549 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
550 DMA_FROM_DEVICE);
551 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
552 return -ENOMEM;
553
554 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
555 phy_ring_tail = eth->phy_scratch_ring +
556 (sizeof(struct mtk_tx_dma) * (cnt - 1));
557
558 for (i = 0; i < cnt; i++) {
559 eth->scratch_ring[i].txd1 =
560 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
561 if (i < cnt - 1)
562 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
563 ((i + 1) * sizeof(struct mtk_tx_dma)));
564 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
565 }
566
567 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
568 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
569 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
570 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
571
572 return 0;
573 }
574
575 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
576 {
577 void *ret = ring->dma;
578
579 return ret + (desc - ring->phys);
580 }
581
582 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
583 struct mtk_tx_dma *txd)
584 {
585 int idx = txd - ring->dma;
586
587 return &ring->buf[idx];
588 }
589
590 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
591 {
592 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
593 dma_unmap_single(eth->dev,
594 dma_unmap_addr(tx_buf, dma_addr0),
595 dma_unmap_len(tx_buf, dma_len0),
596 DMA_TO_DEVICE);
597 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
598 dma_unmap_page(eth->dev,
599 dma_unmap_addr(tx_buf, dma_addr0),
600 dma_unmap_len(tx_buf, dma_len0),
601 DMA_TO_DEVICE);
602 }
603 tx_buf->flags = 0;
604 if (tx_buf->skb &&
605 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
606 dev_kfree_skb_any(tx_buf->skb);
607 tx_buf->skb = NULL;
608 }
609
610 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
611 int tx_num, struct mtk_tx_ring *ring, bool gso)
612 {
613 struct mtk_mac *mac = netdev_priv(dev);
614 struct mtk_eth *eth = mac->hw;
615 struct mtk_tx_dma *itxd, *txd;
616 struct mtk_tx_buf *itx_buf, *tx_buf;
617 dma_addr_t mapped_addr;
618 unsigned int nr_frags;
619 int i, n_desc = 1;
620 u32 txd4 = 0, fport;
621
622 itxd = ring->next_free;
623 if (itxd == ring->last_free)
624 return -ENOMEM;
625
626 /* set the forward port */
627 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
628 txd4 |= fport;
629
630 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
631 memset(itx_buf, 0, sizeof(*itx_buf));
632
633 if (gso)
634 txd4 |= TX_DMA_TSO;
635
636 /* TX Checksum offload */
637 if (skb->ip_summed == CHECKSUM_PARTIAL)
638 txd4 |= TX_DMA_CHKSUM;
639
640 /* VLAN header offload */
641 if (skb_vlan_tag_present(skb))
642 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
643
644 mapped_addr = dma_map_single(eth->dev, skb->data,
645 skb_headlen(skb), DMA_TO_DEVICE);
646 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
647 return -ENOMEM;
648
649 WRITE_ONCE(itxd->txd1, mapped_addr);
650 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
651 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
652 MTK_TX_FLAGS_FPORT1;
653 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
654 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
655
656 /* TX SG offload */
657 txd = itxd;
658 nr_frags = skb_shinfo(skb)->nr_frags;
659 for (i = 0; i < nr_frags; i++) {
660 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
661 unsigned int offset = 0;
662 int frag_size = skb_frag_size(frag);
663
664 while (frag_size) {
665 bool last_frag = false;
666 unsigned int frag_map_size;
667
668 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
669 if (txd == ring->last_free)
670 goto err_dma;
671
672 n_desc++;
673 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
674 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
675 frag_map_size,
676 DMA_TO_DEVICE);
677 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
678 goto err_dma;
679
680 if (i == nr_frags - 1 &&
681 (frag_size - frag_map_size) == 0)
682 last_frag = true;
683
684 WRITE_ONCE(txd->txd1, mapped_addr);
685 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
686 TX_DMA_PLEN0(frag_map_size) |
687 last_frag * TX_DMA_LS0));
688 WRITE_ONCE(txd->txd4, fport);
689
690 tx_buf = mtk_desc_to_tx_buf(ring, txd);
691 memset(tx_buf, 0, sizeof(*tx_buf));
692 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
693 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
694 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
695 MTK_TX_FLAGS_FPORT1;
696
697 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
698 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
699 frag_size -= frag_map_size;
700 offset += frag_map_size;
701 }
702 }
703
704 /* store skb to cleanup */
705 itx_buf->skb = skb;
706
707 WRITE_ONCE(itxd->txd4, txd4);
708 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
709 (!nr_frags * TX_DMA_LS0)));
710
711 netdev_sent_queue(dev, skb->len);
712 skb_tx_timestamp(skb);
713
714 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
715 atomic_sub(n_desc, &ring->free_count);
716
717 /* make sure that all changes to the dma ring are flushed before we
718 * continue
719 */
720 wmb();
721
722 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
723 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
724
725 return 0;
726
727 err_dma:
728 do {
729 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
730
731 /* unmap dma */
732 mtk_tx_unmap(eth, tx_buf);
733
734 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
735 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
736 } while (itxd != txd);
737
738 return -ENOMEM;
739 }
740
741 static inline int mtk_cal_txd_req(struct sk_buff *skb)
742 {
743 int i, nfrags;
744 struct skb_frag_struct *frag;
745
746 nfrags = 1;
747 if (skb_is_gso(skb)) {
748 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
749 frag = &skb_shinfo(skb)->frags[i];
750 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
751 }
752 } else {
753 nfrags += skb_shinfo(skb)->nr_frags;
754 }
755
756 return nfrags;
757 }
758
759 static int mtk_queue_stopped(struct mtk_eth *eth)
760 {
761 int i;
762
763 for (i = 0; i < MTK_MAC_COUNT; i++) {
764 if (!eth->netdev[i])
765 continue;
766 if (netif_queue_stopped(eth->netdev[i]))
767 return 1;
768 }
769
770 return 0;
771 }
772
773 static void mtk_wake_queue(struct mtk_eth *eth)
774 {
775 int i;
776
777 for (i = 0; i < MTK_MAC_COUNT; i++) {
778 if (!eth->netdev[i])
779 continue;
780 netif_wake_queue(eth->netdev[i]);
781 }
782 }
783
784 static void mtk_stop_queue(struct mtk_eth *eth)
785 {
786 int i;
787
788 for (i = 0; i < MTK_MAC_COUNT; i++) {
789 if (!eth->netdev[i])
790 continue;
791 netif_stop_queue(eth->netdev[i]);
792 }
793 }
794
795 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
796 {
797 struct mtk_mac *mac = netdev_priv(dev);
798 struct mtk_eth *eth = mac->hw;
799 struct mtk_tx_ring *ring = &eth->tx_ring;
800 struct net_device_stats *stats = &dev->stats;
801 bool gso = false;
802 int tx_num;
803
804 /* normally we can rely on the stack not calling this more than once,
805 * however we have 2 queues running on the same ring so we need to lock
806 * the ring access
807 */
808 spin_lock(&eth->page_lock);
809
810 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
811 goto drop;
812
813 tx_num = mtk_cal_txd_req(skb);
814 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
815 mtk_stop_queue(eth);
816 netif_err(eth, tx_queued, dev,
817 "Tx Ring full when queue awake!\n");
818 spin_unlock(&eth->page_lock);
819 return NETDEV_TX_BUSY;
820 }
821
822 /* TSO: fill MSS info in tcp checksum field */
823 if (skb_is_gso(skb)) {
824 if (skb_cow_head(skb, 0)) {
825 netif_warn(eth, tx_err, dev,
826 "GSO expand head fail.\n");
827 goto drop;
828 }
829
830 if (skb_shinfo(skb)->gso_type &
831 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
832 gso = true;
833 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
834 }
835 }
836
837 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
838 goto drop;
839
840 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
841 mtk_stop_queue(eth);
842
843 spin_unlock(&eth->page_lock);
844
845 return NETDEV_TX_OK;
846
847 drop:
848 spin_unlock(&eth->page_lock);
849 stats->tx_dropped++;
850 dev_kfree_skb_any(skb);
851 return NETDEV_TX_OK;
852 }
853
854 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
855 {
856 int i;
857 struct mtk_rx_ring *ring;
858 int idx;
859
860 if (!eth->hwlro)
861 return &eth->rx_ring[0];
862
863 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
864 ring = &eth->rx_ring[i];
865 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
866 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
867 ring->calc_idx_update = true;
868 return ring;
869 }
870 }
871
872 return NULL;
873 }
874
875 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
876 {
877 struct mtk_rx_ring *ring;
878 int i;
879
880 if (!eth->hwlro) {
881 ring = &eth->rx_ring[0];
882 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
883 } else {
884 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
885 ring = &eth->rx_ring[i];
886 if (ring->calc_idx_update) {
887 ring->calc_idx_update = false;
888 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
889 }
890 }
891 }
892 }
893
894 static int mtk_poll_rx(struct napi_struct *napi, int budget,
895 struct mtk_eth *eth)
896 {
897 struct mtk_rx_ring *ring;
898 int idx;
899 struct sk_buff *skb;
900 u8 *data, *new_data;
901 struct mtk_rx_dma *rxd, trxd;
902 int done = 0;
903
904 while (done < budget) {
905 struct net_device *netdev;
906 unsigned int pktlen;
907 dma_addr_t dma_addr;
908 int mac = 0;
909
910 ring = mtk_get_rx_ring(eth);
911 if (unlikely(!ring))
912 goto rx_done;
913
914 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
915 rxd = &ring->dma[idx];
916 data = ring->data[idx];
917
918 mtk_rx_get_desc(&trxd, rxd);
919 if (!(trxd.rxd2 & RX_DMA_DONE))
920 break;
921
922 /* find out which mac the packet come from. values start at 1 */
923 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
924 RX_DMA_FPORT_MASK;
925 mac--;
926
927 netdev = eth->netdev[mac];
928
929 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
930 goto release_desc;
931
932 /* alloc new buffer */
933 new_data = napi_alloc_frag(ring->frag_size);
934 if (unlikely(!new_data)) {
935 netdev->stats.rx_dropped++;
936 goto release_desc;
937 }
938 dma_addr = dma_map_single(eth->dev,
939 new_data + NET_SKB_PAD,
940 ring->buf_size,
941 DMA_FROM_DEVICE);
942 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
943 skb_free_frag(new_data);
944 netdev->stats.rx_dropped++;
945 goto release_desc;
946 }
947
948 /* receive data */
949 skb = build_skb(data, ring->frag_size);
950 if (unlikely(!skb)) {
951 skb_free_frag(new_data);
952 netdev->stats.rx_dropped++;
953 goto release_desc;
954 }
955 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
956
957 dma_unmap_single(eth->dev, trxd.rxd1,
958 ring->buf_size, DMA_FROM_DEVICE);
959 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
960 skb->dev = netdev;
961 skb_put(skb, pktlen);
962 if (trxd.rxd4 & RX_DMA_L4_VALID)
963 skb->ip_summed = CHECKSUM_UNNECESSARY;
964 else
965 skb_checksum_none_assert(skb);
966 skb->protocol = eth_type_trans(skb, netdev);
967
968 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
969 RX_DMA_VID(trxd.rxd3))
970 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
971 RX_DMA_VID(trxd.rxd3));
972 napi_gro_receive(napi, skb);
973
974 ring->data[idx] = new_data;
975 rxd->rxd1 = (unsigned int)dma_addr;
976
977 release_desc:
978 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
979
980 ring->calc_idx = idx;
981
982 done++;
983 }
984
985 rx_done:
986 if (done) {
987 /* make sure that all changes to the dma ring are flushed before
988 * we continue
989 */
990 wmb();
991 mtk_update_rx_cpu_idx(eth);
992 }
993
994 return done;
995 }
996
997 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
998 {
999 struct mtk_tx_ring *ring = &eth->tx_ring;
1000 struct mtk_tx_dma *desc;
1001 struct sk_buff *skb;
1002 struct mtk_tx_buf *tx_buf;
1003 unsigned int done[MTK_MAX_DEVS];
1004 unsigned int bytes[MTK_MAX_DEVS];
1005 u32 cpu, dma;
1006 static int condition;
1007 int total = 0, i;
1008
1009 memset(done, 0, sizeof(done));
1010 memset(bytes, 0, sizeof(bytes));
1011
1012 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1013 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1014
1015 desc = mtk_qdma_phys_to_virt(ring, cpu);
1016
1017 while ((cpu != dma) && budget) {
1018 u32 next_cpu = desc->txd2;
1019 int mac = 0;
1020
1021 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1022 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1023 break;
1024
1025 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1026 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1027 mac = 1;
1028
1029 skb = tx_buf->skb;
1030 if (!skb) {
1031 condition = 1;
1032 break;
1033 }
1034
1035 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1036 bytes[mac] += skb->len;
1037 done[mac]++;
1038 budget--;
1039 }
1040 mtk_tx_unmap(eth, tx_buf);
1041
1042 ring->last_free = desc;
1043 atomic_inc(&ring->free_count);
1044
1045 cpu = next_cpu;
1046 }
1047
1048 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1049
1050 for (i = 0; i < MTK_MAC_COUNT; i++) {
1051 if (!eth->netdev[i] || !done[i])
1052 continue;
1053 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1054 total += done[i];
1055 }
1056
1057 if (mtk_queue_stopped(eth) &&
1058 (atomic_read(&ring->free_count) > ring->thresh))
1059 mtk_wake_queue(eth);
1060
1061 return total;
1062 }
1063
1064 static void mtk_handle_status_irq(struct mtk_eth *eth)
1065 {
1066 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1067
1068 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1069 mtk_stats_update(eth);
1070 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1071 MTK_INT_STATUS2);
1072 }
1073 }
1074
1075 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1076 {
1077 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1078 u32 status, mask;
1079 int tx_done = 0;
1080
1081 mtk_handle_status_irq(eth);
1082 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1083 tx_done = mtk_poll_tx(eth, budget);
1084
1085 if (unlikely(netif_msg_intr(eth))) {
1086 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1087 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1088 dev_info(eth->dev,
1089 "done tx %d, intr 0x%08x/0x%x\n",
1090 tx_done, status, mask);
1091 }
1092
1093 if (tx_done == budget)
1094 return budget;
1095
1096 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1097 if (status & MTK_TX_DONE_INT)
1098 return budget;
1099
1100 napi_complete(napi);
1101 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1102
1103 return tx_done;
1104 }
1105
1106 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1107 {
1108 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1109 u32 status, mask;
1110 int rx_done = 0;
1111 int remain_budget = budget;
1112
1113 mtk_handle_status_irq(eth);
1114
1115 poll_again:
1116 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1117 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1118
1119 if (unlikely(netif_msg_intr(eth))) {
1120 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1121 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1122 dev_info(eth->dev,
1123 "done rx %d, intr 0x%08x/0x%x\n",
1124 rx_done, status, mask);
1125 }
1126 if (rx_done == remain_budget)
1127 return budget;
1128
1129 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1130 if (status & MTK_RX_DONE_INT) {
1131 remain_budget -= rx_done;
1132 goto poll_again;
1133 }
1134 napi_complete(napi);
1135 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1136
1137 return rx_done + budget - remain_budget;
1138 }
1139
1140 static int mtk_tx_alloc(struct mtk_eth *eth)
1141 {
1142 struct mtk_tx_ring *ring = &eth->tx_ring;
1143 int i, sz = sizeof(*ring->dma);
1144
1145 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1146 GFP_KERNEL);
1147 if (!ring->buf)
1148 goto no_tx_mem;
1149
1150 ring->dma = dma_alloc_coherent(eth->dev,
1151 MTK_DMA_SIZE * sz,
1152 &ring->phys,
1153 GFP_ATOMIC | __GFP_ZERO);
1154 if (!ring->dma)
1155 goto no_tx_mem;
1156
1157 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1158 for (i = 0; i < MTK_DMA_SIZE; i++) {
1159 int next = (i + 1) % MTK_DMA_SIZE;
1160 u32 next_ptr = ring->phys + next * sz;
1161
1162 ring->dma[i].txd2 = next_ptr;
1163 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1164 }
1165
1166 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1167 ring->next_free = &ring->dma[0];
1168 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1169 ring->thresh = MAX_SKB_FRAGS;
1170
1171 /* make sure that all changes to the dma ring are flushed before we
1172 * continue
1173 */
1174 wmb();
1175
1176 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1177 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1178 mtk_w32(eth,
1179 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1180 MTK_QTX_CRX_PTR);
1181 mtk_w32(eth,
1182 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1183 MTK_QTX_DRX_PTR);
1184 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1185
1186 return 0;
1187
1188 no_tx_mem:
1189 return -ENOMEM;
1190 }
1191
1192 static void mtk_tx_clean(struct mtk_eth *eth)
1193 {
1194 struct mtk_tx_ring *ring = &eth->tx_ring;
1195 int i;
1196
1197 if (ring->buf) {
1198 for (i = 0; i < MTK_DMA_SIZE; i++)
1199 mtk_tx_unmap(eth, &ring->buf[i]);
1200 kfree(ring->buf);
1201 ring->buf = NULL;
1202 }
1203
1204 if (ring->dma) {
1205 dma_free_coherent(eth->dev,
1206 MTK_DMA_SIZE * sizeof(*ring->dma),
1207 ring->dma,
1208 ring->phys);
1209 ring->dma = NULL;
1210 }
1211 }
1212
1213 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1214 {
1215 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
1216 int rx_data_len, rx_dma_size;
1217 int i;
1218
1219 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1220 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1221 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1222 } else {
1223 rx_data_len = ETH_DATA_LEN;
1224 rx_dma_size = MTK_DMA_SIZE;
1225 }
1226
1227 ring->frag_size = mtk_max_frag_size(rx_data_len);
1228 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1229 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1230 GFP_KERNEL);
1231 if (!ring->data)
1232 return -ENOMEM;
1233
1234 for (i = 0; i < rx_dma_size; i++) {
1235 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1236 if (!ring->data[i])
1237 return -ENOMEM;
1238 }
1239
1240 ring->dma = dma_alloc_coherent(eth->dev,
1241 rx_dma_size * sizeof(*ring->dma),
1242 &ring->phys,
1243 GFP_ATOMIC | __GFP_ZERO);
1244 if (!ring->dma)
1245 return -ENOMEM;
1246
1247 for (i = 0; i < rx_dma_size; i++) {
1248 dma_addr_t dma_addr = dma_map_single(eth->dev,
1249 ring->data[i] + NET_SKB_PAD,
1250 ring->buf_size,
1251 DMA_FROM_DEVICE);
1252 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1253 return -ENOMEM;
1254 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1255
1256 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1257 }
1258 ring->dma_size = rx_dma_size;
1259 ring->calc_idx_update = false;
1260 ring->calc_idx = rx_dma_size - 1;
1261 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1262 /* make sure that all changes to the dma ring are flushed before we
1263 * continue
1264 */
1265 wmb();
1266
1267 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
1268 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
1269 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1270 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
1271
1272 return 0;
1273 }
1274
1275 static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
1276 {
1277 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
1278 int i;
1279
1280 if (ring->data && ring->dma) {
1281 for (i = 0; i < ring->dma_size; i++) {
1282 if (!ring->data[i])
1283 continue;
1284 if (!ring->dma[i].rxd1)
1285 continue;
1286 dma_unmap_single(eth->dev,
1287 ring->dma[i].rxd1,
1288 ring->buf_size,
1289 DMA_FROM_DEVICE);
1290 skb_free_frag(ring->data[i]);
1291 }
1292 kfree(ring->data);
1293 ring->data = NULL;
1294 }
1295
1296 if (ring->dma) {
1297 dma_free_coherent(eth->dev,
1298 ring->dma_size * sizeof(*ring->dma),
1299 ring->dma,
1300 ring->phys);
1301 ring->dma = NULL;
1302 }
1303 }
1304
1305 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1306 {
1307 int i;
1308 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1309 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1310
1311 /* set LRO rings to auto-learn modes */
1312 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1313
1314 /* validate LRO ring */
1315 ring_ctrl_dw2 |= MTK_RING_VLD;
1316
1317 /* set AGE timer (unit: 20us) */
1318 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1319 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1320
1321 /* set max AGG timer (unit: 20us) */
1322 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1323
1324 /* set max LRO AGG count */
1325 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1326 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1327
1328 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1329 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1330 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1331 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1332 }
1333
1334 /* IPv4 checksum update enable */
1335 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1336
1337 /* switch priority comparison to packet count mode */
1338 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1339
1340 /* bandwidth threshold setting */
1341 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1342
1343 /* auto-learn score delta setting */
1344 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1345
1346 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1347 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1348 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1349
1350 /* set HW LRO mode & the max aggregation count for rx packets */
1351 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1352
1353 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1354 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1355
1356 /* enable HW LRO */
1357 lro_ctrl_dw0 |= MTK_LRO_EN;
1358
1359 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1360 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1361
1362 return 0;
1363 }
1364
1365 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1366 {
1367 int i;
1368 u32 val;
1369
1370 /* relinquish lro rings, flush aggregated packets */
1371 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1372
1373 /* wait for relinquishments done */
1374 for (i = 0; i < 10; i++) {
1375 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1376 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1377 msleep(20);
1378 continue;
1379 }
1380 break;
1381 }
1382
1383 /* invalidate lro rings */
1384 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1385 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1386
1387 /* disable HW LRO */
1388 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1389 }
1390
1391 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1392 {
1393 u32 reg_val;
1394
1395 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1396
1397 /* invalidate the IP setting */
1398 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1399
1400 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1401
1402 /* validate the IP setting */
1403 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1404 }
1405
1406 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1407 {
1408 u32 reg_val;
1409
1410 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1411
1412 /* invalidate the IP setting */
1413 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1414
1415 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1416 }
1417
1418 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1419 {
1420 int cnt = 0;
1421 int i;
1422
1423 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1424 if (mac->hwlro_ip[i])
1425 cnt++;
1426 }
1427
1428 return cnt;
1429 }
1430
1431 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1432 struct ethtool_rxnfc *cmd)
1433 {
1434 struct ethtool_rx_flow_spec *fsp =
1435 (struct ethtool_rx_flow_spec *)&cmd->fs;
1436 struct mtk_mac *mac = netdev_priv(dev);
1437 struct mtk_eth *eth = mac->hw;
1438 int hwlro_idx;
1439
1440 if ((fsp->flow_type != TCP_V4_FLOW) ||
1441 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1442 (fsp->location > 1))
1443 return -EINVAL;
1444
1445 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1446 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1447
1448 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1449
1450 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1451
1452 return 0;
1453 }
1454
1455 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1456 struct ethtool_rxnfc *cmd)
1457 {
1458 struct ethtool_rx_flow_spec *fsp =
1459 (struct ethtool_rx_flow_spec *)&cmd->fs;
1460 struct mtk_mac *mac = netdev_priv(dev);
1461 struct mtk_eth *eth = mac->hw;
1462 int hwlro_idx;
1463
1464 if (fsp->location > 1)
1465 return -EINVAL;
1466
1467 mac->hwlro_ip[fsp->location] = 0;
1468 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1469
1470 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1471
1472 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1473
1474 return 0;
1475 }
1476
1477 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1478 {
1479 struct mtk_mac *mac = netdev_priv(dev);
1480 struct mtk_eth *eth = mac->hw;
1481 int i, hwlro_idx;
1482
1483 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1484 mac->hwlro_ip[i] = 0;
1485 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1486
1487 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1488 }
1489
1490 mac->hwlro_ip_cnt = 0;
1491 }
1492
1493 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1494 struct ethtool_rxnfc *cmd)
1495 {
1496 struct mtk_mac *mac = netdev_priv(dev);
1497 struct ethtool_rx_flow_spec *fsp =
1498 (struct ethtool_rx_flow_spec *)&cmd->fs;
1499
1500 /* only tcp dst ipv4 is meaningful, others are meaningless */
1501 fsp->flow_type = TCP_V4_FLOW;
1502 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1503 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1504
1505 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1506 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1507 fsp->h_u.tcp_ip4_spec.psrc = 0;
1508 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1509 fsp->h_u.tcp_ip4_spec.pdst = 0;
1510 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1511 fsp->h_u.tcp_ip4_spec.tos = 0;
1512 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1513
1514 return 0;
1515 }
1516
1517 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1518 struct ethtool_rxnfc *cmd,
1519 u32 *rule_locs)
1520 {
1521 struct mtk_mac *mac = netdev_priv(dev);
1522 int cnt = 0;
1523 int i;
1524
1525 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1526 if (mac->hwlro_ip[i]) {
1527 rule_locs[cnt] = i;
1528 cnt++;
1529 }
1530 }
1531
1532 cmd->rule_cnt = cnt;
1533
1534 return 0;
1535 }
1536
1537 static netdev_features_t mtk_fix_features(struct net_device *dev,
1538 netdev_features_t features)
1539 {
1540 if (!(features & NETIF_F_LRO)) {
1541 struct mtk_mac *mac = netdev_priv(dev);
1542 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1543
1544 if (ip_cnt) {
1545 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1546
1547 features |= NETIF_F_LRO;
1548 }
1549 }
1550
1551 return features;
1552 }
1553
1554 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1555 {
1556 int err = 0;
1557
1558 if (!((dev->features ^ features) & NETIF_F_LRO))
1559 return 0;
1560
1561 if (!(features & NETIF_F_LRO))
1562 mtk_hwlro_netdev_disable(dev);
1563
1564 return err;
1565 }
1566
1567 /* wait for DMA to finish whatever it is doing before we start using it again */
1568 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1569 {
1570 unsigned long t_start = jiffies;
1571
1572 while (1) {
1573 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1574 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1575 return 0;
1576 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1577 break;
1578 }
1579
1580 dev_err(eth->dev, "DMA init timeout\n");
1581 return -1;
1582 }
1583
1584 static int mtk_dma_init(struct mtk_eth *eth)
1585 {
1586 int err;
1587 u32 i;
1588
1589 if (mtk_dma_busy_wait(eth))
1590 return -EBUSY;
1591
1592 /* QDMA needs scratch memory for internal reordering of the
1593 * descriptors
1594 */
1595 err = mtk_init_fq_dma(eth);
1596 if (err)
1597 return err;
1598
1599 err = mtk_tx_alloc(eth);
1600 if (err)
1601 return err;
1602
1603 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1604 if (err)
1605 return err;
1606
1607 if (eth->hwlro) {
1608 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1609 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1610 if (err)
1611 return err;
1612 }
1613 err = mtk_hwlro_rx_init(eth);
1614 if (err)
1615 return err;
1616 }
1617
1618 /* Enable random early drop and set drop threshold automatically */
1619 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1620 MTK_QDMA_FC_THRES);
1621 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1622
1623 return 0;
1624 }
1625
1626 static void mtk_dma_free(struct mtk_eth *eth)
1627 {
1628 int i;
1629
1630 for (i = 0; i < MTK_MAC_COUNT; i++)
1631 if (eth->netdev[i])
1632 netdev_reset_queue(eth->netdev[i]);
1633 if (eth->scratch_ring) {
1634 dma_free_coherent(eth->dev,
1635 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1636 eth->scratch_ring,
1637 eth->phy_scratch_ring);
1638 eth->scratch_ring = NULL;
1639 eth->phy_scratch_ring = 0;
1640 }
1641 mtk_tx_clean(eth);
1642 mtk_rx_clean(eth, 0);
1643
1644 if (eth->hwlro) {
1645 mtk_hwlro_rx_uninit(eth);
1646 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1647 mtk_rx_clean(eth, i);
1648 }
1649
1650 kfree(eth->scratch_head);
1651 }
1652
1653 static void mtk_tx_timeout(struct net_device *dev)
1654 {
1655 struct mtk_mac *mac = netdev_priv(dev);
1656 struct mtk_eth *eth = mac->hw;
1657
1658 eth->netdev[mac->id]->stats.tx_errors++;
1659 netif_err(eth, tx_err, dev,
1660 "transmit timed out\n");
1661 schedule_work(&eth->pending_work);
1662 }
1663
1664 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1665 {
1666 struct mtk_eth *eth = _eth;
1667
1668 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1669 __napi_schedule(&eth->rx_napi);
1670 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1671 }
1672
1673 return IRQ_HANDLED;
1674 }
1675
1676 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1677 {
1678 struct mtk_eth *eth = _eth;
1679
1680 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1681 __napi_schedule(&eth->tx_napi);
1682 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1683 }
1684
1685 return IRQ_HANDLED;
1686 }
1687
1688 #ifdef CONFIG_NET_POLL_CONTROLLER
1689 static void mtk_poll_controller(struct net_device *dev)
1690 {
1691 struct mtk_mac *mac = netdev_priv(dev);
1692 struct mtk_eth *eth = mac->hw;
1693
1694 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1695 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1696 mtk_handle_irq_rx(eth->irq[2], dev);
1697 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1698 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1699 }
1700 #endif
1701
1702 static int mtk_start_dma(struct mtk_eth *eth)
1703 {
1704 int err;
1705
1706 err = mtk_dma_init(eth);
1707 if (err) {
1708 mtk_dma_free(eth);
1709 return err;
1710 }
1711
1712 mtk_w32(eth,
1713 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1714 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
1715 MTK_QDMA_GLO_CFG);
1716
1717 mtk_w32(eth,
1718 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1719 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1720 MTK_PDMA_GLO_CFG);
1721
1722 return 0;
1723 }
1724
1725 static int mtk_open(struct net_device *dev)
1726 {
1727 struct mtk_mac *mac = netdev_priv(dev);
1728 struct mtk_eth *eth = mac->hw;
1729
1730 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1731 if (!atomic_read(&eth->dma_refcnt)) {
1732 int err = mtk_start_dma(eth);
1733
1734 if (err)
1735 return err;
1736
1737 napi_enable(&eth->tx_napi);
1738 napi_enable(&eth->rx_napi);
1739 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1740 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1741 }
1742 atomic_inc(&eth->dma_refcnt);
1743
1744 phy_start(dev->phydev);
1745 netif_start_queue(dev);
1746
1747 return 0;
1748 }
1749
1750 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1751 {
1752 u32 val;
1753 int i;
1754
1755 /* stop the dma engine */
1756 spin_lock_bh(&eth->page_lock);
1757 val = mtk_r32(eth, glo_cfg);
1758 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1759 glo_cfg);
1760 spin_unlock_bh(&eth->page_lock);
1761
1762 /* wait for dma stop */
1763 for (i = 0; i < 10; i++) {
1764 val = mtk_r32(eth, glo_cfg);
1765 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1766 msleep(20);
1767 continue;
1768 }
1769 break;
1770 }
1771 }
1772
1773 static int mtk_stop(struct net_device *dev)
1774 {
1775 struct mtk_mac *mac = netdev_priv(dev);
1776 struct mtk_eth *eth = mac->hw;
1777
1778 netif_tx_disable(dev);
1779 phy_stop(dev->phydev);
1780
1781 /* only shutdown DMA if this is the last user */
1782 if (!atomic_dec_and_test(&eth->dma_refcnt))
1783 return 0;
1784
1785 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1786 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1787 napi_disable(&eth->tx_napi);
1788 napi_disable(&eth->rx_napi);
1789
1790 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1791 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1792
1793 mtk_dma_free(eth);
1794
1795 return 0;
1796 }
1797
1798 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1799 {
1800 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1801 reset_bits,
1802 reset_bits);
1803
1804 usleep_range(1000, 1100);
1805 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1806 reset_bits,
1807 ~reset_bits);
1808 mdelay(10);
1809 }
1810
1811 static int mtk_hw_init(struct mtk_eth *eth)
1812 {
1813 int i, val;
1814
1815 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1816 return 0;
1817
1818 pm_runtime_enable(eth->dev);
1819 pm_runtime_get_sync(eth->dev);
1820
1821 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1822 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1823 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1824 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
1825 ethsys_reset(eth, RSTCTRL_FE);
1826 ethsys_reset(eth, RSTCTRL_PPE);
1827
1828 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1829 for (i = 0; i < MTK_MAC_COUNT; i++) {
1830 if (!eth->mac[i])
1831 continue;
1832 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1833 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1834 }
1835 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1836
1837 /* Set GE2 driving and slew rate */
1838 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1839
1840 /* set GE2 TDSEL */
1841 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1842
1843 /* set GE2 TUNE */
1844 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1845
1846 /* GE1, Force 1000M/FD, FC ON */
1847 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1848
1849 /* GE2, Force 1000M/FD, FC ON */
1850 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1851
1852 /* Enable RX VLan Offloading */
1853 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1854
1855 /* disable delay and normal interrupt */
1856 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1857 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1858 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1859 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1860 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1861 mtk_w32(eth, 0, MTK_RST_GL);
1862
1863 /* FE int grouping */
1864 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1865 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1866 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1867 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1868 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1869
1870 for (i = 0; i < 2; i++) {
1871 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1872
1873 /* setup the forward port to send frame to PDMA */
1874 val &= ~0xffff;
1875
1876 /* Enable RX checksum */
1877 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1878
1879 /* setup the mac dma */
1880 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1881 }
1882
1883 return 0;
1884 }
1885
1886 static int mtk_hw_deinit(struct mtk_eth *eth)
1887 {
1888 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
1889 return 0;
1890
1891 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1892 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1893 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1894 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1895
1896 pm_runtime_put_sync(eth->dev);
1897 pm_runtime_disable(eth->dev);
1898
1899 return 0;
1900 }
1901
1902 static int __init mtk_init(struct net_device *dev)
1903 {
1904 struct mtk_mac *mac = netdev_priv(dev);
1905 struct mtk_eth *eth = mac->hw;
1906 const char *mac_addr;
1907
1908 mac_addr = of_get_mac_address(mac->of_node);
1909 if (mac_addr)
1910 ether_addr_copy(dev->dev_addr, mac_addr);
1911
1912 /* If the mac address is invalid, use random mac address */
1913 if (!is_valid_ether_addr(dev->dev_addr)) {
1914 random_ether_addr(dev->dev_addr);
1915 dev_err(eth->dev, "generated random MAC address %pM\n",
1916 dev->dev_addr);
1917 dev->addr_assign_type = NET_ADDR_RANDOM;
1918 }
1919
1920 return mtk_phy_connect(dev);
1921 }
1922
1923 static void mtk_uninit(struct net_device *dev)
1924 {
1925 struct mtk_mac *mac = netdev_priv(dev);
1926 struct mtk_eth *eth = mac->hw;
1927
1928 phy_disconnect(dev->phydev);
1929 if (of_phy_is_fixed_link(mac->of_node))
1930 of_phy_deregister_fixed_link(mac->of_node);
1931 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1932 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1933 }
1934
1935 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1936 {
1937 switch (cmd) {
1938 case SIOCGMIIPHY:
1939 case SIOCGMIIREG:
1940 case SIOCSMIIREG:
1941 return phy_mii_ioctl(dev->phydev, ifr, cmd);
1942 default:
1943 break;
1944 }
1945
1946 return -EOPNOTSUPP;
1947 }
1948
1949 static void mtk_pending_work(struct work_struct *work)
1950 {
1951 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1952 int err, i;
1953 unsigned long restart = 0;
1954
1955 rtnl_lock();
1956
1957 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
1958
1959 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
1960 cpu_relax();
1961
1962 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
1963 /* stop all devices to make sure that dma is properly shut down */
1964 for (i = 0; i < MTK_MAC_COUNT; i++) {
1965 if (!eth->netdev[i])
1966 continue;
1967 mtk_stop(eth->netdev[i]);
1968 __set_bit(i, &restart);
1969 }
1970 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
1971
1972 /* restart underlying hardware such as power, clock, pin mux
1973 * and the connected phy
1974 */
1975 mtk_hw_deinit(eth);
1976
1977 if (eth->dev->pins)
1978 pinctrl_select_state(eth->dev->pins->p,
1979 eth->dev->pins->default_state);
1980 mtk_hw_init(eth);
1981
1982 for (i = 0; i < MTK_MAC_COUNT; i++) {
1983 if (!eth->mac[i] ||
1984 of_phy_is_fixed_link(eth->mac[i]->of_node))
1985 continue;
1986 err = phy_init_hw(eth->netdev[i]->phydev);
1987 if (err)
1988 dev_err(eth->dev, "%s: PHY init failed.\n",
1989 eth->netdev[i]->name);
1990 }
1991
1992 /* restart DMA and enable IRQs */
1993 for (i = 0; i < MTK_MAC_COUNT; i++) {
1994 if (!test_bit(i, &restart))
1995 continue;
1996 err = mtk_open(eth->netdev[i]);
1997 if (err) {
1998 netif_alert(eth, ifup, eth->netdev[i],
1999 "Driver up/down cycle failed, closing device.\n");
2000 dev_close(eth->netdev[i]);
2001 }
2002 }
2003
2004 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2005
2006 clear_bit_unlock(MTK_RESETTING, &eth->state);
2007
2008 rtnl_unlock();
2009 }
2010
2011 static int mtk_free_dev(struct mtk_eth *eth)
2012 {
2013 int i;
2014
2015 for (i = 0; i < MTK_MAC_COUNT; i++) {
2016 if (!eth->netdev[i])
2017 continue;
2018 free_netdev(eth->netdev[i]);
2019 }
2020
2021 return 0;
2022 }
2023
2024 static int mtk_unreg_dev(struct mtk_eth *eth)
2025 {
2026 int i;
2027
2028 for (i = 0; i < MTK_MAC_COUNT; i++) {
2029 if (!eth->netdev[i])
2030 continue;
2031 unregister_netdev(eth->netdev[i]);
2032 }
2033
2034 return 0;
2035 }
2036
2037 static int mtk_cleanup(struct mtk_eth *eth)
2038 {
2039 mtk_unreg_dev(eth);
2040 mtk_free_dev(eth);
2041 cancel_work_sync(&eth->pending_work);
2042
2043 return 0;
2044 }
2045
2046 static int mtk_get_link_ksettings(struct net_device *ndev,
2047 struct ethtool_link_ksettings *cmd)
2048 {
2049 struct mtk_mac *mac = netdev_priv(ndev);
2050
2051 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2052 return -EBUSY;
2053
2054 return phy_ethtool_ksettings_get(ndev->phydev, cmd);
2055 }
2056
2057 static int mtk_set_link_ksettings(struct net_device *ndev,
2058 const struct ethtool_link_ksettings *cmd)
2059 {
2060 struct mtk_mac *mac = netdev_priv(ndev);
2061
2062 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2063 return -EBUSY;
2064
2065 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2066 }
2067
2068 static void mtk_get_drvinfo(struct net_device *dev,
2069 struct ethtool_drvinfo *info)
2070 {
2071 struct mtk_mac *mac = netdev_priv(dev);
2072
2073 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2074 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2075 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2076 }
2077
2078 static u32 mtk_get_msglevel(struct net_device *dev)
2079 {
2080 struct mtk_mac *mac = netdev_priv(dev);
2081
2082 return mac->hw->msg_enable;
2083 }
2084
2085 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2086 {
2087 struct mtk_mac *mac = netdev_priv(dev);
2088
2089 mac->hw->msg_enable = value;
2090 }
2091
2092 static int mtk_nway_reset(struct net_device *dev)
2093 {
2094 struct mtk_mac *mac = netdev_priv(dev);
2095
2096 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2097 return -EBUSY;
2098
2099 return genphy_restart_aneg(dev->phydev);
2100 }
2101
2102 static u32 mtk_get_link(struct net_device *dev)
2103 {
2104 struct mtk_mac *mac = netdev_priv(dev);
2105 int err;
2106
2107 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2108 return -EBUSY;
2109
2110 err = genphy_update_link(dev->phydev);
2111 if (err)
2112 return ethtool_op_get_link(dev);
2113
2114 return dev->phydev->link;
2115 }
2116
2117 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2118 {
2119 int i;
2120
2121 switch (stringset) {
2122 case ETH_SS_STATS:
2123 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2124 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2125 data += ETH_GSTRING_LEN;
2126 }
2127 break;
2128 }
2129 }
2130
2131 static int mtk_get_sset_count(struct net_device *dev, int sset)
2132 {
2133 switch (sset) {
2134 case ETH_SS_STATS:
2135 return ARRAY_SIZE(mtk_ethtool_stats);
2136 default:
2137 return -EOPNOTSUPP;
2138 }
2139 }
2140
2141 static void mtk_get_ethtool_stats(struct net_device *dev,
2142 struct ethtool_stats *stats, u64 *data)
2143 {
2144 struct mtk_mac *mac = netdev_priv(dev);
2145 struct mtk_hw_stats *hwstats = mac->hw_stats;
2146 u64 *data_src, *data_dst;
2147 unsigned int start;
2148 int i;
2149
2150 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2151 return;
2152
2153 if (netif_running(dev) && netif_device_present(dev)) {
2154 if (spin_trylock(&hwstats->stats_lock)) {
2155 mtk_stats_update_mac(mac);
2156 spin_unlock(&hwstats->stats_lock);
2157 }
2158 }
2159
2160 data_src = (u64 *)hwstats;
2161
2162 do {
2163 data_dst = data;
2164 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2165
2166 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2167 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2168 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2169 }
2170
2171 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2172 u32 *rule_locs)
2173 {
2174 int ret = -EOPNOTSUPP;
2175
2176 switch (cmd->cmd) {
2177 case ETHTOOL_GRXRINGS:
2178 if (dev->features & NETIF_F_LRO) {
2179 cmd->data = MTK_MAX_RX_RING_NUM;
2180 ret = 0;
2181 }
2182 break;
2183 case ETHTOOL_GRXCLSRLCNT:
2184 if (dev->features & NETIF_F_LRO) {
2185 struct mtk_mac *mac = netdev_priv(dev);
2186
2187 cmd->rule_cnt = mac->hwlro_ip_cnt;
2188 ret = 0;
2189 }
2190 break;
2191 case ETHTOOL_GRXCLSRULE:
2192 if (dev->features & NETIF_F_LRO)
2193 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2194 break;
2195 case ETHTOOL_GRXCLSRLALL:
2196 if (dev->features & NETIF_F_LRO)
2197 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2198 rule_locs);
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 return ret;
2205 }
2206
2207 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2208 {
2209 int ret = -EOPNOTSUPP;
2210
2211 switch (cmd->cmd) {
2212 case ETHTOOL_SRXCLSRLINS:
2213 if (dev->features & NETIF_F_LRO)
2214 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2215 break;
2216 case ETHTOOL_SRXCLSRLDEL:
2217 if (dev->features & NETIF_F_LRO)
2218 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2219 break;
2220 default:
2221 break;
2222 }
2223
2224 return ret;
2225 }
2226
2227 static const struct ethtool_ops mtk_ethtool_ops = {
2228 .get_link_ksettings = mtk_get_link_ksettings,
2229 .set_link_ksettings = mtk_set_link_ksettings,
2230 .get_drvinfo = mtk_get_drvinfo,
2231 .get_msglevel = mtk_get_msglevel,
2232 .set_msglevel = mtk_set_msglevel,
2233 .nway_reset = mtk_nway_reset,
2234 .get_link = mtk_get_link,
2235 .get_strings = mtk_get_strings,
2236 .get_sset_count = mtk_get_sset_count,
2237 .get_ethtool_stats = mtk_get_ethtool_stats,
2238 .get_rxnfc = mtk_get_rxnfc,
2239 .set_rxnfc = mtk_set_rxnfc,
2240 };
2241
2242 static const struct net_device_ops mtk_netdev_ops = {
2243 .ndo_init = mtk_init,
2244 .ndo_uninit = mtk_uninit,
2245 .ndo_open = mtk_open,
2246 .ndo_stop = mtk_stop,
2247 .ndo_start_xmit = mtk_start_xmit,
2248 .ndo_set_mac_address = mtk_set_mac_address,
2249 .ndo_validate_addr = eth_validate_addr,
2250 .ndo_do_ioctl = mtk_do_ioctl,
2251 .ndo_tx_timeout = mtk_tx_timeout,
2252 .ndo_get_stats64 = mtk_get_stats64,
2253 .ndo_fix_features = mtk_fix_features,
2254 .ndo_set_features = mtk_set_features,
2255 #ifdef CONFIG_NET_POLL_CONTROLLER
2256 .ndo_poll_controller = mtk_poll_controller,
2257 #endif
2258 };
2259
2260 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2261 {
2262 struct mtk_mac *mac;
2263 const __be32 *_id = of_get_property(np, "reg", NULL);
2264 int id, err;
2265
2266 if (!_id) {
2267 dev_err(eth->dev, "missing mac id\n");
2268 return -EINVAL;
2269 }
2270
2271 id = be32_to_cpup(_id);
2272 if (id >= MTK_MAC_COUNT) {
2273 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2274 return -EINVAL;
2275 }
2276
2277 if (eth->netdev[id]) {
2278 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2279 return -EINVAL;
2280 }
2281
2282 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2283 if (!eth->netdev[id]) {
2284 dev_err(eth->dev, "alloc_etherdev failed\n");
2285 return -ENOMEM;
2286 }
2287 mac = netdev_priv(eth->netdev[id]);
2288 eth->mac[id] = mac;
2289 mac->id = id;
2290 mac->hw = eth;
2291 mac->of_node = np;
2292
2293 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2294 mac->hwlro_ip_cnt = 0;
2295
2296 mac->hw_stats = devm_kzalloc(eth->dev,
2297 sizeof(*mac->hw_stats),
2298 GFP_KERNEL);
2299 if (!mac->hw_stats) {
2300 dev_err(eth->dev, "failed to allocate counter memory\n");
2301 err = -ENOMEM;
2302 goto free_netdev;
2303 }
2304 spin_lock_init(&mac->hw_stats->stats_lock);
2305 u64_stats_init(&mac->hw_stats->syncp);
2306 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2307
2308 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2309 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2310 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2311 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2312
2313 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2314 if (eth->hwlro)
2315 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2316
2317 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2318 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2319 eth->netdev[id]->features |= MTK_HW_FEATURES;
2320 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2321
2322 eth->netdev[id]->irq = eth->irq[0];
2323 return 0;
2324
2325 free_netdev:
2326 free_netdev(eth->netdev[id]);
2327 return err;
2328 }
2329
2330 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id)
2331 {
2332 u32 val[2], id[4];
2333
2334 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]);
2335 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]);
2336
2337 id[3] = ((val[0] >> 16) & 0xff) - '0';
2338 id[2] = ((val[0] >> 24) & 0xff) - '0';
2339 id[1] = (val[1] & 0xff) - '0';
2340 id[0] = ((val[1] >> 8) & 0xff) - '0';
2341
2342 *chip_id = (id[3] * 1000) + (id[2] * 100) +
2343 (id[1] * 10) + id[0];
2344
2345 if (!(*chip_id)) {
2346 dev_err(eth->dev, "failed to get chip id\n");
2347 return -ENODEV;
2348 }
2349
2350 dev_info(eth->dev, "chip id = %d\n", *chip_id);
2351
2352 return 0;
2353 }
2354
2355 static bool mtk_is_hwlro_supported(struct mtk_eth *eth)
2356 {
2357 switch (eth->chip_id) {
2358 case MT7623_ETH:
2359 return true;
2360 }
2361
2362 return false;
2363 }
2364
2365 static int mtk_probe(struct platform_device *pdev)
2366 {
2367 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2368 struct device_node *mac_np;
2369 const struct of_device_id *match;
2370 struct mtk_soc_data *soc;
2371 struct mtk_eth *eth;
2372 int err;
2373 int i;
2374
2375 match = of_match_device(of_mtk_match, &pdev->dev);
2376 soc = (struct mtk_soc_data *)match->data;
2377
2378 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2379 if (!eth)
2380 return -ENOMEM;
2381
2382 eth->dev = &pdev->dev;
2383 eth->base = devm_ioremap_resource(&pdev->dev, res);
2384 if (IS_ERR(eth->base))
2385 return PTR_ERR(eth->base);
2386
2387 spin_lock_init(&eth->page_lock);
2388 spin_lock_init(&eth->irq_lock);
2389
2390 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2391 "mediatek,ethsys");
2392 if (IS_ERR(eth->ethsys)) {
2393 dev_err(&pdev->dev, "no ethsys regmap found\n");
2394 return PTR_ERR(eth->ethsys);
2395 }
2396
2397 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2398 "mediatek,pctl");
2399 if (IS_ERR(eth->pctl)) {
2400 dev_err(&pdev->dev, "no pctl regmap found\n");
2401 return PTR_ERR(eth->pctl);
2402 }
2403
2404 for (i = 0; i < 3; i++) {
2405 eth->irq[i] = platform_get_irq(pdev, i);
2406 if (eth->irq[i] < 0) {
2407 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2408 return -ENXIO;
2409 }
2410 }
2411 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2412 eth->clks[i] = devm_clk_get(eth->dev,
2413 mtk_clks_source_name[i]);
2414 if (IS_ERR(eth->clks[i])) {
2415 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2416 return -EPROBE_DEFER;
2417 return -ENODEV;
2418 }
2419 }
2420
2421 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2422 INIT_WORK(&eth->pending_work, mtk_pending_work);
2423
2424 err = mtk_hw_init(eth);
2425 if (err)
2426 return err;
2427
2428 err = mtk_get_chip_id(eth, &eth->chip_id);
2429 if (err)
2430 return err;
2431
2432 eth->hwlro = mtk_is_hwlro_supported(eth);
2433
2434 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2435 if (!of_device_is_compatible(mac_np,
2436 "mediatek,eth-mac"))
2437 continue;
2438
2439 if (!of_device_is_available(mac_np))
2440 continue;
2441
2442 err = mtk_add_mac(eth, mac_np);
2443 if (err)
2444 goto err_deinit_hw;
2445 }
2446
2447 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2448 dev_name(eth->dev), eth);
2449 if (err)
2450 goto err_free_dev;
2451
2452 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2453 dev_name(eth->dev), eth);
2454 if (err)
2455 goto err_free_dev;
2456
2457 err = mtk_mdio_init(eth);
2458 if (err)
2459 goto err_free_dev;
2460
2461 for (i = 0; i < MTK_MAX_DEVS; i++) {
2462 if (!eth->netdev[i])
2463 continue;
2464
2465 err = register_netdev(eth->netdev[i]);
2466 if (err) {
2467 dev_err(eth->dev, "error bringing up device\n");
2468 goto err_deinit_mdio;
2469 } else
2470 netif_info(eth, probe, eth->netdev[i],
2471 "mediatek frame engine at 0x%08lx, irq %d\n",
2472 eth->netdev[i]->base_addr, eth->irq[0]);
2473 }
2474
2475 /* we run 2 devices on the same DMA ring so we need a dummy device
2476 * for NAPI to work
2477 */
2478 init_dummy_netdev(&eth->dummy_dev);
2479 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2480 MTK_NAPI_WEIGHT);
2481 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
2482 MTK_NAPI_WEIGHT);
2483
2484 platform_set_drvdata(pdev, eth);
2485
2486 return 0;
2487
2488 err_deinit_mdio:
2489 mtk_mdio_cleanup(eth);
2490 err_free_dev:
2491 mtk_free_dev(eth);
2492 err_deinit_hw:
2493 mtk_hw_deinit(eth);
2494
2495 return err;
2496 }
2497
2498 static int mtk_remove(struct platform_device *pdev)
2499 {
2500 struct mtk_eth *eth = platform_get_drvdata(pdev);
2501 int i;
2502
2503 /* stop all devices to make sure that dma is properly shut down */
2504 for (i = 0; i < MTK_MAC_COUNT; i++) {
2505 if (!eth->netdev[i])
2506 continue;
2507 mtk_stop(eth->netdev[i]);
2508 }
2509
2510 mtk_hw_deinit(eth);
2511
2512 netif_napi_del(&eth->tx_napi);
2513 netif_napi_del(&eth->rx_napi);
2514 mtk_cleanup(eth);
2515 mtk_mdio_cleanup(eth);
2516
2517 return 0;
2518 }
2519
2520 const struct of_device_id of_mtk_match[] = {
2521 { .compatible = "mediatek,mt2701-eth" },
2522 {},
2523 };
2524 MODULE_DEVICE_TABLE(of, of_mtk_match);
2525
2526 static struct platform_driver mtk_driver = {
2527 .probe = mtk_probe,
2528 .remove = mtk_remove,
2529 .driver = {
2530 .name = "mtk_soc_eth",
2531 .of_match_table = of_mtk_match,
2532 },
2533 };
2534
2535 module_platform_driver(mtk_driver);
2536
2537 MODULE_LICENSE("GPL");
2538 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2539 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux with added FPC-III support