x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / pci / pci.h
blob8dd38e69d6f2a8ae4f4b7d6801f3f321abb5ac1a
1 #ifndef DRIVERS_PCI_H
2 #define DRIVERS_PCI_H
4 #define PCI_FIND_CAP_TTL 48
6 extern const unsigned char pcie_link_speed[];
8 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
10 /* Functions internal to the PCI core code */
12 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
13 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
14 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
15 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
16 { return; }
17 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
18 { return; }
19 #else
20 void pci_create_firmware_label_files(struct pci_dev *pdev);
21 void pci_remove_firmware_label_files(struct pci_dev *pdev);
22 #endif
23 void pci_cleanup_rom(struct pci_dev *dev);
24 #ifdef HAVE_PCI_MMAP
25 enum pci_mmap_api {
26 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
27 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
29 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
30 enum pci_mmap_api mmap_api);
31 #endif
32 int pci_probe_reset_function(struct pci_dev *dev);
34 /**
35 * struct pci_platform_pm_ops - Firmware PM callbacks
37 * @is_manageable: returns 'true' if given device is power manageable by the
38 * platform firmware
40 * @set_state: invokes the platform firmware to set the device's power state
42 * @get_state: queries the platform firmware for a device's current power state
44 * @choose_state: returns PCI power state of given device preferred by the
45 * platform; to be used during system-wide transitions from a
46 * sleeping state to the working state and vice versa
48 * @sleep_wake: enables/disables the system wake up capability of given device
50 * @run_wake: enables/disables the platform to generate run-time wake-up events
51 * for given device (the device's wake-up capability has to be
52 * enabled by @sleep_wake for this feature to work)
54 * @need_resume: returns 'true' if the given device (which is currently
55 * suspended) needs to be resumed to be configured for system
56 * wakeup.
58 * If given platform is generally capable of power managing PCI devices, all of
59 * these callbacks are mandatory.
61 struct pci_platform_pm_ops {
62 bool (*is_manageable)(struct pci_dev *dev);
63 int (*set_state)(struct pci_dev *dev, pci_power_t state);
64 pci_power_t (*get_state)(struct pci_dev *dev);
65 pci_power_t (*choose_state)(struct pci_dev *dev);
66 int (*sleep_wake)(struct pci_dev *dev, bool enable);
67 int (*run_wake)(struct pci_dev *dev, bool enable);
68 bool (*need_resume)(struct pci_dev *dev);
71 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
72 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
73 void pci_power_up(struct pci_dev *dev);
74 void pci_disable_enabled_device(struct pci_dev *dev);
75 int pci_finish_runtime_suspend(struct pci_dev *dev);
76 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
77 bool pci_dev_keep_suspended(struct pci_dev *dev);
78 void pci_dev_complete_resume(struct pci_dev *pci_dev);
79 void pci_config_pm_runtime_get(struct pci_dev *dev);
80 void pci_config_pm_runtime_put(struct pci_dev *dev);
81 void pci_pm_init(struct pci_dev *dev);
82 void pci_ea_init(struct pci_dev *dev);
83 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84 void pci_free_cap_save_buffers(struct pci_dev *dev);
85 bool pci_bridge_d3_possible(struct pci_dev *dev);
86 void pci_bridge_d3_update(struct pci_dev *dev);
88 static inline void pci_wakeup_event(struct pci_dev *dev)
90 /* Wait 100 ms before the system can be put into a sleep state. */
91 pm_wakeup_event(&dev->dev, 100);
94 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
96 return !!(pci_dev->subordinate);
99 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
102 * Currently we allow normal PCI devices and PCI bridges transition
103 * into D3 if their bridge_d3 is set.
105 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
108 struct pci_vpd_ops {
109 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
110 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
111 int (*set_size)(struct pci_dev *dev, size_t len);
114 struct pci_vpd {
115 const struct pci_vpd_ops *ops;
116 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
117 struct mutex lock;
118 unsigned int len;
119 u16 flag;
120 u8 cap;
121 u8 busy:1;
122 u8 valid:1;
125 int pci_vpd_init(struct pci_dev *dev);
126 void pci_vpd_release(struct pci_dev *dev);
128 /* PCI /proc functions */
129 #ifdef CONFIG_PROC_FS
130 int pci_proc_attach_device(struct pci_dev *dev);
131 int pci_proc_detach_device(struct pci_dev *dev);
132 int pci_proc_detach_bus(struct pci_bus *bus);
133 #else
134 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
135 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
136 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
137 #endif
139 /* Functions for PCI Hotplug drivers to use */
140 int pci_hp_add_bridge(struct pci_dev *dev);
142 #ifdef HAVE_PCI_LEGACY
143 void pci_create_legacy_files(struct pci_bus *bus);
144 void pci_remove_legacy_files(struct pci_bus *bus);
145 #else
146 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
147 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
148 #endif
150 /* Lock for read/write access to pci device and bus lists */
151 extern struct rw_semaphore pci_bus_sem;
153 extern raw_spinlock_t pci_lock;
155 extern unsigned int pci_pm_d3_delay;
157 #ifdef CONFIG_PCI_MSI
158 void pci_no_msi(void);
159 #else
160 static inline void pci_no_msi(void) { }
161 #endif
163 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
165 u16 control;
167 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
168 control &= ~PCI_MSI_FLAGS_ENABLE;
169 if (enable)
170 control |= PCI_MSI_FLAGS_ENABLE;
171 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
174 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
176 u16 ctrl;
178 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
179 ctrl &= ~clear;
180 ctrl |= set;
181 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
184 void pci_realloc_get_opt(char *);
186 static inline int pci_no_d1d2(struct pci_dev *dev)
188 unsigned int parent_dstates = 0;
190 if (dev->bus->self)
191 parent_dstates = dev->bus->self->no_d1d2;
192 return (dev->no_d1d2 || parent_dstates);
195 extern const struct attribute_group *pci_dev_groups[];
196 extern const struct attribute_group *pcibus_groups[];
197 extern struct device_type pci_dev_type;
198 extern const struct attribute_group *pci_bus_groups[];
202 * pci_match_one_device - Tell if a PCI device structure has a matching
203 * PCI device id structure
204 * @id: single PCI device id structure to match
205 * @dev: the PCI device structure to match against
207 * Returns the matching pci_device_id structure or %NULL if there is no match.
209 static inline const struct pci_device_id *
210 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
212 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
213 (id->device == PCI_ANY_ID || id->device == dev->device) &&
214 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
215 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
216 !((id->class ^ dev->class) & id->class_mask))
217 return id;
218 return NULL;
221 /* PCI slot sysfs helper code */
222 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
224 extern struct kset *pci_slots_kset;
226 struct pci_slot_attribute {
227 struct attribute attr;
228 ssize_t (*show)(struct pci_slot *, char *);
229 ssize_t (*store)(struct pci_slot *, const char *, size_t);
231 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
233 enum pci_bar_type {
234 pci_bar_unknown, /* Standard PCI BAR probe */
235 pci_bar_io, /* An io port BAR */
236 pci_bar_mem32, /* A 32-bit memory BAR */
237 pci_bar_mem64, /* A 64-bit memory BAR */
240 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
241 int crs_timeout);
242 int pci_setup_device(struct pci_dev *dev);
243 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
244 struct resource *res, unsigned int reg);
245 void pci_configure_ari(struct pci_dev *dev);
246 void __pci_bus_size_bridges(struct pci_bus *bus,
247 struct list_head *realloc_head);
248 void __pci_bus_assign_resources(const struct pci_bus *bus,
249 struct list_head *realloc_head,
250 struct list_head *fail_head);
251 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
253 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
254 void pci_disable_bridge_window(struct pci_dev *dev);
256 /* Single Root I/O Virtualization */
257 struct pci_sriov {
258 int pos; /* capability position */
259 int nres; /* number of resources */
260 u32 cap; /* SR-IOV Capabilities */
261 u16 ctrl; /* SR-IOV Control */
262 u16 total_VFs; /* total VFs associated with the PF */
263 u16 initial_VFs; /* initial VFs associated with the PF */
264 u16 num_VFs; /* number of VFs available */
265 u16 offset; /* first VF Routing ID offset */
266 u16 stride; /* following VF stride */
267 u32 pgsz; /* page size for BAR alignment */
268 u8 link; /* Function Dependency Link */
269 u8 max_VF_buses; /* max buses consumed by VFs */
270 u16 driver_max_VFs; /* max num VFs driver supports */
271 struct pci_dev *dev; /* lowest numbered PF */
272 struct pci_dev *self; /* this PF */
273 struct mutex lock; /* lock for setting sriov_numvfs in sysfs */
274 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
277 #ifdef CONFIG_PCI_ATS
278 void pci_restore_ats_state(struct pci_dev *dev);
279 #else
280 static inline void pci_restore_ats_state(struct pci_dev *dev)
283 #endif /* CONFIG_PCI_ATS */
285 #ifdef CONFIG_PCI_IOV
286 int pci_iov_init(struct pci_dev *dev);
287 void pci_iov_release(struct pci_dev *dev);
288 void pci_iov_update_resource(struct pci_dev *dev, int resno);
289 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
290 void pci_restore_iov_state(struct pci_dev *dev);
291 int pci_iov_bus_range(struct pci_bus *bus);
293 #else
294 static inline int pci_iov_init(struct pci_dev *dev)
296 return -ENODEV;
298 static inline void pci_iov_release(struct pci_dev *dev)
302 static inline void pci_restore_iov_state(struct pci_dev *dev)
305 static inline int pci_iov_bus_range(struct pci_bus *bus)
307 return 0;
310 #endif /* CONFIG_PCI_IOV */
312 unsigned long pci_cardbus_resource_alignment(struct resource *);
314 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
315 struct resource *res)
317 #ifdef CONFIG_PCI_IOV
318 int resno = res - dev->resource;
320 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
321 return pci_sriov_resource_alignment(dev, resno);
322 #endif
323 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
324 return pci_cardbus_resource_alignment(res);
325 return resource_alignment(res);
328 void pci_enable_acs(struct pci_dev *dev);
330 #ifdef CONFIG_PCIE_PTM
331 void pci_ptm_init(struct pci_dev *dev);
332 #else
333 static inline void pci_ptm_init(struct pci_dev *dev) { }
334 #endif
336 struct pci_dev_reset_methods {
337 u16 vendor;
338 u16 device;
339 int (*reset)(struct pci_dev *dev, int probe);
342 #ifdef CONFIG_PCI_QUIRKS
343 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
344 #else
345 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
347 return -ENOTTY;
349 #endif
351 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
352 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
353 struct resource *res);
354 #endif
356 #endif /* DRIVERS_PCI_H */