2 * Procfs interface for the PCI bus.
4 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <linux/uaccess.h>
15 #include <asm/byteorder.h>
18 static int proc_initialized
; /* = 0 */
20 static loff_t
proc_bus_pci_lseek(struct file
*file
, loff_t off
, int whence
)
22 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
23 return fixed_size_llseek(file
, off
, whence
, dev
->cfg_size
);
26 static ssize_t
proc_bus_pci_read(struct file
*file
, char __user
*buf
,
27 size_t nbytes
, loff_t
*ppos
)
29 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
30 unsigned int pos
= *ppos
;
31 unsigned int cnt
, size
;
34 * Normal users can read only the standardized portion of the
35 * configuration space as several chips lock up when trying to read
36 * undefined locations (think of Intel PIIX4 as a typical example).
39 if (capable(CAP_SYS_ADMIN
))
41 else if (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
50 if (pos
+ nbytes
> size
)
54 if (!access_ok(VERIFY_WRITE
, buf
, cnt
))
57 pci_config_pm_runtime_get(dev
);
59 if ((pos
& 1) && cnt
) {
61 pci_user_read_config_byte(dev
, pos
, &val
);
68 if ((pos
& 3) && cnt
> 2) {
70 pci_user_read_config_word(dev
, pos
, &val
);
71 __put_user(cpu_to_le16(val
), (__le16 __user
*) buf
);
79 pci_user_read_config_dword(dev
, pos
, &val
);
80 __put_user(cpu_to_le32(val
), (__le32 __user
*) buf
);
88 pci_user_read_config_word(dev
, pos
, &val
);
89 __put_user(cpu_to_le16(val
), (__le16 __user
*) buf
);
97 pci_user_read_config_byte(dev
, pos
, &val
);
104 pci_config_pm_runtime_put(dev
);
110 static ssize_t
proc_bus_pci_write(struct file
*file
, const char __user
*buf
,
111 size_t nbytes
, loff_t
*ppos
)
113 struct inode
*ino
= file_inode(file
);
114 struct pci_dev
*dev
= PDE_DATA(ino
);
116 int size
= dev
->cfg_size
;
123 if (pos
+ nbytes
> size
)
127 if (!access_ok(VERIFY_READ
, buf
, cnt
))
130 pci_config_pm_runtime_get(dev
);
132 if ((pos
& 1) && cnt
) {
134 __get_user(val
, buf
);
135 pci_user_write_config_byte(dev
, pos
, val
);
141 if ((pos
& 3) && cnt
> 2) {
143 __get_user(val
, (__le16 __user
*) buf
);
144 pci_user_write_config_word(dev
, pos
, le16_to_cpu(val
));
152 __get_user(val
, (__le32 __user
*) buf
);
153 pci_user_write_config_dword(dev
, pos
, le32_to_cpu(val
));
161 __get_user(val
, (__le16 __user
*) buf
);
162 pci_user_write_config_word(dev
, pos
, le16_to_cpu(val
));
170 __get_user(val
, buf
);
171 pci_user_write_config_byte(dev
, pos
, val
);
177 pci_config_pm_runtime_put(dev
);
180 i_size_write(ino
, dev
->cfg_size
);
184 struct pci_filp_private
{
185 enum pci_mmap_state mmap_state
;
189 static long proc_bus_pci_ioctl(struct file
*file
, unsigned int cmd
,
192 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
194 struct pci_filp_private
*fpriv
= file
->private_data
;
195 #endif /* HAVE_PCI_MMAP */
199 case PCIIOC_CONTROLLER
:
200 ret
= pci_domain_nr(dev
->bus
);
204 case PCIIOC_MMAP_IS_IO
:
205 fpriv
->mmap_state
= pci_mmap_io
;
208 case PCIIOC_MMAP_IS_MEM
:
209 fpriv
->mmap_state
= pci_mmap_mem
;
212 case PCIIOC_WRITE_COMBINE
:
214 fpriv
->write_combine
= 1;
216 fpriv
->write_combine
= 0;
219 #endif /* HAVE_PCI_MMAP */
230 static int proc_bus_pci_mmap(struct file
*file
, struct vm_area_struct
*vma
)
232 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
233 struct pci_filp_private
*fpriv
= file
->private_data
;
234 int i
, ret
, write_combine
= 0, res_bit
;
236 if (!capable(CAP_SYS_RAWIO
))
239 if (fpriv
->mmap_state
== pci_mmap_io
)
240 res_bit
= IORESOURCE_IO
;
242 res_bit
= IORESOURCE_MEM
;
244 /* Make sure the caller is mapping a real resource for this device */
245 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++) {
246 if (dev
->resource
[i
].flags
& res_bit
&&
247 pci_mmap_fits(dev
, i
, vma
, PCI_MMAP_PROCFS
))
251 if (i
>= PCI_ROM_RESOURCE
)
254 if (fpriv
->mmap_state
== pci_mmap_mem
&&
255 fpriv
->write_combine
) {
256 if (dev
->resource
[i
].flags
& IORESOURCE_PREFETCH
)
261 ret
= pci_mmap_page_range(dev
, vma
,
262 fpriv
->mmap_state
, write_combine
);
269 static int proc_bus_pci_open(struct inode
*inode
, struct file
*file
)
271 struct pci_filp_private
*fpriv
= kmalloc(sizeof(*fpriv
), GFP_KERNEL
);
276 fpriv
->mmap_state
= pci_mmap_io
;
277 fpriv
->write_combine
= 0;
279 file
->private_data
= fpriv
;
284 static int proc_bus_pci_release(struct inode
*inode
, struct file
*file
)
286 kfree(file
->private_data
);
287 file
->private_data
= NULL
;
291 #endif /* HAVE_PCI_MMAP */
293 static const struct file_operations proc_bus_pci_operations
= {
294 .owner
= THIS_MODULE
,
295 .llseek
= proc_bus_pci_lseek
,
296 .read
= proc_bus_pci_read
,
297 .write
= proc_bus_pci_write
,
298 .unlocked_ioctl
= proc_bus_pci_ioctl
,
299 .compat_ioctl
= proc_bus_pci_ioctl
,
301 .open
= proc_bus_pci_open
,
302 .release
= proc_bus_pci_release
,
303 .mmap
= proc_bus_pci_mmap
,
304 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
305 .get_unmapped_area
= get_pci_unmapped_area
,
306 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
307 #endif /* HAVE_PCI_MMAP */
311 static void *pci_seq_start(struct seq_file
*m
, loff_t
*pos
)
313 struct pci_dev
*dev
= NULL
;
316 for_each_pci_dev(dev
) {
323 static void *pci_seq_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
325 struct pci_dev
*dev
= v
;
328 dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
);
332 static void pci_seq_stop(struct seq_file
*m
, void *v
)
335 struct pci_dev
*dev
= v
;
340 static int show_device(struct seq_file
*m
, void *v
)
342 const struct pci_dev
*dev
= v
;
343 const struct pci_driver
*drv
;
349 drv
= pci_dev_driver(dev
);
350 seq_printf(m
, "%02x%02x\t%04x%04x\t%x",
357 /* only print standard and ROM resources to preserve compatibility */
358 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
359 resource_size_t start
, end
;
360 pci_resource_to_user(dev
, i
, &dev
->resource
[i
], &start
, &end
);
361 seq_printf(m
, "\t%16llx",
362 (unsigned long long)(start
|
363 (dev
->resource
[i
].flags
& PCI_REGION_FLAG_MASK
)));
365 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
366 resource_size_t start
, end
;
367 pci_resource_to_user(dev
, i
, &dev
->resource
[i
], &start
, &end
);
368 seq_printf(m
, "\t%16llx",
369 dev
->resource
[i
].start
< dev
->resource
[i
].end
?
370 (unsigned long long)(end
- start
) + 1 : 0);
374 seq_printf(m
, "%s", drv
->name
);
379 static const struct seq_operations proc_bus_pci_devices_op
= {
380 .start
= pci_seq_start
,
381 .next
= pci_seq_next
,
382 .stop
= pci_seq_stop
,
386 static struct proc_dir_entry
*proc_bus_pci_dir
;
388 int pci_proc_attach_device(struct pci_dev
*dev
)
390 struct pci_bus
*bus
= dev
->bus
;
391 struct proc_dir_entry
*e
;
394 if (!proc_initialized
)
398 if (pci_proc_domain(bus
)) {
399 sprintf(name
, "%04x:%02x", pci_domain_nr(bus
),
402 sprintf(name
, "%02x", bus
->number
);
404 bus
->procdir
= proc_mkdir(name
, proc_bus_pci_dir
);
409 sprintf(name
, "%02x.%x", PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
));
410 e
= proc_create_data(name
, S_IFREG
| S_IRUGO
| S_IWUSR
, bus
->procdir
,
411 &proc_bus_pci_operations
, dev
);
414 proc_set_size(e
, dev
->cfg_size
);
420 int pci_proc_detach_device(struct pci_dev
*dev
)
422 proc_remove(dev
->procent
);
427 int pci_proc_detach_bus(struct pci_bus
*bus
)
429 proc_remove(bus
->procdir
);
433 static int proc_bus_pci_dev_open(struct inode
*inode
, struct file
*file
)
435 return seq_open(file
, &proc_bus_pci_devices_op
);
438 static const struct file_operations proc_bus_pci_dev_operations
= {
439 .owner
= THIS_MODULE
,
440 .open
= proc_bus_pci_dev_open
,
443 .release
= seq_release
,
446 static int __init
pci_proc_init(void)
448 struct pci_dev
*dev
= NULL
;
449 proc_bus_pci_dir
= proc_mkdir("bus/pci", NULL
);
450 proc_create("devices", 0, proc_bus_pci_dir
,
451 &proc_bus_pci_dev_operations
);
452 proc_initialized
= 1;
453 for_each_pci_dev(dev
)
454 pci_proc_attach_device(dev
);
458 device_initcall(pci_proc_init
);