drivers/phy/phy-rockchip-emmc.c

   1 /*
   2  * Rockchip emmc PHY driver
   3  *
   4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
   5  * Copyright (C) 2016 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26
  27 /*
  28  * The higher 16-bit of this register is used for write protection
  29  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
  30  */
  31 #define HIWORD_UPDATE(val, mask, shift) \
  32                 ((val) << (shift) | (mask) << ((shift) + 16))
  33
  34 /* Register definition */
  35 #define GRF_EMMCPHY_CON0                0x0
  36 #define GRF_EMMCPHY_CON1                0x4
  37 #define GRF_EMMCPHY_CON2                0x8
  38 #define GRF_EMMCPHY_CON3                0xc
  39 #define GRF_EMMCPHY_CON4                0x10
  40 #define GRF_EMMCPHY_CON5                0x14
  41 #define GRF_EMMCPHY_CON6                0x18
  42 #define GRF_EMMCPHY_STATUS              0x20
  43
  44 #define PHYCTRL_PDB_MASK                0x1
  45 #define PHYCTRL_PDB_SHIFT               0x0
  46 #define PHYCTRL_PDB_PWR_ON              0x1
  47 #define PHYCTRL_PDB_PWR_OFF             0x0
  48 #define PHYCTRL_ENDLL_MASK              0x1
  49 #define PHYCTRL_ENDLL_SHIFT             0x1
  50 #define PHYCTRL_ENDLL_ENABLE            0x1
  51 #define PHYCTRL_ENDLL_DISABLE           0x0
  52 #define PHYCTRL_CALDONE_MASK            0x1
  53 #define PHYCTRL_CALDONE_SHIFT           0x6
  54 #define PHYCTRL_CALDONE_DONE            0x1
  55 #define PHYCTRL_CALDONE_GOING           0x0
  56 #define PHYCTRL_DLLRDY_MASK             0x1
  57 #define PHYCTRL_DLLRDY_SHIFT            0x5
  58 #define PHYCTRL_DLLRDY_DONE             0x1
  59 #define PHYCTRL_DLLRDY_GOING            0x0
  60 #define PHYCTRL_FREQSEL_200M            0x0
  61 #define PHYCTRL_FREQSEL_50M             0x1
  62 #define PHYCTRL_FREQSEL_100M            0x2
  63 #define PHYCTRL_FREQSEL_150M            0x3
  64 #define PHYCTRL_FREQSEL_MASK            0x3
  65 #define PHYCTRL_FREQSEL_SHIFT           0xc
  66 #define PHYCTRL_DR_MASK                 0x7
  67 #define PHYCTRL_DR_SHIFT                0x4
  68 #define PHYCTRL_DR_50OHM                0x0
  69 #define PHYCTRL_DR_33OHM                0x1
  70 #define PHYCTRL_DR_66OHM                0x2
  71 #define PHYCTRL_DR_100OHM               0x3
  72 #define PHYCTRL_DR_40OHM                0x4
  73 #define PHYCTRL_OTAPDLYENA              0x1
  74 #define PHYCTRL_OTAPDLYENA_MASK         0x1
  75 #define PHYCTRL_OTAPDLYENA_SHIFT        0xb
  76 #define PHYCTRL_OTAPDLYSEL_MASK         0xf
  77 #define PHYCTRL_OTAPDLYSEL_SHIFT        0x7
  78
  79 struct rockchip_emmc_phy {
  80         unsigned int    reg_offset;
  81         struct regmap   *reg_base;
  82         struct clk      *emmcclk;
  83 };
  84
  85 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
  86 {
  87         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
  88         unsigned int caldone;
  89         unsigned int dllrdy;
  90         unsigned int freqsel = PHYCTRL_FREQSEL_200M;
  91         unsigned long rate;
  92         unsigned long timeout;
  93
  94         /*
  95          * Keep phyctrl_pdb and phyctrl_endll low to allow
  96          * initialization of CALIO state M/C DFFs
  97          */
  98         regmap_write(rk_phy->reg_base,
  99                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 100                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
 101                                    PHYCTRL_PDB_MASK,
 102                                    PHYCTRL_PDB_SHIFT));
 103         regmap_write(rk_phy->reg_base,
 104                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 105                      HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
 106                                    PHYCTRL_ENDLL_MASK,
 107                                    PHYCTRL_ENDLL_SHIFT));
 108
 109         /* Already finish power_off above */
 110         if (on_off == PHYCTRL_PDB_PWR_OFF)
 111                 return 0;
 112
 113         rate = clk_get_rate(rk_phy->emmcclk);
 114
 115         if (rate != 0) {
 116                 unsigned long ideal_rate;
 117                 unsigned long diff;
 118
 119                 switch (rate) {
 120                 case 1 ... 74999999:
 121                         ideal_rate = 50000000;
 122                         freqsel = PHYCTRL_FREQSEL_50M;
 123                         break;
 124                 case 75000000 ... 124999999:
 125                         ideal_rate = 100000000;
 126                         freqsel = PHYCTRL_FREQSEL_100M;
 127                         break;
 128                 case 125000000 ... 174999999:
 129                         ideal_rate = 150000000;
 130                         freqsel = PHYCTRL_FREQSEL_150M;
 131                         break;
 132                 default:
 133                         ideal_rate = 200000000;
 134                         break;
 135                 }
 136
 137                 diff = (rate > ideal_rate) ?
 138                         rate - ideal_rate : ideal_rate - rate;
 139
 140                 /*
 141                  * In order for tuning delays to be accurate we need to be
 142                  * pretty spot on for the DLL range, so warn if we're too
 143                  * far off.  Also warn if we're above the 200 MHz max.  Don't
 144                  * warn for really slow rates since we won't be tuning then.
 145                  */
 146                 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
 147                         dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
 148         }
 149
 150         /*
 151          * According to the user manual, calpad calibration
 152          * cycle takes more than 2us without the minimal recommended
 153          * value, so we may need a little margin here
 154          */
 155         udelay(3);
 156         regmap_write(rk_phy->reg_base,
 157                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 158                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
 159                                    PHYCTRL_PDB_MASK,
 160                                    PHYCTRL_PDB_SHIFT));
 161
 162         /*
 163          * According to the user manual, it asks driver to
 164          * wait 5us for calpad busy trimming
 165          */
 166         udelay(5);
 167         regmap_read(rk_phy->reg_base,
 168                     rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 169                     &caldone);
 170         caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 171         if (caldone != PHYCTRL_CALDONE_DONE) {
 172                 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
 173                 return -ETIMEDOUT;
 174         }
 175
 176         /* Set the frequency of the DLL operation */
 177         regmap_write(rk_phy->reg_base,
 178                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 179                      HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
 180                                    PHYCTRL_FREQSEL_SHIFT));
 181
 182         /* Turn on the DLL */
 183         regmap_write(rk_phy->reg_base,
 184                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 185                      HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
 186                                    PHYCTRL_ENDLL_MASK,
 187                                    PHYCTRL_ENDLL_SHIFT));
 188
 189         /*
 190          * We turned on the DLL even though the rate was 0 because we the
 191          * clock might be turned on later.  ...but we can't wait for the DLL
 192          * to lock when the rate is 0 because it will never lock with no
 193          * input clock.
 194          *
 195          * Technically we should be checking the lock later when the clock
 196          * is turned on, but for now we won't.
 197          */
 198         if (rate == 0)
 199                 return 0;
 200
 201         /*
 202          * After enabling analog DLL circuits docs say that we need 10.2 us if
 203          * our source clock is at 50 MHz and that lock time scales linearly
 204          * with clock speed.  If we are powering on the PHY and the card clock
 205          * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
 206          * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
 207          * Hopefully we won't be running at 100 kHz, but we should still make
 208          * sure we wait long enough.
 209          *
 210          * NOTE: There appear to be corner cases where the DLL seems to take
 211          * extra long to lock for reasons that aren't understood.  In some
 212          * extreme cases we've seen it take up to over 10ms (!).  We'll be
 213          * generous and give it 50ms.  We still busy wait here because:
 214          * - In most cases it should be super fast.
 215          * - This is not called lots during normal operation so it shouldn't
 216          *   be a power or performance problem to busy wait.  We expect it
 217          *   only at boot / resume.  In both cases, eMMC is probably on the
 218          *   critical path so busy waiting a little extra time should be OK.
 219          */
 220         timeout = jiffies + msecs_to_jiffies(50);
 221         do {
 222                 udelay(1);
 223
 224                 regmap_read(rk_phy->reg_base,
 225                         rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 226                         &dllrdy);
 227                 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
 228                 if (dllrdy == PHYCTRL_DLLRDY_DONE)
 229                         break;
 230         } while (!time_after(jiffies, timeout));
 231
 232         if (dllrdy != PHYCTRL_DLLRDY_DONE) {
 233                 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
 234                 return -ETIMEDOUT;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int rockchip_emmc_phy_init(struct phy *phy)
 241 {
 242         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 243         int ret = 0;
 244
 245         /*
 246          * We purposely get the clock here and not in probe to avoid the
 247          * circular dependency problem.  We expect:
 248          * - PHY driver to probe
 249          * - SDHCI driver to start probe
 250          * - SDHCI driver to register it's clock
 251          * - SDHCI driver to get the PHY
 252          * - SDHCI driver to init the PHY
 253          *
 254          * The clock is optional, so upon any error we just set to NULL.
 255          *
 256          * NOTE: we don't do anything special for EPROBE_DEFER here.  Given the
 257          * above expected use case, EPROBE_DEFER isn't sensible to expect, so
 258          * it's just like any other error.
 259          */
 260         rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
 261         if (IS_ERR(rk_phy->emmcclk)) {
 262                 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
 263                 rk_phy->emmcclk = NULL;
 264         }
 265
 266         return ret;
 267 }
 268
 269 static int rockchip_emmc_phy_exit(struct phy *phy)
 270 {
 271         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 272
 273         clk_put(rk_phy->emmcclk);
 274
 275         return 0;
 276 }
 277
 278 static int rockchip_emmc_phy_power_off(struct phy *phy)
 279 {
 280         /* Power down emmc phy analog blocks */
 281         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
 282 }
 283
 284 static int rockchip_emmc_phy_power_on(struct phy *phy)
 285 {
 286         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 287
 288         /* Drive impedance: 50 Ohm */
 289         regmap_write(rk_phy->reg_base,
 290                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 291                      HIWORD_UPDATE(PHYCTRL_DR_50OHM,
 292                                    PHYCTRL_DR_MASK,
 293                                    PHYCTRL_DR_SHIFT));
 294
 295         /* Output tap delay: enable */
 296         regmap_write(rk_phy->reg_base,
 297                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 298                      HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
 299                                    PHYCTRL_OTAPDLYENA_MASK,
 300                                    PHYCTRL_OTAPDLYENA_SHIFT));
 301
 302         /* Output tap delay */
 303         regmap_write(rk_phy->reg_base,
 304                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 305                      HIWORD_UPDATE(4,
 306                                    PHYCTRL_OTAPDLYSEL_MASK,
 307                                    PHYCTRL_OTAPDLYSEL_SHIFT));
 308
 309         /* Power up emmc phy analog blocks */
 310         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
 311 }
 312
 313 static const struct phy_ops ops = {
 314         .init           = rockchip_emmc_phy_init,
 315         .exit           = rockchip_emmc_phy_exit,
 316         .power_on       = rockchip_emmc_phy_power_on,
 317         .power_off      = rockchip_emmc_phy_power_off,
 318         .owner          = THIS_MODULE,
 319 };
 320
 321 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
 322 {
 323         struct device *dev = &pdev->dev;
 324         struct rockchip_emmc_phy *rk_phy;
 325         struct phy *generic_phy;
 326         struct phy_provider *phy_provider;
 327         struct regmap *grf;
 328         unsigned int reg_offset;
 329
 330         if (!dev->parent || !dev->parent->of_node)
 331                 return -ENODEV;
 332
 333         grf = syscon_node_to_regmap(dev->parent->of_node);
 334         if (IS_ERR(grf)) {
 335                 dev_err(dev, "Missing rockchip,grf property\n");
 336                 return PTR_ERR(grf);
 337         }
 338
 339         rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
 340         if (!rk_phy)
 341                 return -ENOMEM;
 342
 343         if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
 344                 dev_err(dev, "missing reg property in node %s\n",
 345                         dev->of_node->name);
 346                 return -EINVAL;
 347         }
 348
 349         rk_phy->reg_offset = reg_offset;
 350         rk_phy->reg_base = grf;
 351
 352         generic_phy = devm_phy_create(dev, dev->of_node, &ops);
 353         if (IS_ERR(generic_phy)) {
 354                 dev_err(dev, "failed to create PHY\n");
 355                 return PTR_ERR(generic_phy);
 356         }
 357
 358         phy_set_drvdata(generic_phy, rk_phy);
 359         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 360
 361         return PTR_ERR_OR_ZERO(phy_provider);
 362 }
 363
 364 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
 365         { .compatible = "rockchip,rk3399-emmc-phy" },
 366         {}
 367 };
 368
 369 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
 370
 371 static struct platform_driver rockchip_emmc_driver = {
 372         .probe          = rockchip_emmc_phy_probe,
 373         .driver         = {
 374                 .name   = "rockchip-emmc-phy",
 375                 .of_match_table = rockchip_emmc_phy_dt_ids,
 376         },
 377 };
 378
 379 module_platform_driver(rockchip_emmc_driver);
 380
 381 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
 382 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
 383 MODULE_LICENSE("GPL v2");