drivers/pwm/pwm-atmel.c

   1 /*
   2  * Driver for Atmel Pulse Width Modulation Controller
   3  *
   4  * Copyright (C) 2013 Atmel Corporation
   5  *               Bo Shen <voice.shen@atmel.com>
   6  *
   7  * Licensed under GPLv2.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pwm.h>
  20 #include <linux/slab.h>
  21
  22 /* The following is global registers for PWM controller */
  23 #define PWM_ENA                 0x04
  24 #define PWM_DIS                 0x08
  25 #define PWM_SR                  0x0C
  26 #define PWM_ISR                 0x1C
  27 /* Bit field in SR */
  28 #define PWM_SR_ALL_CH_ON        0x0F
  29
  30 /* The following register is PWM channel related registers */
  31 #define PWM_CH_REG_OFFSET       0x200
  32 #define PWM_CH_REG_SIZE         0x20
  33
  34 #define PWM_CMR                 0x0
  35 /* Bit field in CMR */
  36 #define PWM_CMR_CPOL            (1 << 9)
  37 #define PWM_CMR_UPD_CDTY        (1 << 10)
  38 #define PWM_CMR_CPRE_MSK        0xF
  39
  40 /* The following registers for PWM v1 */
  41 #define PWMV1_CDTY              0x04
  42 #define PWMV1_CPRD              0x08
  43 #define PWMV1_CUPD              0x10
  44
  45 /* The following registers for PWM v2 */
  46 #define PWMV2_CDTY              0x04
  47 #define PWMV2_CDTYUPD           0x08
  48 #define PWMV2_CPRD              0x0C
  49 #define PWMV2_CPRDUPD           0x10
  50
  51 /*
  52  * Max value for duty and period
  53  *
  54  * Although the duty and period register is 32 bit,
  55  * however only the LSB 16 bits are significant.
  56  */
  57 #define PWM_MAX_DTY             0xFFFF
  58 #define PWM_MAX_PRD             0xFFFF
  59 #define PRD_MAX_PRES            10
  60
  61 struct atmel_pwm_chip {
  62         struct pwm_chip chip;
  63         struct clk *clk;
  64         void __iomem *base;
  65
  66         unsigned int updated_pwms;
  67         /* ISR is cleared when read, ensure only one thread does that */
  68         struct mutex isr_lock;
  69
  70         void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
  71                        unsigned long dty, unsigned long prd);
  72 };
  73
  74 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
  75 {
  76         return container_of(chip, struct atmel_pwm_chip, chip);
  77 }
  78
  79 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
  80                                   unsigned long offset)
  81 {
  82         return readl_relaxed(chip->base + offset);
  83 }
  84
  85 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
  86                                     unsigned long offset, unsigned long val)
  87 {
  88         writel_relaxed(val, chip->base + offset);
  89 }
  90
  91 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
  92                                      unsigned int ch, unsigned long offset)
  93 {
  94         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
  95
  96         return readl_relaxed(chip->base + base + offset);
  97 }
  98
  99 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
 100                                        unsigned int ch, unsigned long offset,
 101                                        unsigned long val)
 102 {
 103         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 104
 105         writel_relaxed(val, chip->base + base + offset);
 106 }
 107
 108 static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 109                             int duty_ns, int period_ns)
 110 {
 111         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 112         unsigned long prd, dty;
 113         unsigned long long div;
 114         unsigned int pres = 0;
 115         u32 val;
 116         int ret;
 117
 118         if (pwm_is_enabled(pwm) && (period_ns != pwm_get_period(pwm))) {
 119                 dev_err(chip->dev, "cannot change PWM period while enabled\n");
 120                 return -EBUSY;
 121         }
 122
 123         /* Calculate the period cycles and prescale value */
 124         div = (unsigned long long)clk_get_rate(atmel_pwm->clk) * period_ns;
 125         do_div(div, NSEC_PER_SEC);
 126
 127         while (div > PWM_MAX_PRD) {
 128                 div >>= 1;
 129                 pres++;
 130         }
 131
 132         if (pres > PRD_MAX_PRES) {
 133                 dev_err(chip->dev, "pres exceeds the maximum value\n");
 134                 return -EINVAL;
 135         }
 136
 137         /* Calculate the duty cycles */
 138         prd = div;
 139         div *= duty_ns;
 140         do_div(div, period_ns);
 141         dty = prd - div;
 142
 143         ret = clk_enable(atmel_pwm->clk);
 144         if (ret) {
 145                 dev_err(chip->dev, "failed to enable PWM clock\n");
 146                 return ret;
 147         }
 148
 149         /* It is necessary to preserve CPOL, inside CMR */
 150         val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 151         val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
 152         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 153         atmel_pwm->config(chip, pwm, dty, prd);
 154         mutex_lock(&atmel_pwm->isr_lock);
 155         atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 156         atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
 157         mutex_unlock(&atmel_pwm->isr_lock);
 158
 159         clk_disable(atmel_pwm->clk);
 160         return ret;
 161 }
 162
 163 static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
 164                                 unsigned long dty, unsigned long prd)
 165 {
 166         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 167         unsigned int val;
 168
 169
 170         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
 171
 172         val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 173         val &= ~PWM_CMR_UPD_CDTY;
 174         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 175
 176         /*
 177          * If the PWM channel is enabled, only update CDTY by using the update
 178          * register, it needs to set bit 10 of CMR to 0
 179          */
 180         if (pwm_is_enabled(pwm))
 181                 return;
 182         /*
 183          * If the PWM channel is disabled, write value to duty and period
 184          * registers directly.
 185          */
 186         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
 187         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
 188 }
 189
 190 static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
 191                                 unsigned long dty, unsigned long prd)
 192 {
 193         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 194
 195         if (pwm_is_enabled(pwm)) {
 196                 /*
 197                  * If the PWM channel is enabled, using the duty update register
 198                  * to update the value.
 199                  */
 200                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
 201         } else {
 202                 /*
 203                  * If the PWM channel is disabled, write value to duty and
 204                  * period registers directly.
 205                  */
 206                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
 207                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
 208         }
 209 }
 210
 211 static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 212                                   enum pwm_polarity polarity)
 213 {
 214         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 215         u32 val;
 216         int ret;
 217
 218         val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 219
 220         if (polarity == PWM_POLARITY_NORMAL)
 221                 val &= ~PWM_CMR_CPOL;
 222         else
 223                 val |= PWM_CMR_CPOL;
 224
 225         ret = clk_enable(atmel_pwm->clk);
 226         if (ret) {
 227                 dev_err(chip->dev, "failed to enable PWM clock\n");
 228                 return ret;
 229         }
 230
 231         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 232
 233         clk_disable(atmel_pwm->clk);
 234
 235         return 0;
 236 }
 237
 238 static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 239 {
 240         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 241         int ret;
 242
 243         ret = clk_enable(atmel_pwm->clk);
 244         if (ret) {
 245                 dev_err(chip->dev, "failed to enable PWM clock\n");
 246                 return ret;
 247         }
 248
 249         atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
 250
 251         return 0;
 252 }
 253
 254 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 255 {
 256         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 257         unsigned long timeout = jiffies + 2 * HZ;
 258
 259         /*
 260          * Wait for at least a complete period to have passed before disabling a
 261          * channel to be sure that CDTY has been updated
 262          */
 263         mutex_lock(&atmel_pwm->isr_lock);
 264         atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 265
 266         while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
 267                time_before(jiffies, timeout)) {
 268                 usleep_range(10, 100);
 269                 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 270         }
 271
 272         mutex_unlock(&atmel_pwm->isr_lock);
 273         atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
 274
 275         /*
 276          * Wait for the PWM channel disable operation to be effective before
 277          * stopping the clock.
 278          */
 279         timeout = jiffies + 2 * HZ;
 280
 281         while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
 282                time_before(jiffies, timeout))
 283                 usleep_range(10, 100);
 284
 285         clk_disable(atmel_pwm->clk);
 286 }
 287
 288 static const struct pwm_ops atmel_pwm_ops = {
 289         .config = atmel_pwm_config,
 290         .set_polarity = atmel_pwm_set_polarity,
 291         .enable = atmel_pwm_enable,
 292         .disable = atmel_pwm_disable,
 293         .owner = THIS_MODULE,
 294 };
 295
 296 struct atmel_pwm_data {
 297         void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
 298                        unsigned long dty, unsigned long prd);
 299 };
 300
 301 static const struct atmel_pwm_data atmel_pwm_data_v1 = {
 302         .config = atmel_pwm_config_v1,
 303 };
 304
 305 static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 306         .config = atmel_pwm_config_v2,
 307 };
 308
 309 static const struct platform_device_id atmel_pwm_devtypes[] = {
 310         {
 311                 .name = "at91sam9rl-pwm",
 312                 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
 313         }, {
 314                 .name = "sama5d3-pwm",
 315                 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
 316         }, {
 317                 /* sentinel */
 318         },
 319 };
 320 MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
 321
 322 static const struct of_device_id atmel_pwm_dt_ids[] = {
 323         {
 324                 .compatible = "atmel,at91sam9rl-pwm",
 325                 .data = &atmel_pwm_data_v1,
 326         }, {
 327                 .compatible = "atmel,sama5d3-pwm",
 328                 .data = &atmel_pwm_data_v2,
 329         }, {
 330                 /* sentinel */
 331         },
 332 };
 333 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
 334
 335 static inline const struct atmel_pwm_data *
 336 atmel_pwm_get_driver_data(struct platform_device *pdev)
 337 {
 338         const struct platform_device_id *id;
 339
 340         if (pdev->dev.of_node)
 341                 return of_device_get_match_data(&pdev->dev);
 342
 343         id = platform_get_device_id(pdev);
 344
 345         return (struct atmel_pwm_data *)id->driver_data;
 346 }
 347
 348 static int atmel_pwm_probe(struct platform_device *pdev)
 349 {
 350         const struct atmel_pwm_data *data;
 351         struct atmel_pwm_chip *atmel_pwm;
 352         struct resource *res;
 353         int ret;
 354
 355         data = atmel_pwm_get_driver_data(pdev);
 356         if (!data)
 357                 return -ENODEV;
 358
 359         atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
 360         if (!atmel_pwm)
 361                 return -ENOMEM;
 362
 363         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 364         atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
 365         if (IS_ERR(atmel_pwm->base))
 366                 return PTR_ERR(atmel_pwm->base);
 367
 368         atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
 369         if (IS_ERR(atmel_pwm->clk))
 370                 return PTR_ERR(atmel_pwm->clk);
 371
 372         ret = clk_prepare(atmel_pwm->clk);
 373         if (ret) {
 374                 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
 375                 return ret;
 376         }
 377
 378         atmel_pwm->chip.dev = &pdev->dev;
 379         atmel_pwm->chip.ops = &atmel_pwm_ops;
 380
 381         if (pdev->dev.of_node) {
 382                 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 383                 atmel_pwm->chip.of_pwm_n_cells = 3;
 384         }
 385
 386         atmel_pwm->chip.base = -1;
 387         atmel_pwm->chip.npwm = 4;
 388         atmel_pwm->config = data->config;
 389         atmel_pwm->updated_pwms = 0;
 390         mutex_init(&atmel_pwm->isr_lock);
 391
 392         ret = pwmchip_add(&atmel_pwm->chip);
 393         if (ret < 0) {
 394                 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
 395                 goto unprepare_clk;
 396         }
 397
 398         platform_set_drvdata(pdev, atmel_pwm);
 399
 400         return ret;
 401
 402 unprepare_clk:
 403         clk_unprepare(atmel_pwm->clk);
 404         return ret;
 405 }
 406
 407 static int atmel_pwm_remove(struct platform_device *pdev)
 408 {
 409         struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
 410
 411         clk_unprepare(atmel_pwm->clk);
 412         mutex_destroy(&atmel_pwm->isr_lock);
 413
 414         return pwmchip_remove(&atmel_pwm->chip);
 415 }
 416
 417 static struct platform_driver atmel_pwm_driver = {
 418         .driver = {
 419                 .name = "atmel-pwm",
 420                 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
 421         },
 422         .id_table = atmel_pwm_devtypes,
 423         .probe = atmel_pwm_probe,
 424         .remove = atmel_pwm_remove,
 425 };
 426 module_platform_driver(atmel_pwm_driver);
 427
 428 MODULE_ALIAS("platform:atmel-pwm");
 429 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
 430 MODULE_DESCRIPTION("Atmel PWM driver");
 431 MODULE_LICENSE("GPL v2");