drivers/pwm/pwm-tiecap.c

   1 /*
   2  * ECAP PWM driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/io.h>
  24 #include <linux/err.h>
  25 #include <linux/clk.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/pwm.h>
  28 #include <linux/of_device.h>
  29
  30 /* ECAP registers and bits definitions */
  31 #define CAP1                    0x08
  32 #define CAP2                    0x0C
  33 #define CAP3                    0x10
  34 #define CAP4                    0x14
  35 #define ECCTL2                  0x2A
  36 #define ECCTL2_APWM_POL_LOW     BIT(10)
  37 #define ECCTL2_APWM_MODE        BIT(9)
  38 #define ECCTL2_SYNC_SEL_DISA    (BIT(7) | BIT(6))
  39 #define ECCTL2_TSCTR_FREERUN    BIT(4)
  40
  41 struct ecap_context {
  42         u32     cap3;
  43         u32     cap4;
  44         u16     ecctl2;
  45 };
  46
  47 struct ecap_pwm_chip {
  48         struct pwm_chip chip;
  49         unsigned int    clk_rate;
  50         void __iomem    *mmio_base;
  51         struct ecap_context ctx;
  52 };
  53
  54 static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
  55 {
  56         return container_of(chip, struct ecap_pwm_chip, chip);
  57 }
  58
  59 /*
  60  * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
  61  * duty_ns   = 10^9 * duty_cycles / PWM_CLK_RATE
  62  */
  63 static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  64                 int duty_ns, int period_ns)
  65 {
  66         struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  67         unsigned long long c;
  68         unsigned long period_cycles, duty_cycles;
  69         unsigned int reg_val;
  70
  71         if (period_ns > NSEC_PER_SEC)
  72                 return -ERANGE;
  73
  74         c = pc->clk_rate;
  75         c = c * period_ns;
  76         do_div(c, NSEC_PER_SEC);
  77         period_cycles = (unsigned long)c;
  78
  79         if (period_cycles < 1) {
  80                 period_cycles = 1;
  81                 duty_cycles = 1;
  82         } else {
  83                 c = pc->clk_rate;
  84                 c = c * duty_ns;
  85                 do_div(c, NSEC_PER_SEC);
  86                 duty_cycles = (unsigned long)c;
  87         }
  88
  89         pm_runtime_get_sync(pc->chip.dev);
  90
  91         reg_val = readw(pc->mmio_base + ECCTL2);
  92
  93         /* Configure APWM mode & disable sync option */
  94         reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
  95
  96         writew(reg_val, pc->mmio_base + ECCTL2);
  97
  98         if (!pwm_is_enabled(pwm)) {
  99                 /* Update active registers if not running */
 100                 writel(duty_cycles, pc->mmio_base + CAP2);
 101                 writel(period_cycles, pc->mmio_base + CAP1);
 102         } else {
 103                 /*
 104                  * Update shadow registers to configure period and
 105                  * compare values. This helps current PWM period to
 106                  * complete on reconfiguring
 107                  */
 108                 writel(duty_cycles, pc->mmio_base + CAP4);
 109                 writel(period_cycles, pc->mmio_base + CAP3);
 110         }
 111
 112         if (!pwm_is_enabled(pwm)) {
 113                 reg_val = readw(pc->mmio_base + ECCTL2);
 114                 /* Disable APWM mode to put APWM output Low */
 115                 reg_val &= ~ECCTL2_APWM_MODE;
 116                 writew(reg_val, pc->mmio_base + ECCTL2);
 117         }
 118
 119         pm_runtime_put_sync(pc->chip.dev);
 120         return 0;
 121 }
 122
 123 static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 124                 enum pwm_polarity polarity)
 125 {
 126         struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 127         unsigned short reg_val;
 128
 129         pm_runtime_get_sync(pc->chip.dev);
 130         reg_val = readw(pc->mmio_base + ECCTL2);
 131         if (polarity == PWM_POLARITY_INVERSED)
 132                 /* Duty cycle defines LOW period of PWM */
 133                 reg_val |= ECCTL2_APWM_POL_LOW;
 134         else
 135                 /* Duty cycle defines HIGH period of PWM */
 136                 reg_val &= ~ECCTL2_APWM_POL_LOW;
 137
 138         writew(reg_val, pc->mmio_base + ECCTL2);
 139         pm_runtime_put_sync(pc->chip.dev);
 140         return 0;
 141 }
 142
 143 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 144 {
 145         struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 146         unsigned int reg_val;
 147
 148         /* Leave clock enabled on enabling PWM */
 149         pm_runtime_get_sync(pc->chip.dev);
 150
 151         /*
 152          * Enable 'Free run Time stamp counter mode' to start counter
 153          * and  'APWM mode' to enable APWM output
 154          */
 155         reg_val = readw(pc->mmio_base + ECCTL2);
 156         reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
 157         writew(reg_val, pc->mmio_base + ECCTL2);
 158         return 0;
 159 }
 160
 161 static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 162 {
 163         struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 164         unsigned int reg_val;
 165
 166         /*
 167          * Disable 'Free run Time stamp counter mode' to stop counter
 168          * and 'APWM mode' to put APWM output to low
 169          */
 170         reg_val = readw(pc->mmio_base + ECCTL2);
 171         reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
 172         writew(reg_val, pc->mmio_base + ECCTL2);
 173
 174         /* Disable clock on PWM disable */
 175         pm_runtime_put_sync(pc->chip.dev);
 176 }
 177
 178 static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 179 {
 180         if (pwm_is_enabled(pwm)) {
 181                 dev_warn(chip->dev, "Removing PWM device without disabling\n");
 182                 pm_runtime_put_sync(chip->dev);
 183         }
 184 }
 185
 186 static const struct pwm_ops ecap_pwm_ops = {
 187         .free           = ecap_pwm_free,
 188         .config         = ecap_pwm_config,
 189         .set_polarity   = ecap_pwm_set_polarity,
 190         .enable         = ecap_pwm_enable,
 191         .disable        = ecap_pwm_disable,
 192         .owner          = THIS_MODULE,
 193 };
 194
 195 static const struct of_device_id ecap_of_match[] = {
 196         { .compatible   = "ti,am3352-ecap" },
 197         { .compatible   = "ti,am33xx-ecap" },
 198         {},
 199 };
 200 MODULE_DEVICE_TABLE(of, ecap_of_match);
 201
 202 static int ecap_pwm_probe(struct platform_device *pdev)
 203 {
 204         struct device_node *np = pdev->dev.of_node;
 205         int ret;
 206         struct resource *r;
 207         struct clk *clk;
 208         struct ecap_pwm_chip *pc;
 209
 210         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 211         if (!pc)
 212                 return -ENOMEM;
 213
 214         clk = devm_clk_get(&pdev->dev, "fck");
 215         if (IS_ERR(clk)) {
 216                 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
 217                         dev_warn(&pdev->dev, "Binding is obsolete.\n");
 218                         clk = devm_clk_get(pdev->dev.parent, "fck");
 219                 }
 220         }
 221
 222         if (IS_ERR(clk)) {
 223                 dev_err(&pdev->dev, "failed to get clock\n");
 224                 return PTR_ERR(clk);
 225         }
 226
 227         pc->clk_rate = clk_get_rate(clk);
 228         if (!pc->clk_rate) {
 229                 dev_err(&pdev->dev, "failed to get clock rate\n");
 230                 return -EINVAL;
 231         }
 232
 233         pc->chip.dev = &pdev->dev;
 234         pc->chip.ops = &ecap_pwm_ops;
 235         pc->chip.of_xlate = of_pwm_xlate_with_flags;
 236         pc->chip.of_pwm_n_cells = 3;
 237         pc->chip.base = -1;
 238         pc->chip.npwm = 1;
 239
 240         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 241         pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 242         if (IS_ERR(pc->mmio_base))
 243                 return PTR_ERR(pc->mmio_base);
 244
 245         ret = pwmchip_add(&pc->chip);
 246         if (ret < 0) {
 247                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 248                 return ret;
 249         }
 250
 251         pm_runtime_enable(&pdev->dev);
 252
 253         platform_set_drvdata(pdev, pc);
 254         return 0;
 255 }
 256
 257 static int ecap_pwm_remove(struct platform_device *pdev)
 258 {
 259         struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
 260
 261         pm_runtime_disable(&pdev->dev);
 262         return pwmchip_remove(&pc->chip);
 263 }
 264
 265 #ifdef CONFIG_PM_SLEEP
 266 static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
 267 {
 268         pm_runtime_get_sync(pc->chip.dev);
 269         pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
 270         pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
 271         pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
 272         pm_runtime_put_sync(pc->chip.dev);
 273 }
 274
 275 static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
 276 {
 277         writel(pc->ctx.cap3, pc->mmio_base + CAP3);
 278         writel(pc->ctx.cap4, pc->mmio_base + CAP4);
 279         writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
 280 }
 281
 282 static int ecap_pwm_suspend(struct device *dev)
 283 {
 284         struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
 285         struct pwm_device *pwm = pc->chip.pwms;
 286
 287         ecap_pwm_save_context(pc);
 288
 289         /* Disable explicitly if PWM is running */
 290         if (pwm_is_enabled(pwm))
 291                 pm_runtime_put_sync(dev);
 292
 293         return 0;
 294 }
 295
 296 static int ecap_pwm_resume(struct device *dev)
 297 {
 298         struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
 299         struct pwm_device *pwm = pc->chip.pwms;
 300
 301         /* Enable explicitly if PWM was running */
 302         if (pwm_is_enabled(pwm))
 303                 pm_runtime_get_sync(dev);
 304
 305         ecap_pwm_restore_context(pc);
 306         return 0;
 307 }
 308 #endif
 309
 310 static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
 311
 312 static struct platform_driver ecap_pwm_driver = {
 313         .driver = {
 314                 .name   = "ecap",
 315                 .of_match_table = ecap_of_match,
 316                 .pm     = &ecap_pwm_pm_ops,
 317         },
 318         .probe = ecap_pwm_probe,
 319         .remove = ecap_pwm_remove,
 320 };
 321
 322 module_platform_driver(ecap_pwm_driver);
 323
 324 MODULE_DESCRIPTION("ECAP PWM driver");
 325 MODULE_AUTHOR("Texas Instruments");
 326 MODULE_LICENSE("GPL");