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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_def.h
blobeddbc1218a39ba511700d3d4f446771eb06524f8
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
29
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
36
37 #include "qla_bsg.h"
38 #include "qla_nx.h"
39 #include "qla_nx2.h"
40 #define QLA2XXX_DRIVER_NAME "qla2xxx"
41 #define QLA2XXX_APIDEV "ql2xapidev"
42 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
43
44 /*
45 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
46 * but that's fine as we don't look at the last 24 ones for
47 * ISP2100 HBAs.
48 */
49 #define MAILBOX_REGISTER_COUNT_2100 8
50 #define MAILBOX_REGISTER_COUNT_2200 24
51 #define MAILBOX_REGISTER_COUNT 32
52
53 #define QLA2200A_RISC_ROM_VER 4
54 #define FPM_2300 6
55 #define FPM_2310 7
56
57 #include "qla_settings.h"
58
59 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
60
61 /*
62 * Data bit definitions
63 */
64 #define BIT_0 0x1
65 #define BIT_1 0x2
66 #define BIT_2 0x4
67 #define BIT_3 0x8
68 #define BIT_4 0x10
69 #define BIT_5 0x20
70 #define BIT_6 0x40
71 #define BIT_7 0x80
72 #define BIT_8 0x100
73 #define BIT_9 0x200
74 #define BIT_10 0x400
75 #define BIT_11 0x800
76 #define BIT_12 0x1000
77 #define BIT_13 0x2000
78 #define BIT_14 0x4000
79 #define BIT_15 0x8000
80 #define BIT_16 0x10000
81 #define BIT_17 0x20000
82 #define BIT_18 0x40000
83 #define BIT_19 0x80000
84 #define BIT_20 0x100000
85 #define BIT_21 0x200000
86 #define BIT_22 0x400000
87 #define BIT_23 0x800000
88 #define BIT_24 0x1000000
89 #define BIT_25 0x2000000
90 #define BIT_26 0x4000000
91 #define BIT_27 0x8000000
92 #define BIT_28 0x10000000
93 #define BIT_29 0x20000000
94 #define BIT_30 0x40000000
95 #define BIT_31 0x80000000
96
97 #define LSB(x) ((uint8_t)(x))
98 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
99
100 #define LSW(x) ((uint16_t)(x))
101 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
102
103 #define LSD(x) ((uint32_t)((uint64_t)(x)))
104 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
105
106 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
107
108 /*
109 * I/O register
110 */
111
112 #define RD_REG_BYTE(addr) readb(addr)
113 #define RD_REG_WORD(addr) readw(addr)
114 #define RD_REG_DWORD(addr) readl(addr)
115 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
116 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
117 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
118 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
119 #define WRT_REG_WORD(addr, data) writew(data,addr)
120 #define WRT_REG_DWORD(addr, data) writel(data,addr)
121
122 /*
123 * ISP83XX specific remote register addresses
124 */
125 #define QLA83XX_LED_PORT0 0x00201320
126 #define QLA83XX_LED_PORT1 0x00201328
127 #define QLA83XX_IDC_DEV_STATE 0x22102384
128 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
129 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
130 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
131 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
132 #define QLA83XX_IDC_CONTROL 0x22102390
133 #define QLA83XX_IDC_AUDIT 0x22102394
134 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
135 #define QLA83XX_DRIVER_LOCKID 0x22102104
136 #define QLA83XX_DRIVER_LOCK 0x8111c028
137 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
138 #define QLA83XX_FLASH_LOCKID 0x22102100
139 #define QLA83XX_FLASH_LOCK 0x8111c010
140 #define QLA83XX_FLASH_UNLOCK 0x8111c014
141 #define QLA83XX_DEV_PARTINFO1 0x221023e0
142 #define QLA83XX_DEV_PARTINFO2 0x221023e4
143 #define QLA83XX_FW_HEARTBEAT 0x221020b0
144 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
145 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
146
147 /* 83XX: Macros defining 8200 AEN Reason codes */
148 #define IDC_DEVICE_STATE_CHANGE BIT_0
149 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
150 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
151 #define IDC_HEARTBEAT_FAILURE BIT_3
152
153 /* 83XX: Macros defining 8200 AEN Error-levels */
154 #define ERR_LEVEL_NON_FATAL 0x1
155 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
156 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
157
158 /* 83XX: Macros for IDC Version */
159 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
160 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
161
162 /* 83XX: Macros for scheduling dpc tasks */
163 #define QLA83XX_NIC_CORE_RESET 0x1
164 #define QLA83XX_IDC_STATE_HANDLER 0x2
165 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
166
167 /* 83XX: Macros for defining IDC-Control bits */
168 #define QLA83XX_IDC_RESET_DISABLED BIT_0
169 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
170
171 /* 83XX: Macros for different timeouts */
172 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
173 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
174 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
175
176 /* 83XX: Macros for defining class in DEV-Partition Info register */
177 #define QLA83XX_CLASS_TYPE_NONE 0x0
178 #define QLA83XX_CLASS_TYPE_NIC 0x1
179 #define QLA83XX_CLASS_TYPE_FCOE 0x2
180 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
181
182 /* 83XX: Macros for IDC Lock-Recovery stages */
183 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
184 * lock-recovery
185 */
186 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
187
188 /* 83XX: Macros for IDC Audit type */
189 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
190 * dev-state change to NEED-RESET
191 * or NEED-QUIESCENT
192 */
193 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
194 * reset-recovery completion is
195 * second
196 */
197 /* ISP2031: Values for laser on/off */
198 #define PORT_0_2031 0x00201340
199 #define PORT_1_2031 0x00201350
200 #define LASER_ON_2031 0x01800100
201 #define LASER_OFF_2031 0x01800180
202
203 /*
204 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
205 * 133Mhz slot.
206 */
207 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
208 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
209
210 /*
211 * Fibre Channel device definitions.
212 */
213 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
214 #define MAX_FIBRE_DEVICES_2100 512
215 #define MAX_FIBRE_DEVICES_2400 2048
216 #define MAX_FIBRE_DEVICES_LOOP 128
217 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
218 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
219 #define MAX_FIBRE_LUNS 0xFFFF
220 #define MAX_HOST_COUNT 16
221
222 /*
223 * Host adapter default definitions.
224 */
225 #define MAX_BUSES 1 /* We only have one bus today */
226 #define MIN_LUNS 8
227 #define MAX_LUNS MAX_FIBRE_LUNS
228 #define MAX_CMDS_PER_LUN 255
229
230 /*
231 * Fibre Channel device definitions.
232 */
233 #define SNS_LAST_LOOP_ID_2100 0xfe
234 #define SNS_LAST_LOOP_ID_2300 0x7ff
235
236 #define LAST_LOCAL_LOOP_ID 0x7d
237 #define SNS_FL_PORT 0x7e
238 #define FABRIC_CONTROLLER 0x7f
239 #define SIMPLE_NAME_SERVER 0x80
240 #define SNS_FIRST_LOOP_ID 0x81
241 #define MANAGEMENT_SERVER 0xfe
242 #define BROADCAST 0xff
243
244 /*
245 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
246 * valid range of an N-PORT id is 0 through 0x7ef.
247 */
248 #define NPH_LAST_HANDLE 0x7ef
249 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
250 #define NPH_SNS 0x7fc /* FFFFFC */
251 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
252 #define NPH_F_PORT 0x7fe /* FFFFFE */
253 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
254
255 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
256 #include "qla_fw.h"
257
258 struct name_list_extended {
259 struct get_name_list_extended *l;
260 dma_addr_t ldma;
261 struct list_head fcports; /* protect by sess_list */
262 u32 size;
263 u8 sent;
264 };
265 /*
266 * Timeout timer counts in seconds
267 */
268 #define PORT_RETRY_TIME 1
269 #define LOOP_DOWN_TIMEOUT 60
270 #define LOOP_DOWN_TIME 255 /* 240 */
271 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
272
273 #define DEFAULT_OUTSTANDING_COMMANDS 4096
274 #define MIN_OUTSTANDING_COMMANDS 128
275
276 /* ISP request and response entry counts (37-65535) */
277 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
278 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
279 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
280 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
281 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
282 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
283 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
284 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
285 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
286 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
287 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */
288
289 struct req_que;
290 struct qla_tgt_sess;
291
292 /*
293 * SCSI Request Block
294 */
295 struct srb_cmd {
296 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
297 uint32_t request_sense_length;
298 uint32_t fw_sense_length;
299 uint8_t *request_sense_ptr;
300 void *ctx;
301 };
302
303 /*
304 * SRB flag definitions
305 */
306 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
307 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
308 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
309 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
310 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
311
312 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
313 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
314
315 struct els_logo_payload {
316 uint8_t opcode;
317 uint8_t rsvd[3];
318 uint8_t s_id[3];
319 uint8_t rsvd1[1];
320 uint8_t wwpn[WWN_SIZE];
321 };
322
323 struct ct_arg {
324 void *iocb;
325 u16 nport_handle;
326 dma_addr_t req_dma;
327 dma_addr_t rsp_dma;
328 u32 req_size;
329 u32 rsp_size;
330 void *req;
331 void *rsp;
332 };
333
334 /*
335 * SRB extensions.
336 */
337 struct srb_iocb {
338 union {
339 struct {
340 uint16_t flags;
341 #define SRB_LOGIN_RETRIED BIT_0
342 #define SRB_LOGIN_COND_PLOGI BIT_1
343 #define SRB_LOGIN_SKIP_PRLI BIT_2
344 uint16_t data[2];
345 u32 iop[2];
346 } logio;
347 struct {
348 #define ELS_DCMD_TIMEOUT 20
349 #define ELS_DCMD_LOGO 0x5
350 uint32_t flags;
351 uint32_t els_cmd;
352 struct completion comp;
353 struct els_logo_payload *els_logo_pyld;
354 dma_addr_t els_logo_pyld_dma;
355 } els_logo;
356 struct {
357 /*
358 * Values for flags field below are as
359 * defined in tsk_mgmt_entry struct
360 * for control_flags field in qla_fw.h.
361 */
362 uint64_t lun;
363 uint32_t flags;
364 uint32_t data;
365 struct completion comp;
366 __le16 comp_status;
367 } tmf;
368 struct {
369 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
370 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
371 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
372 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
373 #define FXDISC_TIMEOUT 20
374 uint8_t flags;
375 uint32_t req_len;
376 uint32_t rsp_len;
377 void *req_addr;
378 void *rsp_addr;
379 dma_addr_t req_dma_handle;
380 dma_addr_t rsp_dma_handle;
381 __le32 adapter_id;
382 __le32 adapter_id_hi;
383 __le16 req_func_type;
384 __le32 req_data;
385 __le32 req_data_extra;
386 __le32 result;
387 __le32 seq_number;
388 __le16 fw_flags;
389 struct completion fxiocb_comp;
390 __le32 reserved_0;
391 uint8_t reserved_1;
392 } fxiocb;
393 struct {
394 uint32_t cmd_hndl;
395 __le16 comp_status;
396 struct completion comp;
397 } abt;
398 struct ct_arg ctarg;
399 #define MAX_IOCB_MB_REG 28
400 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
401 struct {
402 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
403 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
404 void *out, *in;
405 dma_addr_t out_dma, in_dma;
406 struct completion comp;
407 int rc;
408 } mbx;
409 struct {
410 struct imm_ntfy_from_isp *ntfy;
411 } nack;
412 } u;
413
414 struct timer_list timer;
415 void (*timeout)(void *);
416 };
417
418 /* Values for srb_ctx type */
419 #define SRB_LOGIN_CMD 1
420 #define SRB_LOGOUT_CMD 2
421 #define SRB_ELS_CMD_RPT 3
422 #define SRB_ELS_CMD_HST 4
423 #define SRB_CT_CMD 5
424 #define SRB_ADISC_CMD 6
425 #define SRB_TM_CMD 7
426 #define SRB_SCSI_CMD 8
427 #define SRB_BIDI_CMD 9
428 #define SRB_FXIOCB_DCMD 10
429 #define SRB_FXIOCB_BCMD 11
430 #define SRB_ABT_CMD 12
431 #define SRB_ELS_DCMD 13
432 #define SRB_MB_IOCB 14
433 #define SRB_CT_PTHRU_CMD 15
434 #define SRB_NACK_PLOGI 16
435 #define SRB_NACK_PRLI 17
436 #define SRB_NACK_LOGO 18
437
438 typedef struct srb {
439 atomic_t ref_count;
440 struct fc_port *fcport;
441 struct scsi_qla_host *vha;
442 uint32_t handle;
443 uint16_t flags;
444 uint16_t type;
445 const char *name;
446 int iocbs;
447 struct qla_qpair *qpair;
448 u32 gen1; /* scratch */
449 u32 gen2; /* scratch */
450 union {
451 struct srb_iocb iocb_cmd;
452 struct bsg_job *bsg_job;
453 struct srb_cmd scmd;
454 } u;
455 void (*done)(void *, int);
456 void (*free)(void *);
457 } srb_t;
458
459 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
460 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
461 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
462
463 #define GET_CMD_SENSE_LEN(sp) \
464 (sp->u.scmd.request_sense_length)
465 #define SET_CMD_SENSE_LEN(sp, len) \
466 (sp->u.scmd.request_sense_length = len)
467 #define GET_CMD_SENSE_PTR(sp) \
468 (sp->u.scmd.request_sense_ptr)
469 #define SET_CMD_SENSE_PTR(sp, ptr) \
470 (sp->u.scmd.request_sense_ptr = ptr)
471 #define GET_FW_SENSE_LEN(sp) \
472 (sp->u.scmd.fw_sense_length)
473 #define SET_FW_SENSE_LEN(sp, len) \
474 (sp->u.scmd.fw_sense_length = len)
475
476 struct msg_echo_lb {
477 dma_addr_t send_dma;
478 dma_addr_t rcv_dma;
479 uint16_t req_sg_cnt;
480 uint16_t rsp_sg_cnt;
481 uint16_t options;
482 uint32_t transfer_size;
483 uint32_t iteration_count;
484 };
485
486 /*
487 * ISP I/O Register Set structure definitions.
488 */
489 struct device_reg_2xxx {
490 uint16_t flash_address; /* Flash BIOS address */
491 uint16_t flash_data; /* Flash BIOS data */
492 uint16_t unused_1[1]; /* Gap */
493 uint16_t ctrl_status; /* Control/Status */
494 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
495 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
496 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
497
498 uint16_t ictrl; /* Interrupt control */
499 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
500 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
501
502 uint16_t istatus; /* Interrupt status */
503 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
504
505 uint16_t semaphore; /* Semaphore */
506 uint16_t nvram; /* NVRAM register. */
507 #define NVR_DESELECT 0
508 #define NVR_BUSY BIT_15
509 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
510 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
511 #define NVR_DATA_IN BIT_3
512 #define NVR_DATA_OUT BIT_2
513 #define NVR_SELECT BIT_1
514 #define NVR_CLOCK BIT_0
515
516 #define NVR_WAIT_CNT 20000
517
518 union {
519 struct {
520 uint16_t mailbox0;
521 uint16_t mailbox1;
522 uint16_t mailbox2;
523 uint16_t mailbox3;
524 uint16_t mailbox4;
525 uint16_t mailbox5;
526 uint16_t mailbox6;
527 uint16_t mailbox7;
528 uint16_t unused_2[59]; /* Gap */
529 } __attribute__((packed)) isp2100;
530 struct {
531 /* Request Queue */
532 uint16_t req_q_in; /* In-Pointer */
533 uint16_t req_q_out; /* Out-Pointer */
534 /* Response Queue */
535 uint16_t rsp_q_in; /* In-Pointer */
536 uint16_t rsp_q_out; /* Out-Pointer */
537
538 /* RISC to Host Status */
539 uint32_t host_status;
540 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
541 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
542
543 /* Host to Host Semaphore */
544 uint16_t host_semaphore;
545 uint16_t unused_3[17]; /* Gap */
546 uint16_t mailbox0;
547 uint16_t mailbox1;
548 uint16_t mailbox2;
549 uint16_t mailbox3;
550 uint16_t mailbox4;
551 uint16_t mailbox5;
552 uint16_t mailbox6;
553 uint16_t mailbox7;
554 uint16_t mailbox8;
555 uint16_t mailbox9;
556 uint16_t mailbox10;
557 uint16_t mailbox11;
558 uint16_t mailbox12;
559 uint16_t mailbox13;
560 uint16_t mailbox14;
561 uint16_t mailbox15;
562 uint16_t mailbox16;
563 uint16_t mailbox17;
564 uint16_t mailbox18;
565 uint16_t mailbox19;
566 uint16_t mailbox20;
567 uint16_t mailbox21;
568 uint16_t mailbox22;
569 uint16_t mailbox23;
570 uint16_t mailbox24;
571 uint16_t mailbox25;
572 uint16_t mailbox26;
573 uint16_t mailbox27;
574 uint16_t mailbox28;
575 uint16_t mailbox29;
576 uint16_t mailbox30;
577 uint16_t mailbox31;
578 uint16_t fb_cmd;
579 uint16_t unused_4[10]; /* Gap */
580 } __attribute__((packed)) isp2300;
581 } u;
582
583 uint16_t fpm_diag_config;
584 uint16_t unused_5[0x4]; /* Gap */
585 uint16_t risc_hw;
586 uint16_t unused_5_1; /* Gap */
587 uint16_t pcr; /* Processor Control Register. */
588 uint16_t unused_6[0x5]; /* Gap */
589 uint16_t mctr; /* Memory Configuration and Timing. */
590 uint16_t unused_7[0x3]; /* Gap */
591 uint16_t fb_cmd_2100; /* Unused on 23XX */
592 uint16_t unused_8[0x3]; /* Gap */
593 uint16_t hccr; /* Host command & control register. */
594 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
595 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
596 /* HCCR commands */
597 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
598 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
599 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
600 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
601 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
602 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
603 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
604 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
605
606 uint16_t unused_9[5]; /* Gap */
607 uint16_t gpiod; /* GPIO Data register. */
608 uint16_t gpioe; /* GPIO Enable register. */
609 #define GPIO_LED_MASK 0x00C0
610 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
611 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
612 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
613 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
614 #define GPIO_LED_ALL_OFF 0x0000
615 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
616 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
617
618 union {
619 struct {
620 uint16_t unused_10[8]; /* Gap */
621 uint16_t mailbox8;
622 uint16_t mailbox9;
623 uint16_t mailbox10;
624 uint16_t mailbox11;
625 uint16_t mailbox12;
626 uint16_t mailbox13;
627 uint16_t mailbox14;
628 uint16_t mailbox15;
629 uint16_t mailbox16;
630 uint16_t mailbox17;
631 uint16_t mailbox18;
632 uint16_t mailbox19;
633 uint16_t mailbox20;
634 uint16_t mailbox21;
635 uint16_t mailbox22;
636 uint16_t mailbox23; /* Also probe reg. */
637 } __attribute__((packed)) isp2200;
638 } u_end;
639 };
640
641 struct device_reg_25xxmq {
642 uint32_t req_q_in;
643 uint32_t req_q_out;
644 uint32_t rsp_q_in;
645 uint32_t rsp_q_out;
646 uint32_t atio_q_in;
647 uint32_t atio_q_out;
648 };
649
650
651 struct device_reg_fx00 {
652 uint32_t mailbox0; /* 00 */
653 uint32_t mailbox1; /* 04 */
654 uint32_t mailbox2; /* 08 */
655 uint32_t mailbox3; /* 0C */
656 uint32_t mailbox4; /* 10 */
657 uint32_t mailbox5; /* 14 */
658 uint32_t mailbox6; /* 18 */
659 uint32_t mailbox7; /* 1C */
660 uint32_t mailbox8; /* 20 */
661 uint32_t mailbox9; /* 24 */
662 uint32_t mailbox10; /* 28 */
663 uint32_t mailbox11;
664 uint32_t mailbox12;
665 uint32_t mailbox13;
666 uint32_t mailbox14;
667 uint32_t mailbox15;
668 uint32_t mailbox16;
669 uint32_t mailbox17;
670 uint32_t mailbox18;
671 uint32_t mailbox19;
672 uint32_t mailbox20;
673 uint32_t mailbox21;
674 uint32_t mailbox22;
675 uint32_t mailbox23;
676 uint32_t mailbox24;
677 uint32_t mailbox25;
678 uint32_t mailbox26;
679 uint32_t mailbox27;
680 uint32_t mailbox28;
681 uint32_t mailbox29;
682 uint32_t mailbox30;
683 uint32_t mailbox31;
684 uint32_t aenmailbox0;
685 uint32_t aenmailbox1;
686 uint32_t aenmailbox2;
687 uint32_t aenmailbox3;
688 uint32_t aenmailbox4;
689 uint32_t aenmailbox5;
690 uint32_t aenmailbox6;
691 uint32_t aenmailbox7;
692 /* Request Queue. */
693 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
694 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
695 /* Response Queue. */
696 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
697 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
698 /* Init values shadowed on FW Up Event */
699 uint32_t initval0; /* B0 */
700 uint32_t initval1; /* B4 */
701 uint32_t initval2; /* B8 */
702 uint32_t initval3; /* BC */
703 uint32_t initval4; /* C0 */
704 uint32_t initval5; /* C4 */
705 uint32_t initval6; /* C8 */
706 uint32_t initval7; /* CC */
707 uint32_t fwheartbeat; /* D0 */
708 uint32_t pseudoaen; /* D4 */
709 };
710
711
712
713 typedef union {
714 struct device_reg_2xxx isp;
715 struct device_reg_24xx isp24;
716 struct device_reg_25xxmq isp25mq;
717 struct device_reg_82xx isp82;
718 struct device_reg_fx00 ispfx00;
719 } __iomem device_reg_t;
720
721 #define ISP_REQ_Q_IN(ha, reg) \
722 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
723 &(reg)->u.isp2100.mailbox4 : \
724 &(reg)->u.isp2300.req_q_in)
725 #define ISP_REQ_Q_OUT(ha, reg) \
726 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
727 &(reg)->u.isp2100.mailbox4 : \
728 &(reg)->u.isp2300.req_q_out)
729 #define ISP_RSP_Q_IN(ha, reg) \
730 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
731 &(reg)->u.isp2100.mailbox5 : \
732 &(reg)->u.isp2300.rsp_q_in)
733 #define ISP_RSP_Q_OUT(ha, reg) \
734 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
735 &(reg)->u.isp2100.mailbox5 : \
736 &(reg)->u.isp2300.rsp_q_out)
737
738 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
739 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
740
741 #define MAILBOX_REG(ha, reg, num) \
742 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
743 (num < 8 ? \
744 &(reg)->u.isp2100.mailbox0 + (num) : \
745 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
746 &(reg)->u.isp2300.mailbox0 + (num))
747 #define RD_MAILBOX_REG(ha, reg, num) \
748 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
749 #define WRT_MAILBOX_REG(ha, reg, num, data) \
750 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
751
752 #define FB_CMD_REG(ha, reg) \
753 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
754 &(reg)->fb_cmd_2100 : \
755 &(reg)->u.isp2300.fb_cmd)
756 #define RD_FB_CMD_REG(ha, reg) \
757 RD_REG_WORD(FB_CMD_REG(ha, reg))
758 #define WRT_FB_CMD_REG(ha, reg, data) \
759 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
760
761 typedef struct {
762 uint32_t out_mb; /* outbound from driver */
763 uint32_t in_mb; /* Incoming from RISC */
764 uint16_t mb[MAILBOX_REGISTER_COUNT];
765 long buf_size;
766 void *bufp;
767 uint32_t tov;
768 uint8_t flags;
769 #define MBX_DMA_IN BIT_0
770 #define MBX_DMA_OUT BIT_1
771 #define IOCTL_CMD BIT_2
772 } mbx_cmd_t;
773
774 struct mbx_cmd_32 {
775 uint32_t out_mb; /* outbound from driver */
776 uint32_t in_mb; /* Incoming from RISC */
777 uint32_t mb[MAILBOX_REGISTER_COUNT];
778 long buf_size;
779 void *bufp;
780 uint32_t tov;
781 uint8_t flags;
782 #define MBX_DMA_IN BIT_0
783 #define MBX_DMA_OUT BIT_1
784 #define IOCTL_CMD BIT_2
785 };
786
787
788 #define MBX_TOV_SECONDS 30
789
790 /*
791 * ISP product identification definitions in mailboxes after reset.
792 */
793 #define PROD_ID_1 0x4953
794 #define PROD_ID_2 0x0000
795 #define PROD_ID_2a 0x5020
796 #define PROD_ID_3 0x2020
797
798 /*
799 * ISP mailbox Self-Test status codes
800 */
801 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
802 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
803 #define MBS_BUSY 4 /* Busy. */
804
805 /*
806 * ISP mailbox command complete status codes
807 */
808 #define MBS_COMMAND_COMPLETE 0x4000
809 #define MBS_INVALID_COMMAND 0x4001
810 #define MBS_HOST_INTERFACE_ERROR 0x4002
811 #define MBS_TEST_FAILED 0x4003
812 #define MBS_COMMAND_ERROR 0x4005
813 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
814 #define MBS_PORT_ID_USED 0x4007
815 #define MBS_LOOP_ID_USED 0x4008
816 #define MBS_ALL_IDS_IN_USE 0x4009
817 #define MBS_NOT_LOGGED_IN 0x400A
818 #define MBS_LINK_DOWN_ERROR 0x400B
819 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
820
821 /*
822 * ISP mailbox asynchronous event status codes
823 */
824 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
825 #define MBA_RESET 0x8001 /* Reset Detected. */
826 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
827 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
828 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
829 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
830 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
831 /* occurred. */
832 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
833 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
834 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
835 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
836 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
837 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
838 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
839 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
840 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
841 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
842 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
843 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
844 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
845 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
846 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
847 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
848 /* used. */
849 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
850 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
851 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
852 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
853 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
854 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
855 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
856 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
857 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
858 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
859 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
860 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
861 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
862 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
863 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
864 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
865 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
866 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
867 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
868 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
869 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
870 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
871 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
872 Notification */
873 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
874 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
875 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
876 /* 83XX FCoE specific */
877 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
878
879 /* Interrupt type codes */
880 #define INTR_ROM_MB_SUCCESS 0x1
881 #define INTR_ROM_MB_FAILED 0x2
882 #define INTR_MB_SUCCESS 0x10
883 #define INTR_MB_FAILED 0x11
884 #define INTR_ASYNC_EVENT 0x12
885 #define INTR_RSP_QUE_UPDATE 0x13
886 #define INTR_RSP_QUE_UPDATE_83XX 0x14
887 #define INTR_ATIO_QUE_UPDATE 0x1C
888 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
889
890 /* ISP mailbox loopback echo diagnostic error code */
891 #define MBS_LB_RESET 0x17
892 /*
893 * Firmware options 1, 2, 3.
894 */
895 #define FO1_AE_ON_LIPF8 BIT_0
896 #define FO1_AE_ALL_LIP_RESET BIT_1
897 #define FO1_CTIO_RETRY BIT_3
898 #define FO1_DISABLE_LIP_F7_SW BIT_4
899 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
900 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
901 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
902 #define FO1_SET_EMPHASIS_SWING BIT_8
903 #define FO1_AE_AUTO_BYPASS BIT_9
904 #define FO1_ENABLE_PURE_IOCB BIT_10
905 #define FO1_AE_PLOGI_RJT BIT_11
906 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
907 #define FO1_AE_QUEUE_FULL BIT_13
908
909 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
910 #define FO2_REV_LOOPBACK BIT_1
911
912 #define FO3_ENABLE_EMERG_IOCB BIT_0
913 #define FO3_AE_RND_ERROR BIT_1
914
915 /* 24XX additional firmware options */
916 #define ADD_FO_COUNT 3
917 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
918 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
919
920 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
921
922 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
923
924 /*
925 * ISP mailbox commands
926 */
927 #define MBC_LOAD_RAM 1 /* Load RAM. */
928 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
929 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
930 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
931 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
932 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
933 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
934 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
935 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
936 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
937 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
938 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
939 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
940 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
941 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
942 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
943 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
944 #define MBC_RESET 0x18 /* Reset. */
945 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
946 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
947 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
948 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
949 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
950 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
951 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
952 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
953 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
954 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
955 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
956 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
957 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
958 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
959 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
960 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
961 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
962 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
963 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
964 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
965 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
966 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
967 #define MBC_DATA_RATE 0x5d /* Data Rate */
968 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
969 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
970 /* Initialization Procedure */
971 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
972 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
973 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
974 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
975 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
976 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
977 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
978 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
979 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
980 #define MBC_LIP_RESET 0x6c /* LIP reset. */
981 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
982 /* commandd. */
983 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
984 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
985 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
986 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
987 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
988 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
989 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
990 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
991 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
992 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
993 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
994
995 /*
996 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
997 * should be defined with MBC_MR_*
998 */
999 #define MBC_MR_DRV_SHUTDOWN 0x6A
1000
1001 /*
1002 * ISP24xx mailbox commands
1003 */
1004 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1005 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1006 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1007 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1008 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1009 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1010 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1011 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1012 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1013 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1014 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1015 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1016 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1017 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1018 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1019 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1020 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1021 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1022 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1023 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1024 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1025 #define MBC_PORT_RESET 0x120 /* Port Reset */
1026 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1027 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1028
1029 /*
1030 * ISP81xx mailbox commands
1031 */
1032 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1033
1034 /*
1035 * ISP8044 mailbox commands
1036 */
1037 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1038 #define HCS_WRITE_SERDES 0x3
1039 #define HCS_READ_SERDES 0x4
1040
1041 /* Firmware return data sizes */
1042 #define FCAL_MAP_SIZE 128
1043
1044 /* Mailbox bit definitions for out_mb and in_mb */
1045 #define MBX_31 BIT_31
1046 #define MBX_30 BIT_30
1047 #define MBX_29 BIT_29
1048 #define MBX_28 BIT_28
1049 #define MBX_27 BIT_27
1050 #define MBX_26 BIT_26
1051 #define MBX_25 BIT_25
1052 #define MBX_24 BIT_24
1053 #define MBX_23 BIT_23
1054 #define MBX_22 BIT_22
1055 #define MBX_21 BIT_21
1056 #define MBX_20 BIT_20
1057 #define MBX_19 BIT_19
1058 #define MBX_18 BIT_18
1059 #define MBX_17 BIT_17
1060 #define MBX_16 BIT_16
1061 #define MBX_15 BIT_15
1062 #define MBX_14 BIT_14
1063 #define MBX_13 BIT_13
1064 #define MBX_12 BIT_12
1065 #define MBX_11 BIT_11
1066 #define MBX_10 BIT_10
1067 #define MBX_9 BIT_9
1068 #define MBX_8 BIT_8
1069 #define MBX_7 BIT_7
1070 #define MBX_6 BIT_6
1071 #define MBX_5 BIT_5
1072 #define MBX_4 BIT_4
1073 #define MBX_3 BIT_3
1074 #define MBX_2 BIT_2
1075 #define MBX_1 BIT_1
1076 #define MBX_0 BIT_0
1077
1078 #define RNID_TYPE_SET_VERSION 0x9
1079 #define RNID_TYPE_ASIC_TEMP 0xC
1080
1081 /*
1082 * Firmware state codes from get firmware state mailbox command
1083 */
1084 #define FSTATE_CONFIG_WAIT 0
1085 #define FSTATE_WAIT_AL_PA 1
1086 #define FSTATE_WAIT_LOGIN 2
1087 #define FSTATE_READY 3
1088 #define FSTATE_LOSS_OF_SYNC 4
1089 #define FSTATE_ERROR 5
1090 #define FSTATE_REINIT 6
1091 #define FSTATE_NON_PART 7
1092
1093 #define FSTATE_CONFIG_CORRECT 0
1094 #define FSTATE_P2P_RCV_LIP 1
1095 #define FSTATE_P2P_CHOOSE_LOOP 2
1096 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1097 #define FSTATE_FATAL_ERROR 4
1098 #define FSTATE_LOOP_BACK_CONN 5
1099
1100 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1101 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1102 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1103 #define QLA27XX_PRIMARY_IMAGE 1
1104 #define QLA27XX_SECONDARY_IMAGE 2
1105
1106 /*
1107 * Port Database structure definition
1108 * Little endian except where noted.
1109 */
1110 #define PORT_DATABASE_SIZE 128 /* bytes */
1111 typedef struct {
1112 uint8_t options;
1113 uint8_t control;
1114 uint8_t master_state;
1115 uint8_t slave_state;
1116 uint8_t reserved[2];
1117 uint8_t hard_address;
1118 uint8_t reserved_1;
1119 uint8_t port_id[4];
1120 uint8_t node_name[WWN_SIZE];
1121 uint8_t port_name[WWN_SIZE];
1122 uint16_t execution_throttle;
1123 uint16_t execution_count;
1124 uint8_t reset_count;
1125 uint8_t reserved_2;
1126 uint16_t resource_allocation;
1127 uint16_t current_allocation;
1128 uint16_t queue_head;
1129 uint16_t queue_tail;
1130 uint16_t transmit_execution_list_next;
1131 uint16_t transmit_execution_list_previous;
1132 uint16_t common_features;
1133 uint16_t total_concurrent_sequences;
1134 uint16_t RO_by_information_category;
1135 uint8_t recipient;
1136 uint8_t initiator;
1137 uint16_t receive_data_size;
1138 uint16_t concurrent_sequences;
1139 uint16_t open_sequences_per_exchange;
1140 uint16_t lun_abort_flags;
1141 uint16_t lun_stop_flags;
1142 uint16_t stop_queue_head;
1143 uint16_t stop_queue_tail;
1144 uint16_t port_retry_timer;
1145 uint16_t next_sequence_id;
1146 uint16_t frame_count;
1147 uint16_t PRLI_payload_length;
1148 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1149 /* Bits 15-0 of word 0 */
1150 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1151 /* Bits 15-0 of word 3 */
1152 uint16_t loop_id;
1153 uint16_t extended_lun_info_list_pointer;
1154 uint16_t extended_lun_stop_list_pointer;
1155 } port_database_t;
1156
1157 /*
1158 * Port database slave/master states
1159 */
1160 #define PD_STATE_DISCOVERY 0
1161 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1162 #define PD_STATE_PORT_LOGIN 2
1163 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1164 #define PD_STATE_PROCESS_LOGIN 4
1165 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1166 #define PD_STATE_PORT_LOGGED_IN 6
1167 #define PD_STATE_PORT_UNAVAILABLE 7
1168 #define PD_STATE_PROCESS_LOGOUT 8
1169 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1170 #define PD_STATE_PORT_LOGOUT 10
1171 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1172
1173
1174 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1175 #define QLA_ZIO_DISABLED 0
1176 #define QLA_ZIO_DEFAULT_TIMER 2
1177
1178 /*
1179 * ISP Initialization Control Block.
1180 * Little endian except where noted.
1181 */
1182 #define ICB_VERSION 1
1183 typedef struct {
1184 uint8_t version;
1185 uint8_t reserved_1;
1186
1187 /*
1188 * LSB BIT 0 = Enable Hard Loop Id
1189 * LSB BIT 1 = Enable Fairness
1190 * LSB BIT 2 = Enable Full-Duplex
1191 * LSB BIT 3 = Enable Fast Posting
1192 * LSB BIT 4 = Enable Target Mode
1193 * LSB BIT 5 = Disable Initiator Mode
1194 * LSB BIT 6 = Enable ADISC
1195 * LSB BIT 7 = Enable Target Inquiry Data
1196 *
1197 * MSB BIT 0 = Enable PDBC Notify
1198 * MSB BIT 1 = Non Participating LIP
1199 * MSB BIT 2 = Descending Loop ID Search
1200 * MSB BIT 3 = Acquire Loop ID in LIPA
1201 * MSB BIT 4 = Stop PortQ on Full Status
1202 * MSB BIT 5 = Full Login after LIP
1203 * MSB BIT 6 = Node Name Option
1204 * MSB BIT 7 = Ext IFWCB enable bit
1205 */
1206 uint8_t firmware_options[2];
1207
1208 uint16_t frame_payload_size;
1209 uint16_t max_iocb_allocation;
1210 uint16_t execution_throttle;
1211 uint8_t retry_count;
1212 uint8_t retry_delay; /* unused */
1213 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1214 uint16_t hard_address;
1215 uint8_t inquiry_data;
1216 uint8_t login_timeout;
1217 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1218
1219 uint16_t request_q_outpointer;
1220 uint16_t response_q_inpointer;
1221 uint16_t request_q_length;
1222 uint16_t response_q_length;
1223 uint32_t request_q_address[2];
1224 uint32_t response_q_address[2];
1225
1226 uint16_t lun_enables;
1227 uint8_t command_resource_count;
1228 uint8_t immediate_notify_resource_count;
1229 uint16_t timeout;
1230 uint8_t reserved_2[2];
1231
1232 /*
1233 * LSB BIT 0 = Timer Operation mode bit 0
1234 * LSB BIT 1 = Timer Operation mode bit 1
1235 * LSB BIT 2 = Timer Operation mode bit 2
1236 * LSB BIT 3 = Timer Operation mode bit 3
1237 * LSB BIT 4 = Init Config Mode bit 0
1238 * LSB BIT 5 = Init Config Mode bit 1
1239 * LSB BIT 6 = Init Config Mode bit 2
1240 * LSB BIT 7 = Enable Non part on LIHA failure
1241 *
1242 * MSB BIT 0 = Enable class 2
1243 * MSB BIT 1 = Enable ACK0
1244 * MSB BIT 2 =
1245 * MSB BIT 3 =
1246 * MSB BIT 4 = FC Tape Enable
1247 * MSB BIT 5 = Enable FC Confirm
1248 * MSB BIT 6 = Enable command queuing in target mode
1249 * MSB BIT 7 = No Logo On Link Down
1250 */
1251 uint8_t add_firmware_options[2];
1252
1253 uint8_t response_accumulation_timer;
1254 uint8_t interrupt_delay_timer;
1255
1256 /*
1257 * LSB BIT 0 = Enable Read xfr_rdy
1258 * LSB BIT 1 = Soft ID only
1259 * LSB BIT 2 =
1260 * LSB BIT 3 =
1261 * LSB BIT 4 = FCP RSP Payload [0]
1262 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1263 * LSB BIT 6 = Enable Out-of-Order frame handling
1264 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1265 *
1266 * MSB BIT 0 = Sbus enable - 2300
1267 * MSB BIT 1 =
1268 * MSB BIT 2 =
1269 * MSB BIT 3 =
1270 * MSB BIT 4 = LED mode
1271 * MSB BIT 5 = enable 50 ohm termination
1272 * MSB BIT 6 = Data Rate (2300 only)
1273 * MSB BIT 7 = Data Rate (2300 only)
1274 */
1275 uint8_t special_options[2];
1276
1277 uint8_t reserved_3[26];
1278 } init_cb_t;
1279
1280 /*
1281 * Get Link Status mailbox command return buffer.
1282 */
1283 #define GLSO_SEND_RPS BIT_0
1284 #define GLSO_USE_DID BIT_3
1285
1286 struct link_statistics {
1287 uint32_t link_fail_cnt;
1288 uint32_t loss_sync_cnt;
1289 uint32_t loss_sig_cnt;
1290 uint32_t prim_seq_err_cnt;
1291 uint32_t inval_xmit_word_cnt;
1292 uint32_t inval_crc_cnt;
1293 uint32_t lip_cnt;
1294 uint32_t link_up_cnt;
1295 uint32_t link_down_loop_init_tmo;
1296 uint32_t link_down_los;
1297 uint32_t link_down_loss_rcv_clk;
1298 uint32_t reserved0[5];
1299 uint32_t port_cfg_chg;
1300 uint32_t reserved1[11];
1301 uint32_t rsp_q_full;
1302 uint32_t atio_q_full;
1303 uint32_t drop_ae;
1304 uint32_t els_proto_err;
1305 uint32_t reserved2;
1306 uint32_t tx_frames;
1307 uint32_t rx_frames;
1308 uint32_t discarded_frames;
1309 uint32_t dropped_frames;
1310 uint32_t reserved3;
1311 uint32_t nos_rcvd;
1312 uint32_t reserved4[4];
1313 uint32_t tx_prjt;
1314 uint32_t rcv_exfail;
1315 uint32_t rcv_abts;
1316 uint32_t seq_frm_miss;
1317 uint32_t corr_err;
1318 uint32_t mb_rqst;
1319 uint32_t nport_full;
1320 uint32_t eofa;
1321 uint32_t reserved5;
1322 uint32_t fpm_recv_word_cnt_lo;
1323 uint32_t fpm_recv_word_cnt_hi;
1324 uint32_t fpm_disc_word_cnt_lo;
1325 uint32_t fpm_disc_word_cnt_hi;
1326 uint32_t fpm_xmit_word_cnt_lo;
1327 uint32_t fpm_xmit_word_cnt_hi;
1328 uint32_t reserved6[70];
1329 };
1330
1331 /*
1332 * NVRAM Command values.
1333 */
1334 #define NV_START_BIT BIT_2
1335 #define NV_WRITE_OP (BIT_26+BIT_24)
1336 #define NV_READ_OP (BIT_26+BIT_25)
1337 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1338 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1339 #define NV_DELAY_COUNT 10
1340
1341 /*
1342 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1343 */
1344 typedef struct {
1345 /*
1346 * NVRAM header
1347 */
1348 uint8_t id[4];
1349 uint8_t nvram_version;
1350 uint8_t reserved_0;
1351
1352 /*
1353 * NVRAM RISC parameter block
1354 */
1355 uint8_t parameter_block_version;
1356 uint8_t reserved_1;
1357
1358 /*
1359 * LSB BIT 0 = Enable Hard Loop Id
1360 * LSB BIT 1 = Enable Fairness
1361 * LSB BIT 2 = Enable Full-Duplex
1362 * LSB BIT 3 = Enable Fast Posting
1363 * LSB BIT 4 = Enable Target Mode
1364 * LSB BIT 5 = Disable Initiator Mode
1365 * LSB BIT 6 = Enable ADISC
1366 * LSB BIT 7 = Enable Target Inquiry Data
1367 *
1368 * MSB BIT 0 = Enable PDBC Notify
1369 * MSB BIT 1 = Non Participating LIP
1370 * MSB BIT 2 = Descending Loop ID Search
1371 * MSB BIT 3 = Acquire Loop ID in LIPA
1372 * MSB BIT 4 = Stop PortQ on Full Status
1373 * MSB BIT 5 = Full Login after LIP
1374 * MSB BIT 6 = Node Name Option
1375 * MSB BIT 7 = Ext IFWCB enable bit
1376 */
1377 uint8_t firmware_options[2];
1378
1379 uint16_t frame_payload_size;
1380 uint16_t max_iocb_allocation;
1381 uint16_t execution_throttle;
1382 uint8_t retry_count;
1383 uint8_t retry_delay; /* unused */
1384 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1385 uint16_t hard_address;
1386 uint8_t inquiry_data;
1387 uint8_t login_timeout;
1388 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1389
1390 /*
1391 * LSB BIT 0 = Timer Operation mode bit 0
1392 * LSB BIT 1 = Timer Operation mode bit 1
1393 * LSB BIT 2 = Timer Operation mode bit 2
1394 * LSB BIT 3 = Timer Operation mode bit 3
1395 * LSB BIT 4 = Init Config Mode bit 0
1396 * LSB BIT 5 = Init Config Mode bit 1
1397 * LSB BIT 6 = Init Config Mode bit 2
1398 * LSB BIT 7 = Enable Non part on LIHA failure
1399 *
1400 * MSB BIT 0 = Enable class 2
1401 * MSB BIT 1 = Enable ACK0
1402 * MSB BIT 2 =
1403 * MSB BIT 3 =
1404 * MSB BIT 4 = FC Tape Enable
1405 * MSB BIT 5 = Enable FC Confirm
1406 * MSB BIT 6 = Enable command queuing in target mode
1407 * MSB BIT 7 = No Logo On Link Down
1408 */
1409 uint8_t add_firmware_options[2];
1410
1411 uint8_t response_accumulation_timer;
1412 uint8_t interrupt_delay_timer;
1413
1414 /*
1415 * LSB BIT 0 = Enable Read xfr_rdy
1416 * LSB BIT 1 = Soft ID only
1417 * LSB BIT 2 =
1418 * LSB BIT 3 =
1419 * LSB BIT 4 = FCP RSP Payload [0]
1420 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1421 * LSB BIT 6 = Enable Out-of-Order frame handling
1422 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1423 *
1424 * MSB BIT 0 = Sbus enable - 2300
1425 * MSB BIT 1 =
1426 * MSB BIT 2 =
1427 * MSB BIT 3 =
1428 * MSB BIT 4 = LED mode
1429 * MSB BIT 5 = enable 50 ohm termination
1430 * MSB BIT 6 = Data Rate (2300 only)
1431 * MSB BIT 7 = Data Rate (2300 only)
1432 */
1433 uint8_t special_options[2];
1434
1435 /* Reserved for expanded RISC parameter block */
1436 uint8_t reserved_2[22];
1437
1438 /*
1439 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1440 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1441 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1442 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1443 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1444 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1445 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1446 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1447 *
1448 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1449 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1450 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1451 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1452 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1453 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1454 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1455 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1456 *
1457 * LSB BIT 0 = Output Swing 1G bit 0
1458 * LSB BIT 1 = Output Swing 1G bit 1
1459 * LSB BIT 2 = Output Swing 1G bit 2
1460 * LSB BIT 3 = Output Emphasis 1G bit 0
1461 * LSB BIT 4 = Output Emphasis 1G bit 1
1462 * LSB BIT 5 = Output Swing 2G bit 0
1463 * LSB BIT 6 = Output Swing 2G bit 1
1464 * LSB BIT 7 = Output Swing 2G bit 2
1465 *
1466 * MSB BIT 0 = Output Emphasis 2G bit 0
1467 * MSB BIT 1 = Output Emphasis 2G bit 1
1468 * MSB BIT 2 = Output Enable
1469 * MSB BIT 3 =
1470 * MSB BIT 4 =
1471 * MSB BIT 5 =
1472 * MSB BIT 6 =
1473 * MSB BIT 7 =
1474 */
1475 uint8_t seriallink_options[4];
1476
1477 /*
1478 * NVRAM host parameter block
1479 *
1480 * LSB BIT 0 = Enable spinup delay
1481 * LSB BIT 1 = Disable BIOS
1482 * LSB BIT 2 = Enable Memory Map BIOS
1483 * LSB BIT 3 = Enable Selectable Boot
1484 * LSB BIT 4 = Disable RISC code load
1485 * LSB BIT 5 = Set cache line size 1
1486 * LSB BIT 6 = PCI Parity Disable
1487 * LSB BIT 7 = Enable extended logging
1488 *
1489 * MSB BIT 0 = Enable 64bit addressing
1490 * MSB BIT 1 = Enable lip reset
1491 * MSB BIT 2 = Enable lip full login
1492 * MSB BIT 3 = Enable target reset
1493 * MSB BIT 4 = Enable database storage
1494 * MSB BIT 5 = Enable cache flush read
1495 * MSB BIT 6 = Enable database load
1496 * MSB BIT 7 = Enable alternate WWN
1497 */
1498 uint8_t host_p[2];
1499
1500 uint8_t boot_node_name[WWN_SIZE];
1501 uint8_t boot_lun_number;
1502 uint8_t reset_delay;
1503 uint8_t port_down_retry_count;
1504 uint8_t boot_id_number;
1505 uint16_t max_luns_per_target;
1506 uint8_t fcode_boot_port_name[WWN_SIZE];
1507 uint8_t alternate_port_name[WWN_SIZE];
1508 uint8_t alternate_node_name[WWN_SIZE];
1509
1510 /*
1511 * BIT 0 = Selective Login
1512 * BIT 1 = Alt-Boot Enable
1513 * BIT 2 =
1514 * BIT 3 = Boot Order List
1515 * BIT 4 =
1516 * BIT 5 = Selective LUN
1517 * BIT 6 =
1518 * BIT 7 = unused
1519 */
1520 uint8_t efi_parameters;
1521
1522 uint8_t link_down_timeout;
1523
1524 uint8_t adapter_id[16];
1525
1526 uint8_t alt1_boot_node_name[WWN_SIZE];
1527 uint16_t alt1_boot_lun_number;
1528 uint8_t alt2_boot_node_name[WWN_SIZE];
1529 uint16_t alt2_boot_lun_number;
1530 uint8_t alt3_boot_node_name[WWN_SIZE];
1531 uint16_t alt3_boot_lun_number;
1532 uint8_t alt4_boot_node_name[WWN_SIZE];
1533 uint16_t alt4_boot_lun_number;
1534 uint8_t alt5_boot_node_name[WWN_SIZE];
1535 uint16_t alt5_boot_lun_number;
1536 uint8_t alt6_boot_node_name[WWN_SIZE];
1537 uint16_t alt6_boot_lun_number;
1538 uint8_t alt7_boot_node_name[WWN_SIZE];
1539 uint16_t alt7_boot_lun_number;
1540
1541 uint8_t reserved_3[2];
1542
1543 /* Offset 200-215 : Model Number */
1544 uint8_t model_number[16];
1545
1546 /* OEM related items */
1547 uint8_t oem_specific[16];
1548
1549 /*
1550 * NVRAM Adapter Features offset 232-239
1551 *
1552 * LSB BIT 0 = External GBIC
1553 * LSB BIT 1 = Risc RAM parity
1554 * LSB BIT 2 = Buffer Plus Module
1555 * LSB BIT 3 = Multi Chip Adapter
1556 * LSB BIT 4 = Internal connector
1557 * LSB BIT 5 =
1558 * LSB BIT 6 =
1559 * LSB BIT 7 =
1560 *
1561 * MSB BIT 0 =
1562 * MSB BIT 1 =
1563 * MSB BIT 2 =
1564 * MSB BIT 3 =
1565 * MSB BIT 4 =
1566 * MSB BIT 5 =
1567 * MSB BIT 6 =
1568 * MSB BIT 7 =
1569 */
1570 uint8_t adapter_features[2];
1571
1572 uint8_t reserved_4[16];
1573
1574 /* Subsystem vendor ID for ISP2200 */
1575 uint16_t subsystem_vendor_id_2200;
1576
1577 /* Subsystem device ID for ISP2200 */
1578 uint16_t subsystem_device_id_2200;
1579
1580 uint8_t reserved_5;
1581 uint8_t checksum;
1582 } nvram_t;
1583
1584 /*
1585 * ISP queue - response queue entry definition.
1586 */
1587 typedef struct {
1588 uint8_t entry_type; /* Entry type. */
1589 uint8_t entry_count; /* Entry count. */
1590 uint8_t sys_define; /* System defined. */
1591 uint8_t entry_status; /* Entry Status. */
1592 uint32_t handle; /* System defined handle */
1593 uint8_t data[52];
1594 uint32_t signature;
1595 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1596 } response_t;
1597
1598 /*
1599 * ISP queue - ATIO queue entry definition.
1600 */
1601 struct atio {
1602 uint8_t entry_type; /* Entry type. */
1603 uint8_t entry_count; /* Entry count. */
1604 __le16 attr_n_length;
1605 uint8_t data[56];
1606 uint32_t signature;
1607 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1608 };
1609
1610 typedef union {
1611 uint16_t extended;
1612 struct {
1613 uint8_t reserved;
1614 uint8_t standard;
1615 } id;
1616 } target_id_t;
1617
1618 #define SET_TARGET_ID(ha, to, from) \
1619 do { \
1620 if (HAS_EXTENDED_IDS(ha)) \
1621 to.extended = cpu_to_le16(from); \
1622 else \
1623 to.id.standard = (uint8_t)from; \
1624 } while (0)
1625
1626 /*
1627 * ISP queue - command entry structure definition.
1628 */
1629 #define COMMAND_TYPE 0x11 /* Command entry */
1630 typedef struct {
1631 uint8_t entry_type; /* Entry type. */
1632 uint8_t entry_count; /* Entry count. */
1633 uint8_t sys_define; /* System defined. */
1634 uint8_t entry_status; /* Entry Status. */
1635 uint32_t handle; /* System handle. */
1636 target_id_t target; /* SCSI ID */
1637 uint16_t lun; /* SCSI LUN */
1638 uint16_t control_flags; /* Control flags. */
1639 #define CF_WRITE BIT_6
1640 #define CF_READ BIT_5
1641 #define CF_SIMPLE_TAG BIT_3
1642 #define CF_ORDERED_TAG BIT_2
1643 #define CF_HEAD_TAG BIT_1
1644 uint16_t reserved_1;
1645 uint16_t timeout; /* Command timeout. */
1646 uint16_t dseg_count; /* Data segment count. */
1647 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1648 uint32_t byte_count; /* Total byte count. */
1649 uint32_t dseg_0_address; /* Data segment 0 address. */
1650 uint32_t dseg_0_length; /* Data segment 0 length. */
1651 uint32_t dseg_1_address; /* Data segment 1 address. */
1652 uint32_t dseg_1_length; /* Data segment 1 length. */
1653 uint32_t dseg_2_address; /* Data segment 2 address. */
1654 uint32_t dseg_2_length; /* Data segment 2 length. */
1655 } cmd_entry_t;
1656
1657 /*
1658 * ISP queue - 64-Bit addressing, command entry structure definition.
1659 */
1660 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1661 typedef struct {
1662 uint8_t entry_type; /* Entry type. */
1663 uint8_t entry_count; /* Entry count. */
1664 uint8_t sys_define; /* System defined. */
1665 uint8_t entry_status; /* Entry Status. */
1666 uint32_t handle; /* System handle. */
1667 target_id_t target; /* SCSI ID */
1668 uint16_t lun; /* SCSI LUN */
1669 uint16_t control_flags; /* Control flags. */
1670 uint16_t reserved_1;
1671 uint16_t timeout; /* Command timeout. */
1672 uint16_t dseg_count; /* Data segment count. */
1673 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1674 uint32_t byte_count; /* Total byte count. */
1675 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1676 uint32_t dseg_0_length; /* Data segment 0 length. */
1677 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1678 uint32_t dseg_1_length; /* Data segment 1 length. */
1679 } cmd_a64_entry_t, request_t;
1680
1681 /*
1682 * ISP queue - continuation entry structure definition.
1683 */
1684 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1685 typedef struct {
1686 uint8_t entry_type; /* Entry type. */
1687 uint8_t entry_count; /* Entry count. */
1688 uint8_t sys_define; /* System defined. */
1689 uint8_t entry_status; /* Entry Status. */
1690 uint32_t reserved;
1691 uint32_t dseg_0_address; /* Data segment 0 address. */
1692 uint32_t dseg_0_length; /* Data segment 0 length. */
1693 uint32_t dseg_1_address; /* Data segment 1 address. */
1694 uint32_t dseg_1_length; /* Data segment 1 length. */
1695 uint32_t dseg_2_address; /* Data segment 2 address. */
1696 uint32_t dseg_2_length; /* Data segment 2 length. */
1697 uint32_t dseg_3_address; /* Data segment 3 address. */
1698 uint32_t dseg_3_length; /* Data segment 3 length. */
1699 uint32_t dseg_4_address; /* Data segment 4 address. */
1700 uint32_t dseg_4_length; /* Data segment 4 length. */
1701 uint32_t dseg_5_address; /* Data segment 5 address. */
1702 uint32_t dseg_5_length; /* Data segment 5 length. */
1703 uint32_t dseg_6_address; /* Data segment 6 address. */
1704 uint32_t dseg_6_length; /* Data segment 6 length. */
1705 } cont_entry_t;
1706
1707 /*
1708 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1709 */
1710 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1711 typedef struct {
1712 uint8_t entry_type; /* Entry type. */
1713 uint8_t entry_count; /* Entry count. */
1714 uint8_t sys_define; /* System defined. */
1715 uint8_t entry_status; /* Entry Status. */
1716 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1717 uint32_t dseg_0_length; /* Data segment 0 length. */
1718 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1719 uint32_t dseg_1_length; /* Data segment 1 length. */
1720 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1721 uint32_t dseg_2_length; /* Data segment 2 length. */
1722 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1723 uint32_t dseg_3_length; /* Data segment 3 length. */
1724 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1725 uint32_t dseg_4_length; /* Data segment 4 length. */
1726 } cont_a64_entry_t;
1727
1728 #define PO_MODE_DIF_INSERT 0
1729 #define PO_MODE_DIF_REMOVE 1
1730 #define PO_MODE_DIF_PASS 2
1731 #define PO_MODE_DIF_REPLACE 3
1732 #define PO_MODE_DIF_TCP_CKSUM 6
1733 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1734 #define PO_DISABLE_GUARD_CHECK BIT_4
1735 #define PO_DISABLE_INCR_REF_TAG BIT_5
1736 #define PO_DIS_HEADER_MODE BIT_7
1737 #define PO_ENABLE_DIF_BUNDLING BIT_8
1738 #define PO_DIS_FRAME_MODE BIT_9
1739 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1740 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1741
1742 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1743 #define PO_DIS_REF_TAG_REPL BIT_13
1744 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1745 #define PO_DIS_REF_TAG_VALD BIT_15
1746
1747 /*
1748 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1749 */
1750 struct crc_context {
1751 uint32_t handle; /* System handle. */
1752 __le32 ref_tag;
1753 __le16 app_tag;
1754 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1755 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1756 __le16 guard_seed; /* Initial Guard Seed */
1757 __le16 prot_opts; /* Requested Data Protection Mode */
1758 __le16 blk_size; /* Data size in bytes */
1759 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1760 * only) */
1761 __le32 byte_count; /* Total byte count/ total data
1762 * transfer count */
1763 union {
1764 struct {
1765 uint32_t reserved_1;
1766 uint16_t reserved_2;
1767 uint16_t reserved_3;
1768 uint32_t reserved_4;
1769 uint32_t data_address[2];
1770 uint32_t data_length;
1771 uint32_t reserved_5[2];
1772 uint32_t reserved_6;
1773 } nobundling;
1774 struct {
1775 __le32 dif_byte_count; /* Total DIF byte
1776 * count */
1777 uint16_t reserved_1;
1778 __le16 dseg_count; /* Data segment count */
1779 uint32_t reserved_2;
1780 uint32_t data_address[2];
1781 uint32_t data_length;
1782 uint32_t dif_address[2];
1783 uint32_t dif_length; /* Data segment 0
1784 * length */
1785 } bundling;
1786 } u;
1787
1788 struct fcp_cmnd fcp_cmnd;
1789 dma_addr_t crc_ctx_dma;
1790 /* List of DMA context transfers */
1791 struct list_head dsd_list;
1792
1793 /* This structure should not exceed 512 bytes */
1794 };
1795
1796 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1797 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1798
1799 /*
1800 * ISP queue - status entry structure definition.
1801 */
1802 #define STATUS_TYPE 0x03 /* Status entry. */
1803 typedef struct {
1804 uint8_t entry_type; /* Entry type. */
1805 uint8_t entry_count; /* Entry count. */
1806 uint8_t sys_define; /* System defined. */
1807 uint8_t entry_status; /* Entry Status. */
1808 uint32_t handle; /* System handle. */
1809 uint16_t scsi_status; /* SCSI status. */
1810 uint16_t comp_status; /* Completion status. */
1811 uint16_t state_flags; /* State flags. */
1812 uint16_t status_flags; /* Status flags. */
1813 uint16_t rsp_info_len; /* Response Info Length. */
1814 uint16_t req_sense_length; /* Request sense data length. */
1815 uint32_t residual_length; /* Residual transfer length. */
1816 uint8_t rsp_info[8]; /* FCP response information. */
1817 uint8_t req_sense_data[32]; /* Request sense data. */
1818 } sts_entry_t;
1819
1820 /*
1821 * Status entry entry status
1822 */
1823 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1824 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1825 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1826 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1827 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1828 #define RF_BUSY BIT_1 /* Busy */
1829 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1830 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1831 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1832 RF_INV_E_TYPE)
1833
1834 /*
1835 * Status entry SCSI status bit definitions.
1836 */
1837 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1838 #define SS_RESIDUAL_UNDER BIT_11
1839 #define SS_RESIDUAL_OVER BIT_10
1840 #define SS_SENSE_LEN_VALID BIT_9
1841 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1842 #define SS_SCSI_STATUS_BYTE 0xff
1843
1844 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1845 #define SS_BUSY_CONDITION BIT_3
1846 #define SS_CONDITION_MET BIT_2
1847 #define SS_CHECK_CONDITION BIT_1
1848
1849 /*
1850 * Status entry completion status
1851 */
1852 #define CS_COMPLETE 0x0 /* No errors */
1853 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1854 #define CS_DMA 0x2 /* A DMA direction error. */
1855 #define CS_TRANSPORT 0x3 /* Transport error. */
1856 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1857 #define CS_ABORTED 0x5 /* System aborted command. */
1858 #define CS_TIMEOUT 0x6 /* Timeout error. */
1859 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1860 #define CS_DIF_ERROR 0xC /* DIF error detected */
1861
1862 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1863 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1864 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1865 /* (selection timeout) */
1866 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1867 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1868 #define CS_PORT_BUSY 0x2B /* Port Busy */
1869 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1870 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1871 failure */
1872 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1873 #define CS_UNKNOWN 0x81 /* Driver defined */
1874 #define CS_RETRY 0x82 /* Driver defined */
1875 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1876
1877 #define CS_BIDIR_RD_OVERRUN 0x700
1878 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1879 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1880 #define CS_BIDIR_RD_UNDERRUN 0x1500
1881 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1882 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1883 #define CS_BIDIR_DMA 0x200
1884 /*
1885 * Status entry status flags
1886 */
1887 #define SF_ABTS_TERMINATED BIT_10
1888 #define SF_LOGOUT_SENT BIT_13
1889
1890 /*
1891 * ISP queue - status continuation entry structure definition.
1892 */
1893 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1894 typedef struct {
1895 uint8_t entry_type; /* Entry type. */
1896 uint8_t entry_count; /* Entry count. */
1897 uint8_t sys_define; /* System defined. */
1898 uint8_t entry_status; /* Entry Status. */
1899 uint8_t data[60]; /* data */
1900 } sts_cont_entry_t;
1901
1902 /*
1903 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1904 * structure definition.
1905 */
1906 #define STATUS_TYPE_21 0x21 /* Status entry. */
1907 typedef struct {
1908 uint8_t entry_type; /* Entry type. */
1909 uint8_t entry_count; /* Entry count. */
1910 uint8_t handle_count; /* Handle count. */
1911 uint8_t entry_status; /* Entry Status. */
1912 uint32_t handle[15]; /* System handles. */
1913 } sts21_entry_t;
1914
1915 /*
1916 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1917 * structure definition.
1918 */
1919 #define STATUS_TYPE_22 0x22 /* Status entry. */
1920 typedef struct {
1921 uint8_t entry_type; /* Entry type. */
1922 uint8_t entry_count; /* Entry count. */
1923 uint8_t handle_count; /* Handle count. */
1924 uint8_t entry_status; /* Entry Status. */
1925 uint16_t handle[30]; /* System handles. */
1926 } sts22_entry_t;
1927
1928 /*
1929 * ISP queue - marker entry structure definition.
1930 */
1931 #define MARKER_TYPE 0x04 /* Marker entry. */
1932 typedef struct {
1933 uint8_t entry_type; /* Entry type. */
1934 uint8_t entry_count; /* Entry count. */
1935 uint8_t handle_count; /* Handle count. */
1936 uint8_t entry_status; /* Entry Status. */
1937 uint32_t sys_define_2; /* System defined. */
1938 target_id_t target; /* SCSI ID */
1939 uint8_t modifier; /* Modifier (7-0). */
1940 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1941 #define MK_SYNC_ID 1 /* Synchronize ID */
1942 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1943 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1944 /* clear port changed, */
1945 /* use sequence number. */
1946 uint8_t reserved_1;
1947 uint16_t sequence_number; /* Sequence number of event */
1948 uint16_t lun; /* SCSI LUN */
1949 uint8_t reserved_2[48];
1950 } mrk_entry_t;
1951
1952 /*
1953 * ISP queue - Management Server entry structure definition.
1954 */
1955 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1956 typedef struct {
1957 uint8_t entry_type; /* Entry type. */
1958 uint8_t entry_count; /* Entry count. */
1959 uint8_t handle_count; /* Handle count. */
1960 uint8_t entry_status; /* Entry Status. */
1961 uint32_t handle1; /* System handle. */
1962 target_id_t loop_id;
1963 uint16_t status;
1964 uint16_t control_flags; /* Control flags. */
1965 uint16_t reserved2;
1966 uint16_t timeout;
1967 uint16_t cmd_dsd_count;
1968 uint16_t total_dsd_count;
1969 uint8_t type;
1970 uint8_t r_ctl;
1971 uint16_t rx_id;
1972 uint16_t reserved3;
1973 uint32_t handle2;
1974 uint32_t rsp_bytecount;
1975 uint32_t req_bytecount;
1976 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1977 uint32_t dseg_req_length; /* Data segment 0 length. */
1978 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1979 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1980 } ms_iocb_entry_t;
1981
1982
1983 /*
1984 * ISP queue - Mailbox Command entry structure definition.
1985 */
1986 #define MBX_IOCB_TYPE 0x39
1987 struct mbx_entry {
1988 uint8_t entry_type;
1989 uint8_t entry_count;
1990 uint8_t sys_define1;
1991 /* Use sys_define1 for source type */
1992 #define SOURCE_SCSI 0x00
1993 #define SOURCE_IP 0x01
1994 #define SOURCE_VI 0x02
1995 #define SOURCE_SCTP 0x03
1996 #define SOURCE_MP 0x04
1997 #define SOURCE_MPIOCTL 0x05
1998 #define SOURCE_ASYNC_IOCB 0x07
1999
2000 uint8_t entry_status;
2001
2002 uint32_t handle;
2003 target_id_t loop_id;
2004
2005 uint16_t status;
2006 uint16_t state_flags;
2007 uint16_t status_flags;
2008
2009 uint32_t sys_define2[2];
2010
2011 uint16_t mb0;
2012 uint16_t mb1;
2013 uint16_t mb2;
2014 uint16_t mb3;
2015 uint16_t mb6;
2016 uint16_t mb7;
2017 uint16_t mb9;
2018 uint16_t mb10;
2019 uint32_t reserved_2[2];
2020 uint8_t node_name[WWN_SIZE];
2021 uint8_t port_name[WWN_SIZE];
2022 };
2023
2024 #ifndef IMMED_NOTIFY_TYPE
2025 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2026 /*
2027 * ISP queue - immediate notify entry structure definition.
2028 * This is sent by the ISP to the Target driver.
2029 * This IOCB would have report of events sent by the
2030 * initiator, that needs to be handled by the target
2031 * driver immediately.
2032 */
2033 struct imm_ntfy_from_isp {
2034 uint8_t entry_type; /* Entry type. */
2035 uint8_t entry_count; /* Entry count. */
2036 uint8_t sys_define; /* System defined. */
2037 uint8_t entry_status; /* Entry Status. */
2038 union {
2039 struct {
2040 uint32_t sys_define_2; /* System defined. */
2041 target_id_t target;
2042 uint16_t lun;
2043 uint8_t target_id;
2044 uint8_t reserved_1;
2045 uint16_t status_modifier;
2046 uint16_t status;
2047 uint16_t task_flags;
2048 uint16_t seq_id;
2049 uint16_t srr_rx_id;
2050 uint32_t srr_rel_offs;
2051 uint16_t srr_ui;
2052 #define SRR_IU_DATA_IN 0x1
2053 #define SRR_IU_DATA_OUT 0x5
2054 #define SRR_IU_STATUS 0x7
2055 uint16_t srr_ox_id;
2056 uint8_t reserved_2[28];
2057 } isp2x;
2058 struct {
2059 uint32_t reserved;
2060 uint16_t nport_handle;
2061 uint16_t reserved_2;
2062 uint16_t flags;
2063 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2064 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2065 uint16_t srr_rx_id;
2066 uint16_t status;
2067 uint8_t status_subcode;
2068 uint8_t fw_handle;
2069 uint32_t exchange_address;
2070 uint32_t srr_rel_offs;
2071 uint16_t srr_ui;
2072 uint16_t srr_ox_id;
2073 union {
2074 struct {
2075 uint8_t node_name[8];
2076 } plogi; /* PLOGI/ADISC/PDISC */
2077 struct {
2078 /* PRLI word 3 bit 0-15 */
2079 uint16_t wd3_lo;
2080 uint8_t resv0[6];
2081 } prli;
2082 struct {
2083 uint8_t port_id[3];
2084 uint8_t resv1;
2085 uint16_t nport_handle;
2086 uint16_t resv2;
2087 } req_els;
2088 } u;
2089 uint8_t port_name[8];
2090 uint8_t resv3[3];
2091 uint8_t vp_index;
2092 uint32_t reserved_5;
2093 uint8_t port_id[3];
2094 uint8_t reserved_6;
2095 } isp24;
2096 } u;
2097 uint16_t reserved_7;
2098 uint16_t ox_id;
2099 } __packed;
2100 #endif
2101
2102 /*
2103 * ISP request and response queue entry sizes
2104 */
2105 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2106 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2107
2108
2109 /*
2110 * 24 bit port ID type definition.
2111 */
2112 typedef union {
2113 uint32_t b24 : 24;
2114
2115 struct {
2116 #ifdef __BIG_ENDIAN
2117 uint8_t domain;
2118 uint8_t area;
2119 uint8_t al_pa;
2120 #elif defined(__LITTLE_ENDIAN)
2121 uint8_t al_pa;
2122 uint8_t area;
2123 uint8_t domain;
2124 #else
2125 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
2126 #endif
2127 uint8_t rsvd_1;
2128 } b;
2129 } port_id_t;
2130 #define INVALID_PORT_ID 0xFFFFFF
2131
2132 /*
2133 * Switch info gathering structure.
2134 */
2135 typedef struct {
2136 port_id_t d_id;
2137 uint8_t node_name[WWN_SIZE];
2138 uint8_t port_name[WWN_SIZE];
2139 uint8_t fabric_port_name[WWN_SIZE];
2140 uint16_t fp_speed;
2141 uint8_t fc4_type;
2142 } sw_info_t;
2143
2144 /* FCP-4 types */
2145 #define FC4_TYPE_FCP_SCSI 0x08
2146 #define FC4_TYPE_OTHER 0x0
2147 #define FC4_TYPE_UNKNOWN 0xff
2148
2149 /* mailbox command 4G & above */
2150 struct mbx_24xx_entry {
2151 uint8_t entry_type;
2152 uint8_t entry_count;
2153 uint8_t sys_define1;
2154 uint8_t entry_status;
2155 uint32_t handle;
2156 uint16_t mb[28];
2157 };
2158
2159 #define IOCB_SIZE 64
2160
2161 /*
2162 * Fibre channel port type.
2163 */
2164 typedef enum {
2165 FCT_UNKNOWN,
2166 FCT_RSCN,
2167 FCT_SWITCH,
2168 FCT_BROADCAST,
2169 FCT_INITIATOR,
2170 FCT_TARGET
2171 } fc_port_type_t;
2172
2173 enum qla_sess_deletion {
2174 QLA_SESS_DELETION_NONE = 0,
2175 QLA_SESS_DELETION_IN_PROGRESS,
2176 QLA_SESS_DELETED,
2177 };
2178
2179 enum qlt_plogi_link_t {
2180 QLT_PLOGI_LINK_SAME_WWN,
2181 QLT_PLOGI_LINK_CONFLICT,
2182 QLT_PLOGI_LINK_MAX
2183 };
2184
2185 struct qlt_plogi_ack_t {
2186 struct list_head list;
2187 struct imm_ntfy_from_isp iocb;
2188 port_id_t id;
2189 int ref_count;
2190 void *fcport;
2191 };
2192
2193 struct ct_sns_desc {
2194 struct ct_sns_pkt *ct_sns;
2195 dma_addr_t ct_sns_dma;
2196 };
2197
2198 enum discovery_state {
2199 DSC_DELETED,
2200 DSC_GID_PN,
2201 DSC_GNL,
2202 DSC_LOGIN_PEND,
2203 DSC_LOGIN_FAILED,
2204 DSC_GPDB,
2205 DSC_GPSC,
2206 DSC_UPD_FCPORT,
2207 DSC_LOGIN_COMPLETE,
2208 DSC_DELETE_PEND,
2209 };
2210
2211 enum login_state { /* FW control Target side */
2212 DSC_LS_LLIOCB_SENT = 2,
2213 DSC_LS_PLOGI_PEND,
2214 DSC_LS_PLOGI_COMP,
2215 DSC_LS_PRLI_PEND,
2216 DSC_LS_PRLI_COMP,
2217 DSC_LS_PORT_UNAVAIL,
2218 DSC_LS_PRLO_PEND = 9,
2219 DSC_LS_LOGO_PEND,
2220 };
2221
2222 enum fcport_mgt_event {
2223 FCME_RELOGIN = 1,
2224 FCME_RSCN,
2225 FCME_GIDPN_DONE,
2226 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2227 FCME_GNL_DONE,
2228 FCME_GPSC_DONE,
2229 FCME_GPDB_DONE,
2230 FCME_GPNID_DONE,
2231 FCME_DELETE_DONE,
2232 };
2233
2234 enum rscn_addr_format {
2235 RSCN_PORT_ADDR,
2236 RSCN_AREA_ADDR,
2237 RSCN_DOM_ADDR,
2238 RSCN_FAB_ADDR,
2239 };
2240
2241 /*
2242 * Fibre channel port structure.
2243 */
2244 typedef struct fc_port {
2245 struct list_head list;
2246 struct scsi_qla_host *vha;
2247
2248 uint8_t node_name[WWN_SIZE];
2249 uint8_t port_name[WWN_SIZE];
2250 port_id_t d_id;
2251 uint16_t loop_id;
2252 uint16_t old_loop_id;
2253
2254 unsigned int conf_compl_supported:1;
2255 unsigned int deleted:2;
2256 unsigned int local:1;
2257 unsigned int logout_on_delete:1;
2258 unsigned int logo_ack_needed:1;
2259 unsigned int keep_nport_handle:1;
2260 unsigned int send_els_logo:1;
2261 unsigned int login_pause:1;
2262 unsigned int login_succ:1;
2263
2264 struct fc_port *conflict;
2265 unsigned char logout_completed;
2266 int generation;
2267
2268 struct se_session *se_sess;
2269 struct kref sess_kref;
2270 struct qla_tgt *tgt;
2271 unsigned long expires;
2272 struct list_head del_list_entry;
2273 struct work_struct free_work;
2274
2275 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2276
2277 uint16_t tgt_id;
2278 uint16_t old_tgt_id;
2279
2280 uint8_t fcp_prio;
2281
2282 uint8_t fabric_port_name[WWN_SIZE];
2283 uint16_t fp_speed;
2284
2285 fc_port_type_t port_type;
2286
2287 atomic_t state;
2288 uint32_t flags;
2289
2290 int login_retry;
2291
2292 struct fc_rport *rport, *drport;
2293 u32 supported_classes;
2294
2295 uint8_t fc4_type;
2296 uint8_t scan_state;
2297
2298 unsigned long last_queue_full;
2299 unsigned long last_ramp_up;
2300
2301 uint16_t port_id;
2302
2303 unsigned long retry_delay_timestamp;
2304 struct qla_tgt_sess *tgt_session;
2305 struct ct_sns_desc ct_desc;
2306 enum discovery_state disc_state;
2307 enum login_state fw_login_state;
2308 unsigned long plogi_nack_done_deadline;
2309
2310 u32 login_gen, last_login_gen;
2311 u32 rscn_gen, last_rscn_gen;
2312 u32 chip_reset;
2313 struct list_head gnl_entry;
2314 struct work_struct del_work;
2315 u8 iocb[IOCB_SIZE];
2316 } fc_port_t;
2317
2318 #define QLA_FCPORT_SCAN 1
2319 #define QLA_FCPORT_FOUND 2
2320
2321 struct event_arg {
2322 enum fcport_mgt_event event;
2323 fc_port_t *fcport;
2324 srb_t *sp;
2325 port_id_t id;
2326 u16 data[2], rc;
2327 u8 port_name[WWN_SIZE];
2328 u32 iop[2];
2329 };
2330
2331 #include "qla_mr.h"
2332
2333 /*
2334 * Fibre channel port/lun states.
2335 */
2336 #define FCS_UNCONFIGURED 1
2337 #define FCS_DEVICE_DEAD 2
2338 #define FCS_DEVICE_LOST 3
2339 #define FCS_ONLINE 4
2340
2341 static const char * const port_state_str[] = {
2342 "Unknown",
2343 "UNCONFIGURED",
2344 "DEAD",
2345 "LOST",
2346 "ONLINE"
2347 };
2348
2349 /*
2350 * FC port flags.
2351 */
2352 #define FCF_FABRIC_DEVICE BIT_0
2353 #define FCF_LOGIN_NEEDED BIT_1
2354 #define FCF_FCP2_DEVICE BIT_2
2355 #define FCF_ASYNC_SENT BIT_3
2356 #define FCF_CONF_COMP_SUPPORTED BIT_4
2357
2358 /* No loop ID flag. */
2359 #define FC_NO_LOOP_ID 0x1000
2360
2361 /*
2362 * FC-CT interface
2363 *
2364 * NOTE: All structures are big-endian in form.
2365 */
2366
2367 #define CT_REJECT_RESPONSE 0x8001
2368 #define CT_ACCEPT_RESPONSE 0x8002
2369 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2370 #define CT_REASON_CANNOT_PERFORM 0x09
2371 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2372 #define CT_EXPL_ALREADY_REGISTERED 0x10
2373 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2374 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2375 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2376 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2377 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2378 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2379 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2380 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2381 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2382 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2383 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2384
2385 #define NS_N_PORT_TYPE 0x01
2386 #define NS_NL_PORT_TYPE 0x02
2387 #define NS_NX_PORT_TYPE 0x7F
2388
2389 #define GA_NXT_CMD 0x100
2390 #define GA_NXT_REQ_SIZE (16 + 4)
2391 #define GA_NXT_RSP_SIZE (16 + 620)
2392
2393 #define GID_PT_CMD 0x1A1
2394 #define GID_PT_REQ_SIZE (16 + 4)
2395
2396 #define GPN_ID_CMD 0x112
2397 #define GPN_ID_REQ_SIZE (16 + 4)
2398 #define GPN_ID_RSP_SIZE (16 + 8)
2399
2400 #define GNN_ID_CMD 0x113
2401 #define GNN_ID_REQ_SIZE (16 + 4)
2402 #define GNN_ID_RSP_SIZE (16 + 8)
2403
2404 #define GFT_ID_CMD 0x117
2405 #define GFT_ID_REQ_SIZE (16 + 4)
2406 #define GFT_ID_RSP_SIZE (16 + 32)
2407
2408 #define GID_PN_CMD 0x121
2409 #define GID_PN_REQ_SIZE (16 + 8)
2410 #define GID_PN_RSP_SIZE (16 + 4)
2411
2412 #define RFT_ID_CMD 0x217
2413 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2414 #define RFT_ID_RSP_SIZE 16
2415
2416 #define RFF_ID_CMD 0x21F
2417 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2418 #define RFF_ID_RSP_SIZE 16
2419
2420 #define RNN_ID_CMD 0x213
2421 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2422 #define RNN_ID_RSP_SIZE 16
2423
2424 #define RSNN_NN_CMD 0x239
2425 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2426 #define RSNN_NN_RSP_SIZE 16
2427
2428 #define GFPN_ID_CMD 0x11C
2429 #define GFPN_ID_REQ_SIZE (16 + 4)
2430 #define GFPN_ID_RSP_SIZE (16 + 8)
2431
2432 #define GPSC_CMD 0x127
2433 #define GPSC_REQ_SIZE (16 + 8)
2434 #define GPSC_RSP_SIZE (16 + 2 + 2)
2435
2436 #define GFF_ID_CMD 0x011F
2437 #define GFF_ID_REQ_SIZE (16 + 4)
2438 #define GFF_ID_RSP_SIZE (16 + 128)
2439
2440 /*
2441 * HBA attribute types.
2442 */
2443 #define FDMI_HBA_ATTR_COUNT 9
2444 #define FDMIV2_HBA_ATTR_COUNT 17
2445 #define FDMI_HBA_NODE_NAME 0x1
2446 #define FDMI_HBA_MANUFACTURER 0x2
2447 #define FDMI_HBA_SERIAL_NUMBER 0x3
2448 #define FDMI_HBA_MODEL 0x4
2449 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2450 #define FDMI_HBA_HARDWARE_VERSION 0x6
2451 #define FDMI_HBA_DRIVER_VERSION 0x7
2452 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2453 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2454 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2455 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2456 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2457 #define FDMI_HBA_VENDOR_ID 0xd
2458 #define FDMI_HBA_NUM_PORTS 0xe
2459 #define FDMI_HBA_FABRIC_NAME 0xf
2460 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2461 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2462
2463 struct ct_fdmi_hba_attr {
2464 uint16_t type;
2465 uint16_t len;
2466 union {
2467 uint8_t node_name[WWN_SIZE];
2468 uint8_t manufacturer[64];
2469 uint8_t serial_num[32];
2470 uint8_t model[16+1];
2471 uint8_t model_desc[80];
2472 uint8_t hw_version[32];
2473 uint8_t driver_version[32];
2474 uint8_t orom_version[16];
2475 uint8_t fw_version[32];
2476 uint8_t os_version[128];
2477 uint32_t max_ct_len;
2478 } a;
2479 };
2480
2481 struct ct_fdmi_hba_attributes {
2482 uint32_t count;
2483 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2484 };
2485
2486 struct ct_fdmiv2_hba_attr {
2487 uint16_t type;
2488 uint16_t len;
2489 union {
2490 uint8_t node_name[WWN_SIZE];
2491 uint8_t manufacturer[64];
2492 uint8_t serial_num[32];
2493 uint8_t model[16+1];
2494 uint8_t model_desc[80];
2495 uint8_t hw_version[16];
2496 uint8_t driver_version[32];
2497 uint8_t orom_version[16];
2498 uint8_t fw_version[32];
2499 uint8_t os_version[128];
2500 uint32_t max_ct_len;
2501 uint8_t sym_name[256];
2502 uint32_t vendor_id;
2503 uint32_t num_ports;
2504 uint8_t fabric_name[WWN_SIZE];
2505 uint8_t bios_name[32];
2506 uint8_t vendor_identifier[8];
2507 } a;
2508 };
2509
2510 struct ct_fdmiv2_hba_attributes {
2511 uint32_t count;
2512 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2513 };
2514
2515 /*
2516 * Port attribute types.
2517 */
2518 #define FDMI_PORT_ATTR_COUNT 6
2519 #define FDMIV2_PORT_ATTR_COUNT 16
2520 #define FDMI_PORT_FC4_TYPES 0x1
2521 #define FDMI_PORT_SUPPORT_SPEED 0x2
2522 #define FDMI_PORT_CURRENT_SPEED 0x3
2523 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2524 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2525 #define FDMI_PORT_HOST_NAME 0x6
2526 #define FDMI_PORT_NODE_NAME 0x7
2527 #define FDMI_PORT_NAME 0x8
2528 #define FDMI_PORT_SYM_NAME 0x9
2529 #define FDMI_PORT_TYPE 0xa
2530 #define FDMI_PORT_SUPP_COS 0xb
2531 #define FDMI_PORT_FABRIC_NAME 0xc
2532 #define FDMI_PORT_FC4_TYPE 0xd
2533 #define FDMI_PORT_STATE 0x101
2534 #define FDMI_PORT_COUNT 0x102
2535 #define FDMI_PORT_ID 0x103
2536
2537 #define FDMI_PORT_SPEED_1GB 0x1
2538 #define FDMI_PORT_SPEED_2GB 0x2
2539 #define FDMI_PORT_SPEED_10GB 0x4
2540 #define FDMI_PORT_SPEED_4GB 0x8
2541 #define FDMI_PORT_SPEED_8GB 0x10
2542 #define FDMI_PORT_SPEED_16GB 0x20
2543 #define FDMI_PORT_SPEED_32GB 0x40
2544 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2545
2546 #define FC_CLASS_2 0x04
2547 #define FC_CLASS_3 0x08
2548 #define FC_CLASS_2_3 0x0C
2549
2550 struct ct_fdmiv2_port_attr {
2551 uint16_t type;
2552 uint16_t len;
2553 union {
2554 uint8_t fc4_types[32];
2555 uint32_t sup_speed;
2556 uint32_t cur_speed;
2557 uint32_t max_frame_size;
2558 uint8_t os_dev_name[32];
2559 uint8_t host_name[256];
2560 uint8_t node_name[WWN_SIZE];
2561 uint8_t port_name[WWN_SIZE];
2562 uint8_t port_sym_name[128];
2563 uint32_t port_type;
2564 uint32_t port_supported_cos;
2565 uint8_t fabric_name[WWN_SIZE];
2566 uint8_t port_fc4_type[32];
2567 uint32_t port_state;
2568 uint32_t num_ports;
2569 uint32_t port_id;
2570 } a;
2571 };
2572
2573 /*
2574 * Port Attribute Block.
2575 */
2576 struct ct_fdmiv2_port_attributes {
2577 uint32_t count;
2578 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2579 };
2580
2581 struct ct_fdmi_port_attr {
2582 uint16_t type;
2583 uint16_t len;
2584 union {
2585 uint8_t fc4_types[32];
2586 uint32_t sup_speed;
2587 uint32_t cur_speed;
2588 uint32_t max_frame_size;
2589 uint8_t os_dev_name[32];
2590 uint8_t host_name[256];
2591 } a;
2592 };
2593
2594 struct ct_fdmi_port_attributes {
2595 uint32_t count;
2596 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2597 };
2598
2599 /* FDMI definitions. */
2600 #define GRHL_CMD 0x100
2601 #define GHAT_CMD 0x101
2602 #define GRPL_CMD 0x102
2603 #define GPAT_CMD 0x110
2604
2605 #define RHBA_CMD 0x200
2606 #define RHBA_RSP_SIZE 16
2607
2608 #define RHAT_CMD 0x201
2609 #define RPRT_CMD 0x210
2610
2611 #define RPA_CMD 0x211
2612 #define RPA_RSP_SIZE 16
2613
2614 #define DHBA_CMD 0x300
2615 #define DHBA_REQ_SIZE (16 + 8)
2616 #define DHBA_RSP_SIZE 16
2617
2618 #define DHAT_CMD 0x301
2619 #define DPRT_CMD 0x310
2620 #define DPA_CMD 0x311
2621
2622 /* CT command header -- request/response common fields */
2623 struct ct_cmd_hdr {
2624 uint8_t revision;
2625 uint8_t in_id[3];
2626 uint8_t gs_type;
2627 uint8_t gs_subtype;
2628 uint8_t options;
2629 uint8_t reserved;
2630 };
2631
2632 /* CT command request */
2633 struct ct_sns_req {
2634 struct ct_cmd_hdr header;
2635 uint16_t command;
2636 uint16_t max_rsp_size;
2637 uint8_t fragment_id;
2638 uint8_t reserved[3];
2639
2640 union {
2641 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2642 struct {
2643 uint8_t reserved;
2644 uint8_t port_id[3];
2645 } port_id;
2646
2647 struct {
2648 uint8_t port_type;
2649 uint8_t domain;
2650 uint8_t area;
2651 uint8_t reserved;
2652 } gid_pt;
2653
2654 struct {
2655 uint8_t reserved;
2656 uint8_t port_id[3];
2657 uint8_t fc4_types[32];
2658 } rft_id;
2659
2660 struct {
2661 uint8_t reserved;
2662 uint8_t port_id[3];
2663 uint16_t reserved2;
2664 uint8_t fc4_feature;
2665 uint8_t fc4_type;
2666 } rff_id;
2667
2668 struct {
2669 uint8_t reserved;
2670 uint8_t port_id[3];
2671 uint8_t node_name[8];
2672 } rnn_id;
2673
2674 struct {
2675 uint8_t node_name[8];
2676 uint8_t name_len;
2677 uint8_t sym_node_name[255];
2678 } rsnn_nn;
2679
2680 struct {
2681 uint8_t hba_identifier[8];
2682 } ghat;
2683
2684 struct {
2685 uint8_t hba_identifier[8];
2686 uint32_t entry_count;
2687 uint8_t port_name[8];
2688 struct ct_fdmi_hba_attributes attrs;
2689 } rhba;
2690
2691 struct {
2692 uint8_t hba_identifier[8];
2693 uint32_t entry_count;
2694 uint8_t port_name[8];
2695 struct ct_fdmiv2_hba_attributes attrs;
2696 } rhba2;
2697
2698 struct {
2699 uint8_t hba_identifier[8];
2700 struct ct_fdmi_hba_attributes attrs;
2701 } rhat;
2702
2703 struct {
2704 uint8_t port_name[8];
2705 struct ct_fdmi_port_attributes attrs;
2706 } rpa;
2707
2708 struct {
2709 uint8_t port_name[8];
2710 struct ct_fdmiv2_port_attributes attrs;
2711 } rpa2;
2712
2713 struct {
2714 uint8_t port_name[8];
2715 } dhba;
2716
2717 struct {
2718 uint8_t port_name[8];
2719 } dhat;
2720
2721 struct {
2722 uint8_t port_name[8];
2723 } dprt;
2724
2725 struct {
2726 uint8_t port_name[8];
2727 } dpa;
2728
2729 struct {
2730 uint8_t port_name[8];
2731 } gpsc;
2732
2733 struct {
2734 uint8_t reserved;
2735 uint8_t port_name[3];
2736 } gff_id;
2737
2738 struct {
2739 uint8_t port_name[8];
2740 } gid_pn;
2741 } req;
2742 };
2743
2744 /* CT command response header */
2745 struct ct_rsp_hdr {
2746 struct ct_cmd_hdr header;
2747 uint16_t response;
2748 uint16_t residual;
2749 uint8_t fragment_id;
2750 uint8_t reason_code;
2751 uint8_t explanation_code;
2752 uint8_t vendor_unique;
2753 };
2754
2755 struct ct_sns_gid_pt_data {
2756 uint8_t control_byte;
2757 uint8_t port_id[3];
2758 };
2759
2760 struct ct_sns_rsp {
2761 struct ct_rsp_hdr header;
2762
2763 union {
2764 struct {
2765 uint8_t port_type;
2766 uint8_t port_id[3];
2767 uint8_t port_name[8];
2768 uint8_t sym_port_name_len;
2769 uint8_t sym_port_name[255];
2770 uint8_t node_name[8];
2771 uint8_t sym_node_name_len;
2772 uint8_t sym_node_name[255];
2773 uint8_t init_proc_assoc[8];
2774 uint8_t node_ip_addr[16];
2775 uint8_t class_of_service[4];
2776 uint8_t fc4_types[32];
2777 uint8_t ip_address[16];
2778 uint8_t fabric_port_name[8];
2779 uint8_t reserved;
2780 uint8_t hard_address[3];
2781 } ga_nxt;
2782
2783 struct {
2784 /* Assume the largest number of targets for the union */
2785 struct ct_sns_gid_pt_data
2786 entries[MAX_FIBRE_DEVICES_MAX];
2787 } gid_pt;
2788
2789 struct {
2790 uint8_t port_name[8];
2791 } gpn_id;
2792
2793 struct {
2794 uint8_t node_name[8];
2795 } gnn_id;
2796
2797 struct {
2798 uint8_t fc4_types[32];
2799 } gft_id;
2800
2801 struct {
2802 uint32_t entry_count;
2803 uint8_t port_name[8];
2804 struct ct_fdmi_hba_attributes attrs;
2805 } ghat;
2806
2807 struct {
2808 uint8_t port_name[8];
2809 } gfpn_id;
2810
2811 struct {
2812 uint16_t speeds;
2813 uint16_t speed;
2814 } gpsc;
2815
2816 #define GFF_FCP_SCSI_OFFSET 7
2817 struct {
2818 uint8_t fc4_features[128];
2819 } gff_id;
2820 struct {
2821 uint8_t reserved;
2822 uint8_t port_id[3];
2823 } gid_pn;
2824 } rsp;
2825 };
2826
2827 struct ct_sns_pkt {
2828 union {
2829 struct ct_sns_req req;
2830 struct ct_sns_rsp rsp;
2831 } p;
2832 };
2833
2834 /*
2835 * SNS command structures -- for 2200 compatibility.
2836 */
2837 #define RFT_ID_SNS_SCMD_LEN 22
2838 #define RFT_ID_SNS_CMD_SIZE 60
2839 #define RFT_ID_SNS_DATA_SIZE 16
2840
2841 #define RNN_ID_SNS_SCMD_LEN 10
2842 #define RNN_ID_SNS_CMD_SIZE 36
2843 #define RNN_ID_SNS_DATA_SIZE 16
2844
2845 #define GA_NXT_SNS_SCMD_LEN 6
2846 #define GA_NXT_SNS_CMD_SIZE 28
2847 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2848
2849 #define GID_PT_SNS_SCMD_LEN 6
2850 #define GID_PT_SNS_CMD_SIZE 28
2851 /*
2852 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2853 * adapters.
2854 */
2855 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2856
2857 #define GPN_ID_SNS_SCMD_LEN 6
2858 #define GPN_ID_SNS_CMD_SIZE 28
2859 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2860
2861 #define GNN_ID_SNS_SCMD_LEN 6
2862 #define GNN_ID_SNS_CMD_SIZE 28
2863 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2864
2865 struct sns_cmd_pkt {
2866 union {
2867 struct {
2868 uint16_t buffer_length;
2869 uint16_t reserved_1;
2870 uint32_t buffer_address[2];
2871 uint16_t subcommand_length;
2872 uint16_t reserved_2;
2873 uint16_t subcommand;
2874 uint16_t size;
2875 uint32_t reserved_3;
2876 uint8_t param[36];
2877 } cmd;
2878
2879 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2880 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2881 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2882 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2883 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2884 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2885 } p;
2886 };
2887
2888 struct fw_blob {
2889 char *name;
2890 uint32_t segs[4];
2891 const struct firmware *fw;
2892 };
2893
2894 /* Return data from MBC_GET_ID_LIST call. */
2895 struct gid_list_info {
2896 uint8_t al_pa;
2897 uint8_t area;
2898 uint8_t domain;
2899 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2900 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2901 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2902 };
2903
2904 /* NPIV */
2905 typedef struct vport_info {
2906 uint8_t port_name[WWN_SIZE];
2907 uint8_t node_name[WWN_SIZE];
2908 int vp_id;
2909 uint16_t loop_id;
2910 unsigned long host_no;
2911 uint8_t port_id[3];
2912 int loop_state;
2913 } vport_info_t;
2914
2915 typedef struct vport_params {
2916 uint8_t port_name[WWN_SIZE];
2917 uint8_t node_name[WWN_SIZE];
2918 uint32_t options;
2919 #define VP_OPTS_RETRY_ENABLE BIT_0
2920 #define VP_OPTS_VP_DISABLE BIT_1
2921 } vport_params_t;
2922
2923 /* NPIV - return codes of VP create and modify */
2924 #define VP_RET_CODE_OK 0
2925 #define VP_RET_CODE_FATAL 1
2926 #define VP_RET_CODE_WRONG_ID 2
2927 #define VP_RET_CODE_WWPN 3
2928 #define VP_RET_CODE_RESOURCES 4
2929 #define VP_RET_CODE_NO_MEM 5
2930 #define VP_RET_CODE_NOT_FOUND 6
2931
2932 struct qla_hw_data;
2933 struct rsp_que;
2934 /*
2935 * ISP operations
2936 */
2937 struct isp_operations {
2938
2939 int (*pci_config) (struct scsi_qla_host *);
2940 void (*reset_chip) (struct scsi_qla_host *);
2941 int (*chip_diag) (struct scsi_qla_host *);
2942 void (*config_rings) (struct scsi_qla_host *);
2943 void (*reset_adapter) (struct scsi_qla_host *);
2944 int (*nvram_config) (struct scsi_qla_host *);
2945 void (*update_fw_options) (struct scsi_qla_host *);
2946 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2947
2948 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2949 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
2950
2951 irq_handler_t intr_handler;
2952 void (*enable_intrs) (struct qla_hw_data *);
2953 void (*disable_intrs) (struct qla_hw_data *);
2954
2955 int (*abort_command) (srb_t *);
2956 int (*target_reset) (struct fc_port *, uint64_t, int);
2957 int (*lun_reset) (struct fc_port *, uint64_t, int);
2958 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2959 uint8_t, uint8_t, uint16_t *, uint8_t);
2960 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2961 uint8_t, uint8_t);
2962
2963 uint16_t (*calc_req_entries) (uint16_t);
2964 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2965 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
2966 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2967 uint32_t);
2968
2969 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
2970 uint32_t, uint32_t);
2971 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2972 uint32_t);
2973
2974 void (*fw_dump) (struct scsi_qla_host *, int);
2975
2976 int (*beacon_on) (struct scsi_qla_host *);
2977 int (*beacon_off) (struct scsi_qla_host *);
2978 void (*beacon_blink) (struct scsi_qla_host *);
2979
2980 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2981 uint32_t, uint32_t);
2982 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2983 uint32_t);
2984
2985 int (*get_flash_version) (struct scsi_qla_host *, void *);
2986 int (*start_scsi) (srb_t *);
2987 int (*start_scsi_mq) (srb_t *);
2988 int (*abort_isp) (struct scsi_qla_host *);
2989 int (*iospace_config)(struct qla_hw_data*);
2990 int (*initialize_adapter)(struct scsi_qla_host *);
2991 };
2992
2993 /* MSI-X Support *************************************************************/
2994
2995 #define QLA_MSIX_CHIP_REV_24XX 3
2996 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2997 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2998
2999 #define QLA_BASE_VECTORS 2 /* default + RSP */
3000 #define QLA_MSIX_RSP_Q 0x01
3001 #define QLA_ATIO_VECTOR 0x02
3002 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3003
3004 #define QLA_MIDX_DEFAULT 0
3005 #define QLA_MIDX_RSP_Q 1
3006 #define QLA_PCI_MSIX_CONTROL 0xa2
3007 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3008
3009 struct scsi_qla_host;
3010
3011
3012 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3013
3014 struct qla_msix_entry {
3015 int have_irq;
3016 int in_use;
3017 uint32_t vector;
3018 uint16_t entry;
3019 char name[30];
3020 void *handle;
3021 int cpuid;
3022 };
3023
3024 #define WATCH_INTERVAL 1 /* number of seconds */
3025
3026 /* Work events. */
3027 enum qla_work_type {
3028 QLA_EVT_AEN,
3029 QLA_EVT_IDC_ACK,
3030 QLA_EVT_ASYNC_LOGIN,
3031 QLA_EVT_ASYNC_LOGOUT,
3032 QLA_EVT_ASYNC_LOGOUT_DONE,
3033 QLA_EVT_ASYNC_ADISC,
3034 QLA_EVT_ASYNC_ADISC_DONE,
3035 QLA_EVT_UEVENT,
3036 QLA_EVT_AENFX,
3037 QLA_EVT_GIDPN,
3038 QLA_EVT_GPNID,
3039 QLA_EVT_GPNID_DONE,
3040 QLA_EVT_NEW_SESS,
3041 QLA_EVT_GPDB,
3042 QLA_EVT_GPSC,
3043 QLA_EVT_UPD_FCPORT,
3044 QLA_EVT_GNL,
3045 QLA_EVT_NACK,
3046 };
3047
3048
3049 struct qla_work_evt {
3050 struct list_head list;
3051 enum qla_work_type type;
3052 u32 flags;
3053 #define QLA_EVT_FLAG_FREE 0x1
3054
3055 union {
3056 struct {
3057 enum fc_host_event_code code;
3058 u32 data;
3059 } aen;
3060 struct {
3061 #define QLA_IDC_ACK_REGS 7
3062 uint16_t mb[QLA_IDC_ACK_REGS];
3063 } idc_ack;
3064 struct {
3065 struct fc_port *fcport;
3066 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3067 u16 data[2];
3068 } logio;
3069 struct {
3070 u32 code;
3071 #define QLA_UEVENT_CODE_FW_DUMP 0
3072 } uevent;
3073 struct {
3074 uint32_t evtcode;
3075 uint32_t mbx[8];
3076 uint32_t count;
3077 } aenfx;
3078 struct {
3079 srb_t *sp;
3080 } iosb;
3081 struct {
3082 port_id_t id;
3083 } gpnid;
3084 struct {
3085 port_id_t id;
3086 u8 port_name[8];
3087 void *pla;
3088 } new_sess;
3089 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3090 fc_port_t *fcport;
3091 u8 opt;
3092 } fcport;
3093 struct {
3094 fc_port_t *fcport;
3095 u8 iocb[IOCB_SIZE];
3096 int type;
3097 } nack;
3098 } u;
3099 };
3100
3101 struct qla_chip_state_84xx {
3102 struct list_head list;
3103 struct kref kref;
3104
3105 void *bus;
3106 spinlock_t access_lock;
3107 struct mutex fw_update_mutex;
3108 uint32_t fw_update;
3109 uint32_t op_fw_version;
3110 uint32_t op_fw_size;
3111 uint32_t op_fw_seq_size;
3112 uint32_t diag_fw_version;
3113 uint32_t gold_fw_version;
3114 };
3115
3116 struct qla_dif_statistics {
3117 uint64_t dif_input_bytes;
3118 uint64_t dif_output_bytes;
3119 uint64_t dif_input_requests;
3120 uint64_t dif_output_requests;
3121 uint32_t dif_guard_err;
3122 uint32_t dif_ref_tag_err;
3123 uint32_t dif_app_tag_err;
3124 };
3125
3126 struct qla_statistics {
3127 uint32_t total_isp_aborts;
3128 uint64_t input_bytes;
3129 uint64_t output_bytes;
3130 uint64_t input_requests;
3131 uint64_t output_requests;
3132 uint32_t control_requests;
3133
3134 uint64_t jiffies_at_last_reset;
3135 uint32_t stat_max_pend_cmds;
3136 uint32_t stat_max_qfull_cmds_alloc;
3137 uint32_t stat_max_qfull_cmds_dropped;
3138
3139 struct qla_dif_statistics qla_dif_stats;
3140 };
3141
3142 struct bidi_statistics {
3143 unsigned long long io_count;
3144 unsigned long long transfer_bytes;
3145 };
3146
3147 struct qla_tc_param {
3148 struct scsi_qla_host *vha;
3149 uint32_t blk_sz;
3150 uint32_t bufflen;
3151 struct scatterlist *sg;
3152 struct scatterlist *prot_sg;
3153 struct crc_context *ctx;
3154 uint8_t *ctx_dsd_alloced;
3155 };
3156
3157 /* Multi queue support */
3158 #define MBC_INITIALIZE_MULTIQ 0x1f
3159 #define QLA_QUE_PAGE 0X1000
3160 #define QLA_MQ_SIZE 32
3161 #define QLA_MAX_QUEUES 256
3162 #define ISP_QUE_REG(ha, id) \
3163 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3164 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3165 ((void __iomem *)ha->iobase))
3166 #define QLA_REQ_QUE_ID(tag) \
3167 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3168 #define QLA_DEFAULT_QUE_QOS 5
3169 #define QLA_PRECONFIG_VPORTS 32
3170 #define QLA_MAX_VPORTS_QLA24XX 128
3171 #define QLA_MAX_VPORTS_QLA25XX 256
3172 /* Response queue data structure */
3173 struct rsp_que {
3174 dma_addr_t dma;
3175 response_t *ring;
3176 response_t *ring_ptr;
3177 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3178 uint32_t __iomem *rsp_q_out;
3179 uint16_t ring_index;
3180 uint16_t out_ptr;
3181 uint16_t *in_ptr; /* queue shadow in index */
3182 uint16_t length;
3183 uint16_t options;
3184 uint16_t rid;
3185 uint16_t id;
3186 uint16_t vp_idx;
3187 struct qla_hw_data *hw;
3188 struct qla_msix_entry *msix;
3189 struct req_que *req;
3190 srb_t *status_srb; /* status continuation entry */
3191
3192 dma_addr_t dma_fx00;
3193 response_t *ring_fx00;
3194 uint16_t length_fx00;
3195 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3196 };
3197
3198 /* Request queue data structure */
3199 struct req_que {
3200 dma_addr_t dma;
3201 request_t *ring;
3202 request_t *ring_ptr;
3203 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3204 uint32_t __iomem *req_q_out;
3205 uint16_t ring_index;
3206 uint16_t in_ptr;
3207 uint16_t *out_ptr; /* queue shadow out index */
3208 uint16_t cnt;
3209 uint16_t length;
3210 uint16_t options;
3211 uint16_t rid;
3212 uint16_t id;
3213 uint16_t qos;
3214 uint16_t vp_idx;
3215 struct rsp_que *rsp;
3216 srb_t **outstanding_cmds;
3217 uint32_t current_outstanding_cmd;
3218 uint16_t num_outstanding_cmds;
3219 int max_q_depth;
3220
3221 dma_addr_t dma_fx00;
3222 request_t *ring_fx00;
3223 uint16_t length_fx00;
3224 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3225 };
3226
3227 /*Queue pair data structure */
3228 struct qla_qpair {
3229 spinlock_t qp_lock;
3230 atomic_t ref_count;
3231 /* distill these fields down to 'online=0/1'
3232 * ha->flags.eeh_busy
3233 * ha->flags.pci_channel_io_perm_failure
3234 * base_vha->loop_state
3235 */
3236 uint32_t online:1;
3237 /* move vha->flags.difdix_supported here */
3238 uint32_t difdix_supported:1;
3239 uint32_t delete_in_progress:1;
3240
3241 uint16_t id; /* qp number used with FW */
3242 uint16_t num_active_cmd; /* cmds down at firmware */
3243 cpumask_t cpu_mask; /* CPU mask for cpu affinity operation */
3244 uint16_t vp_idx; /* vport ID */
3245
3246 mempool_t *srb_mempool;
3247
3248 /* to do: New driver: move queues to here instead of pointers */
3249 struct req_que *req;
3250 struct rsp_que *rsp;
3251 struct atio_que *atio;
3252 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3253 struct qla_hw_data *hw;
3254 struct work_struct q_work;
3255 struct list_head qp_list_elem; /* vha->qp_list */
3256 struct scsi_qla_host *vha;
3257 };
3258
3259 /* Place holder for FW buffer parameters */
3260 struct qlfc_fw {
3261 void *fw_buf;
3262 dma_addr_t fw_dma;
3263 uint32_t len;
3264 };
3265
3266 struct scsi_qlt_host {
3267 void *target_lport_ptr;
3268 struct mutex tgt_mutex;
3269 struct mutex tgt_host_action_mutex;
3270 struct qla_tgt *qla_tgt;
3271 };
3272
3273 struct qlt_hw_data {
3274 /* Protected by hw lock */
3275 uint32_t enable_class_2:1;
3276 uint32_t enable_explicit_conf:1;
3277 uint32_t node_name_set:1;
3278
3279 dma_addr_t atio_dma; /* Physical address. */
3280 struct atio *atio_ring; /* Base virtual address */
3281 struct atio *atio_ring_ptr; /* Current address. */
3282 uint16_t atio_ring_index; /* Current index. */
3283 uint16_t atio_q_length;
3284 uint32_t __iomem *atio_q_in;
3285 uint32_t __iomem *atio_q_out;
3286
3287 struct qla_tgt_func_tmpl *tgt_ops;
3288 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
3289 uint16_t current_handle;
3290
3291 struct qla_tgt_vp_map *tgt_vp_map;
3292
3293 int saved_set;
3294 uint16_t saved_exchange_count;
3295 uint32_t saved_firmware_options_1;
3296 uint32_t saved_firmware_options_2;
3297 uint32_t saved_firmware_options_3;
3298 uint8_t saved_firmware_options[2];
3299 uint8_t saved_add_firmware_options[2];
3300
3301 uint8_t tgt_node_name[WWN_SIZE];
3302
3303 struct dentry *dfs_tgt_sess;
3304 struct dentry *dfs_tgt_port_database;
3305
3306 struct list_head q_full_list;
3307 uint32_t num_pend_cmds;
3308 uint32_t num_qfull_cmds_alloc;
3309 uint32_t num_qfull_cmds_dropped;
3310 spinlock_t q_full_lock;
3311 uint32_t leak_exchg_thresh_hold;
3312 spinlock_t sess_lock;
3313 int rspq_vector_cpuid;
3314 spinlock_t atio_lock ____cacheline_aligned;
3315 struct btree_head32 host_map;
3316 };
3317
3318 #define MAX_QFULL_CMDS_ALLOC 8192
3319 #define Q_FULL_THRESH_HOLD_PERCENT 90
3320 #define Q_FULL_THRESH_HOLD(ha) \
3321 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3322
3323 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3324
3325 #define QLA_EARLY_LINKUP(_ha) \
3326 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \
3327 _ha->flags.fw_started && !_ha->flags.fw_init_done)
3328
3329 /*
3330 * Qlogic host adapter specific data structure.
3331 */
3332 struct qla_hw_data {
3333 struct pci_dev *pdev;
3334 /* SRB cache. */
3335 #define SRB_MIN_REQ 128
3336 mempool_t *srb_mempool;
3337
3338 volatile struct {
3339 uint32_t mbox_int :1;
3340 uint32_t mbox_busy :1;
3341 uint32_t disable_risc_code_load :1;
3342 uint32_t enable_64bit_addressing :1;
3343 uint32_t enable_lip_reset :1;
3344 uint32_t enable_target_reset :1;
3345 uint32_t enable_lip_full_login :1;
3346 uint32_t enable_led_scheme :1;
3347
3348 uint32_t msi_enabled :1;
3349 uint32_t msix_enabled :1;
3350 uint32_t disable_serdes :1;
3351 uint32_t gpsc_supported :1;
3352 uint32_t npiv_supported :1;
3353 uint32_t pci_channel_io_perm_failure :1;
3354 uint32_t fce_enabled :1;
3355 uint32_t fac_supported :1;
3356
3357 uint32_t chip_reset_done :1;
3358 uint32_t running_gold_fw :1;
3359 uint32_t eeh_busy :1;
3360 uint32_t disable_msix_handshake :1;
3361 uint32_t fcp_prio_enabled :1;
3362 uint32_t isp82xx_fw_hung:1;
3363 uint32_t nic_core_hung:1;
3364
3365 uint32_t quiesce_owner:1;
3366 uint32_t nic_core_reset_hdlr_active:1;
3367 uint32_t nic_core_reset_owner:1;
3368 uint32_t isp82xx_no_md_cap:1;
3369 uint32_t host_shutting_down:1;
3370 uint32_t idc_compl_status:1;
3371 uint32_t mr_reset_hdlr_active:1;
3372 uint32_t mr_intr_valid:1;
3373
3374 uint32_t dport_enabled:1;
3375 uint32_t fawwpn_enabled:1;
3376 uint32_t exlogins_enabled:1;
3377 uint32_t exchoffld_enabled:1;
3378
3379 uint32_t lip_ae:1;
3380 uint32_t n2n_ae:1;
3381 uint32_t fw_started:1;
3382 uint32_t fw_init_done:1;
3383 } flags;
3384
3385 /* This spinlock is used to protect "io transactions", you must
3386 * acquire it before doing any IO to the card, eg with RD_REG*() and
3387 * WRT_REG*() for the duration of your entire commandtransaction.
3388 *
3389 * This spinlock is of lower priority than the io request lock.
3390 */
3391
3392 spinlock_t hardware_lock ____cacheline_aligned;
3393 int bars;
3394 int mem_only;
3395 device_reg_t *iobase; /* Base I/O address */
3396 resource_size_t pio_address;
3397
3398 #define MIN_IOBASE_LEN 0x100
3399 dma_addr_t bar0_hdl;
3400
3401 void __iomem *cregbase;
3402 dma_addr_t bar2_hdl;
3403 #define BAR0_LEN_FX00 (1024 * 1024)
3404 #define BAR2_LEN_FX00 (128 * 1024)
3405
3406 uint32_t rqstq_intr_code;
3407 uint32_t mbx_intr_code;
3408 uint32_t req_que_len;
3409 uint32_t rsp_que_len;
3410 uint32_t req_que_off;
3411 uint32_t rsp_que_off;
3412
3413 /* Multi queue data structs */
3414 device_reg_t *mqiobase;
3415 device_reg_t *msixbase;
3416 uint16_t msix_count;
3417 uint8_t mqenable;
3418 struct req_que **req_q_map;
3419 struct rsp_que **rsp_q_map;
3420 struct qla_qpair **queue_pair_map;
3421 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3422 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3423 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3424 / sizeof(unsigned long)];
3425 uint8_t max_req_queues;
3426 uint8_t max_rsp_queues;
3427 uint8_t max_qpairs;
3428 uint8_t num_qpairs;
3429 struct qla_qpair *base_qpair;
3430 struct qla_npiv_entry *npiv_info;
3431 uint16_t nvram_npiv_size;
3432
3433 uint16_t switch_cap;
3434 #define FLOGI_SEQ_DEL BIT_8
3435 #define FLOGI_MID_SUPPORT BIT_10
3436 #define FLOGI_VSAN_SUPPORT BIT_12
3437 #define FLOGI_SP_SUPPORT BIT_13
3438
3439 uint8_t port_no; /* Physical port of adapter */
3440 uint8_t exch_starvation;
3441
3442 /* Timeout timers. */
3443 uint8_t loop_down_abort_time; /* port down timer */
3444 atomic_t loop_down_timer; /* loop down timer */
3445 uint8_t link_down_timeout; /* link down timeout */
3446 uint16_t max_loop_id;
3447 uint16_t max_fibre_devices; /* Maximum number of targets */
3448
3449 uint16_t fb_rev;
3450 uint16_t min_external_loopid; /* First external loop Id */
3451
3452 #define PORT_SPEED_UNKNOWN 0xFFFF
3453 #define PORT_SPEED_1GB 0x00
3454 #define PORT_SPEED_2GB 0x01
3455 #define PORT_SPEED_4GB 0x03
3456 #define PORT_SPEED_8GB 0x04
3457 #define PORT_SPEED_16GB 0x05
3458 #define PORT_SPEED_32GB 0x06
3459 #define PORT_SPEED_10GB 0x13
3460 uint16_t link_data_rate; /* F/W operating speed */
3461
3462 uint8_t current_topology;
3463 uint8_t prev_topology;
3464 #define ISP_CFG_NL 1
3465 #define ISP_CFG_N 2
3466 #define ISP_CFG_FL 4
3467 #define ISP_CFG_F 8
3468
3469 uint8_t operating_mode; /* F/W operating mode */
3470 #define LOOP 0
3471 #define P2P 1
3472 #define LOOP_P2P 2
3473 #define P2P_LOOP 3
3474 uint8_t interrupts_on;
3475 uint32_t isp_abort_cnt;
3476 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3477 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3478 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3479 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3480 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3481 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3482 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3483 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3484
3485 uint32_t isp_type;
3486 #define DT_ISP2100 BIT_0
3487 #define DT_ISP2200 BIT_1
3488 #define DT_ISP2300 BIT_2
3489 #define DT_ISP2312 BIT_3
3490 #define DT_ISP2322 BIT_4
3491 #define DT_ISP6312 BIT_5
3492 #define DT_ISP6322 BIT_6
3493 #define DT_ISP2422 BIT_7
3494 #define DT_ISP2432 BIT_8
3495 #define DT_ISP5422 BIT_9
3496 #define DT_ISP5432 BIT_10
3497 #define DT_ISP2532 BIT_11
3498 #define DT_ISP8432 BIT_12
3499 #define DT_ISP8001 BIT_13
3500 #define DT_ISP8021 BIT_14
3501 #define DT_ISP2031 BIT_15
3502 #define DT_ISP8031 BIT_16
3503 #define DT_ISPFX00 BIT_17
3504 #define DT_ISP8044 BIT_18
3505 #define DT_ISP2071 BIT_19
3506 #define DT_ISP2271 BIT_20
3507 #define DT_ISP2261 BIT_21
3508 #define DT_ISP_LAST (DT_ISP2261 << 1)
3509
3510 uint32_t device_type;
3511 #define DT_T10_PI BIT_25
3512 #define DT_IIDMA BIT_26
3513 #define DT_FWI2 BIT_27
3514 #define DT_ZIO_SUPPORTED BIT_28
3515 #define DT_OEM_001 BIT_29
3516 #define DT_ISP2200A BIT_30
3517 #define DT_EXTENDED_IDS BIT_31
3518
3519 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3520 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3521 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3522 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3523 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3524 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3525 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3526 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3527 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3528 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3529 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3530 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3531 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3532 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3533 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3534 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3535 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3536 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3537 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3538 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3539 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3540 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3541 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3542 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3543
3544 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3545 IS_QLA6312(ha) || IS_QLA6322(ha))
3546 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3547 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3548 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3549 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3550 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3551 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3552 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3553 IS_QLA84XX(ha))
3554 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3555 IS_QLA8031(ha) || IS_QLA8044(ha))
3556 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3557 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3558 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3559 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3560 IS_QLA8044(ha) || IS_QLA27XX(ha))
3561 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3562 IS_QLA27XX(ha))
3563 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3564 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3565 IS_QLA27XX(ha))
3566 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3567 IS_QLA27XX(ha))
3568 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3569
3570 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3571 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3572 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3573 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3574 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3575 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3576 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3577 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3578 IS_QLA27XX(ha))
3579 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3580 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3581 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3582 ((ha)->fw_attributes_ext[0] & BIT_0))
3583 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3584 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3585 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3586 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3587 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3588 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3589 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3590 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3591 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3592 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3593 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3594
3595 /* HBA serial number */
3596 uint8_t serial0;
3597 uint8_t serial1;
3598 uint8_t serial2;
3599
3600 /* NVRAM configuration data */
3601 #define MAX_NVRAM_SIZE 4096
3602 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3603 uint16_t nvram_size;
3604 uint16_t nvram_base;
3605 void *nvram;
3606 uint16_t vpd_size;
3607 uint16_t vpd_base;
3608 void *vpd;
3609
3610 uint16_t loop_reset_delay;
3611 uint8_t retry_count;
3612 uint8_t login_timeout;
3613 uint16_t r_a_tov;
3614 int port_down_retry_count;
3615 uint8_t mbx_count;
3616 uint8_t aen_mbx_count;
3617
3618 uint32_t login_retry_count;
3619 /* SNS command interfaces. */
3620 ms_iocb_entry_t *ms_iocb;
3621 dma_addr_t ms_iocb_dma;
3622 struct ct_sns_pkt *ct_sns;
3623 dma_addr_t ct_sns_dma;
3624 /* SNS command interfaces for 2200. */
3625 struct sns_cmd_pkt *sns_cmd;
3626 dma_addr_t sns_cmd_dma;
3627
3628 #define SFP_DEV_SIZE 256
3629 #define SFP_BLOCK_SIZE 64
3630 void *sfp_data;
3631 dma_addr_t sfp_data_dma;
3632
3633 #define XGMAC_DATA_SIZE 4096
3634 void *xgmac_data;
3635 dma_addr_t xgmac_data_dma;
3636
3637 #define DCBX_TLV_DATA_SIZE 4096
3638 void *dcbx_tlv;
3639 dma_addr_t dcbx_tlv_dma;
3640
3641 struct task_struct *dpc_thread;
3642 uint8_t dpc_active; /* DPC routine is active */
3643
3644 dma_addr_t gid_list_dma;
3645 struct gid_list_info *gid_list;
3646 int gid_list_info_size;
3647
3648 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3649 #define DMA_POOL_SIZE 256
3650 struct dma_pool *s_dma_pool;
3651
3652 dma_addr_t init_cb_dma;
3653 init_cb_t *init_cb;
3654 int init_cb_size;
3655 dma_addr_t ex_init_cb_dma;
3656 struct ex_init_cb_81xx *ex_init_cb;
3657
3658 void *async_pd;
3659 dma_addr_t async_pd_dma;
3660
3661 #define ENABLE_EXTENDED_LOGIN BIT_7
3662
3663 /* Extended Logins */
3664 void *exlogin_buf;
3665 dma_addr_t exlogin_buf_dma;
3666 int exlogin_size;
3667
3668 #define ENABLE_EXCHANGE_OFFLD BIT_2
3669
3670 /* Exchange Offload */
3671 void *exchoffld_buf;
3672 dma_addr_t exchoffld_buf_dma;
3673 int exchoffld_size;
3674 int exchoffld_count;
3675
3676 void *swl;
3677
3678 /* These are used by mailbox operations. */
3679 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3680 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3681 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3682
3683 mbx_cmd_t *mcp;
3684 struct mbx_cmd_32 *mcp32;
3685
3686 unsigned long mbx_cmd_flags;
3687 #define MBX_INTERRUPT 1
3688 #define MBX_INTR_WAIT 2
3689 #define MBX_UPDATE_FLASH_ACTIVE 3
3690
3691 struct mutex vport_lock; /* Virtual port synchronization */
3692 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3693 struct mutex mq_lock; /* multi-queue synchronization */
3694 struct completion mbx_cmd_comp; /* Serialize mbx access */
3695 struct completion mbx_intr_comp; /* Used for completion notification */
3696 struct completion dcbx_comp; /* For set port config notification */
3697 struct completion lb_portup_comp; /* Used to wait for link up during
3698 * loopback */
3699 #define DCBX_COMP_TIMEOUT 20
3700 #define LB_PORTUP_COMP_TIMEOUT 10
3701
3702 int notify_dcbx_comp;
3703 int notify_lb_portup_comp;
3704 struct mutex selflogin_lock;
3705
3706 /* Basic firmware related information. */
3707 uint16_t fw_major_version;
3708 uint16_t fw_minor_version;
3709 uint16_t fw_subminor_version;
3710 uint16_t fw_attributes;
3711 uint16_t fw_attributes_h;
3712 uint16_t fw_attributes_ext[2];
3713 uint32_t fw_memory_size;
3714 uint32_t fw_transfer_size;
3715 uint32_t fw_srisc_address;
3716 #define RISC_START_ADDRESS_2100 0x1000
3717 #define RISC_START_ADDRESS_2300 0x800
3718 #define RISC_START_ADDRESS_2400 0x100000
3719
3720 uint16_t orig_fw_tgt_xcb_count;
3721 uint16_t cur_fw_tgt_xcb_count;
3722 uint16_t orig_fw_xcb_count;
3723 uint16_t cur_fw_xcb_count;
3724 uint16_t orig_fw_iocb_count;
3725 uint16_t cur_fw_iocb_count;
3726 uint16_t fw_max_fcf_count;
3727
3728 uint32_t fw_shared_ram_start;
3729 uint32_t fw_shared_ram_end;
3730 uint32_t fw_ddr_ram_start;
3731 uint32_t fw_ddr_ram_end;
3732
3733 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3734 uint8_t fw_seriallink_options[4];
3735 uint16_t fw_seriallink_options24[4];
3736
3737 uint8_t mpi_version[3];
3738 uint32_t mpi_capabilities;
3739 uint8_t phy_version[3];
3740 uint8_t pep_version[3];
3741
3742 /* Firmware dump template */
3743 void *fw_dump_template;
3744 uint32_t fw_dump_template_len;
3745 /* Firmware dump information. */
3746 struct qla2xxx_fw_dump *fw_dump;
3747 uint32_t fw_dump_len;
3748 int fw_dumped;
3749 unsigned long fw_dump_cap_flags;
3750 #define RISC_PAUSE_CMPL 0
3751 #define DMA_SHUTDOWN_CMPL 1
3752 #define ISP_RESET_CMPL 2
3753 #define RISC_RDY_AFT_RESET 3
3754 #define RISC_SRAM_DUMP_CMPL 4
3755 #define RISC_EXT_MEM_DUMP_CMPL 5
3756 #define ISP_MBX_RDY 6
3757 #define ISP_SOFT_RESET_CMPL 7
3758 int fw_dump_reading;
3759 int prev_minidump_failed;
3760 dma_addr_t eft_dma;
3761 void *eft;
3762 /* Current size of mctp dump is 0x086064 bytes */
3763 #define MCTP_DUMP_SIZE 0x086064
3764 dma_addr_t mctp_dump_dma;
3765 void *mctp_dump;
3766 int mctp_dumped;
3767 int mctp_dump_reading;
3768 uint32_t chain_offset;
3769 struct dentry *dfs_dir;
3770 struct dentry *dfs_fce;
3771 struct dentry *dfs_tgt_counters;
3772 struct dentry *dfs_fw_resource_cnt;
3773
3774 dma_addr_t fce_dma;
3775 void *fce;
3776 uint32_t fce_bufs;
3777 uint16_t fce_mb[8];
3778 uint64_t fce_wr, fce_rd;
3779 struct mutex fce_mutex;
3780
3781 uint32_t pci_attr;
3782 uint16_t chip_revision;
3783
3784 uint16_t product_id[4];
3785
3786 uint8_t model_number[16+1];
3787 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3788 char model_desc[80];
3789 uint8_t adapter_id[16+1];
3790
3791 /* Option ROM information. */
3792 char *optrom_buffer;
3793 uint32_t optrom_size;
3794 int optrom_state;
3795 #define QLA_SWAITING 0
3796 #define QLA_SREADING 1
3797 #define QLA_SWRITING 2
3798 uint32_t optrom_region_start;
3799 uint32_t optrom_region_size;
3800 struct mutex optrom_mutex;
3801
3802 /* PCI expansion ROM image information. */
3803 #define ROM_CODE_TYPE_BIOS 0
3804 #define ROM_CODE_TYPE_FCODE 1
3805 #define ROM_CODE_TYPE_EFI 3
3806 uint8_t bios_revision[2];
3807 uint8_t efi_revision[2];
3808 uint8_t fcode_revision[16];
3809 uint32_t fw_revision[4];
3810
3811 uint32_t gold_fw_version[4];
3812
3813 /* Offsets for flash/nvram access (set to ~0 if not used). */
3814 uint32_t flash_conf_off;
3815 uint32_t flash_data_off;
3816 uint32_t nvram_conf_off;
3817 uint32_t nvram_data_off;
3818
3819 uint32_t fdt_wrt_disable;
3820 uint32_t fdt_wrt_enable;
3821 uint32_t fdt_erase_cmd;
3822 uint32_t fdt_block_size;
3823 uint32_t fdt_unprotect_sec_cmd;
3824 uint32_t fdt_protect_sec_cmd;
3825 uint32_t fdt_wrt_sts_reg_cmd;
3826
3827 uint32_t flt_region_flt;
3828 uint32_t flt_region_fdt;
3829 uint32_t flt_region_boot;
3830 uint32_t flt_region_boot_sec;
3831 uint32_t flt_region_fw;
3832 uint32_t flt_region_fw_sec;
3833 uint32_t flt_region_vpd_nvram;
3834 uint32_t flt_region_vpd;
3835 uint32_t flt_region_vpd_sec;
3836 uint32_t flt_region_nvram;
3837 uint32_t flt_region_npiv_conf;
3838 uint32_t flt_region_gold_fw;
3839 uint32_t flt_region_fcp_prio;
3840 uint32_t flt_region_bootload;
3841 uint32_t flt_region_img_status_pri;
3842 uint32_t flt_region_img_status_sec;
3843 uint8_t active_image;
3844
3845 /* Needed for BEACON */
3846 uint16_t beacon_blink_led;
3847 uint8_t beacon_color_state;
3848 #define QLA_LED_GRN_ON 0x01
3849 #define QLA_LED_YLW_ON 0x02
3850 #define QLA_LED_ABR_ON 0x04
3851 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3852 /* ISP2322: red, green, amber. */
3853 uint16_t zio_mode;
3854 uint16_t zio_timer;
3855
3856 struct qla_msix_entry *msix_entries;
3857
3858 struct list_head vp_list; /* list of VP */
3859 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3860 sizeof(unsigned long)];
3861 uint16_t num_vhosts; /* number of vports created */
3862 uint16_t num_vsans; /* number of vsan created */
3863 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3864 int cur_vport_count;
3865
3866 struct qla_chip_state_84xx *cs84xx;
3867 struct isp_operations *isp_ops;
3868 struct workqueue_struct *wq;
3869 struct qlfc_fw fw_buf;
3870
3871 /* FCP_CMND priority support */
3872 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3873
3874 struct dma_pool *dl_dma_pool;
3875 #define DSD_LIST_DMA_POOL_SIZE 512
3876
3877 struct dma_pool *fcp_cmnd_dma_pool;
3878 mempool_t *ctx_mempool;
3879 #define FCP_CMND_DMA_POOL_SIZE 512
3880
3881 void __iomem *nx_pcibase; /* Base I/O address */
3882 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3883 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3884
3885 uint32_t crb_win;
3886 uint32_t curr_window;
3887 uint32_t ddr_mn_window;
3888 unsigned long mn_win_crb;
3889 unsigned long ms_win_crb;
3890 int qdr_sn_window;
3891 uint32_t fcoe_dev_init_timeout;
3892 uint32_t fcoe_reset_timeout;
3893 rwlock_t hw_lock;
3894 uint16_t portnum; /* port number */
3895 int link_width;
3896 struct fw_blob *hablob;
3897 struct qla82xx_legacy_intr_set nx_legacy_intr;
3898
3899 uint16_t gbl_dsd_inuse;
3900 uint16_t gbl_dsd_avail;
3901 struct list_head gbl_dsd_list;
3902 #define NUM_DSD_CHAIN 4096
3903
3904 uint8_t fw_type;
3905 __le32 file_prd_off; /* File firmware product offset */
3906
3907 uint32_t md_template_size;
3908 void *md_tmplt_hdr;
3909 dma_addr_t md_tmplt_hdr_dma;
3910 void *md_dump;
3911 uint32_t md_dump_size;
3912
3913 void *loop_id_map;
3914
3915 /* QLA83XX IDC specific fields */
3916 uint32_t idc_audit_ts;
3917 uint32_t idc_extend_tmo;
3918
3919 /* DPC low-priority workqueue */
3920 struct workqueue_struct *dpc_lp_wq;
3921 struct work_struct idc_aen;
3922 /* DPC high-priority workqueue */
3923 struct workqueue_struct *dpc_hp_wq;
3924 struct work_struct nic_core_reset;
3925 struct work_struct idc_state_handler;
3926 struct work_struct nic_core_unrecoverable;
3927 struct work_struct board_disable;
3928
3929 struct mr_data_fx00 mr;
3930 uint32_t chip_reset;
3931
3932 struct qlt_hw_data tgt;
3933 int allow_cna_fw_dump;
3934 };
3935
3936 struct qla_tgt_counters {
3937 uint64_t qla_core_sbt_cmd;
3938 uint64_t core_qla_que_buf;
3939 uint64_t qla_core_ret_ctio;
3940 uint64_t core_qla_snd_status;
3941 uint64_t qla_core_ret_sta_ctio;
3942 uint64_t core_qla_free_cmd;
3943 uint64_t num_q_full_sent;
3944 uint64_t num_alloc_iocb_failed;
3945 uint64_t num_term_xchg_sent;
3946 };
3947
3948 /*
3949 * Qlogic scsi host structure
3950 */
3951 typedef struct scsi_qla_host {
3952 struct list_head list;
3953 struct list_head vp_fcports; /* list of fcports */
3954 struct list_head work_list;
3955 spinlock_t work_lock;
3956 struct work_struct iocb_work;
3957
3958 /* Commonly used flags and state information. */
3959 struct Scsi_Host *host;
3960 unsigned long host_no;
3961 uint8_t host_str[16];
3962
3963 volatile struct {
3964 uint32_t init_done :1;
3965 uint32_t online :1;
3966 uint32_t reset_active :1;
3967
3968 uint32_t management_server_logged_in :1;
3969 uint32_t process_response_queue :1;
3970 uint32_t difdix_supported:1;
3971 uint32_t delete_progress:1;
3972
3973 uint32_t fw_tgt_reported:1;
3974 uint32_t bbcr_enable:1;
3975 uint32_t qpairs_available:1;
3976 } flags;
3977
3978 atomic_t loop_state;
3979 #define LOOP_TIMEOUT 1
3980 #define LOOP_DOWN 2
3981 #define LOOP_UP 3
3982 #define LOOP_UPDATE 4
3983 #define LOOP_READY 5
3984 #define LOOP_DEAD 6
3985
3986 unsigned long dpc_flags;
3987 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3988 #define RESET_ACTIVE 1
3989 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3990 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3991 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3992 #define LOOP_RESYNC_ACTIVE 5
3993 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3994 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
3995 #define RELOGIN_NEEDED 8
3996 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3997 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
3998 #define BEACON_BLINK_NEEDED 11
3999 #define REGISTER_FDMI_NEEDED 12
4000 #define FCPORT_UPDATE_NEEDED 13
4001 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4002 #define UNLOADING 15
4003 #define NPIV_CONFIG_NEEDED 16
4004 #define ISP_UNRECOVERABLE 17
4005 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4006 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4007 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4008 #define FREE_BIT 21
4009 #define PORT_UPDATE_NEEDED 22
4010 #define FX00_RESET_RECOVERY 23
4011 #define FX00_TARGET_SCAN 24
4012 #define FX00_CRITEMP_RECOVERY 25
4013 #define FX00_HOST_INFO_RESEND 26
4014 #define QPAIR_ONLINE_CHECK_NEEDED 27
4015
4016 unsigned long pci_flags;
4017 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4018 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4019 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4020 #define PCI_ERR 30
4021
4022 uint32_t device_flags;
4023 #define SWITCH_FOUND BIT_0
4024 #define DFLG_NO_CABLE BIT_1
4025 #define DFLG_DEV_FAILED BIT_5
4026
4027 /* ISP configuration data. */
4028 uint16_t loop_id; /* Host adapter loop id */
4029 uint16_t self_login_loop_id; /* host adapter loop id
4030 * get it on self login
4031 */
4032 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4033 * no need of allocating it for
4034 * each command
4035 */
4036
4037 port_id_t d_id; /* Host adapter port id */
4038 uint8_t marker_needed;
4039 uint16_t mgmt_svr_loop_id;
4040
4041
4042
4043 /* Timeout timers. */
4044 uint8_t loop_down_abort_time; /* port down timer */
4045 atomic_t loop_down_timer; /* loop down timer */
4046 uint8_t link_down_timeout; /* link down timeout */
4047
4048 uint32_t timer_active;
4049 struct timer_list timer;
4050
4051 uint8_t node_name[WWN_SIZE];
4052 uint8_t port_name[WWN_SIZE];
4053 uint8_t fabric_node_name[WWN_SIZE];
4054
4055 uint16_t fcoe_vlan_id;
4056 uint16_t fcoe_fcf_idx;
4057 uint8_t fcoe_vn_port_mac[6];
4058
4059 /* list of commands waiting on workqueue */
4060 struct list_head qla_cmd_list;
4061 struct list_head qla_sess_op_cmd_list;
4062 struct list_head unknown_atio_list;
4063 spinlock_t cmd_list_lock;
4064 struct delayed_work unknown_atio_work;
4065
4066 /* Counter to detect races between ELS and RSCN events */
4067 atomic_t generation_tick;
4068 /* Time when global fcport update has been scheduled */
4069 int total_fcport_update_gen;
4070 /* List of pending LOGOs, protected by tgt_mutex */
4071 struct list_head logo_list;
4072 /* List of pending PLOGI acks, protected by hw lock */
4073 struct list_head plogi_ack_list;
4074
4075 struct list_head qp_list;
4076
4077 uint32_t vp_abort_cnt;
4078
4079 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4080 uint16_t vp_idx; /* vport ID */
4081 struct qla_qpair *qpair; /* base qpair */
4082
4083 unsigned long vp_flags;
4084 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4085 #define VP_CREATE_NEEDED 1
4086 #define VP_BIND_NEEDED 2
4087 #define VP_DELETE_NEEDED 3
4088 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4089 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4090 atomic_t vp_state;
4091 #define VP_OFFLINE 0
4092 #define VP_ACTIVE 1
4093 #define VP_FAILED 2
4094 // #define VP_DISABLE 3
4095 uint16_t vp_err_state;
4096 uint16_t vp_prev_err_state;
4097 #define VP_ERR_UNKWN 0
4098 #define VP_ERR_PORTDWN 1
4099 #define VP_ERR_FAB_UNSUPPORTED 2
4100 #define VP_ERR_FAB_NORESOURCES 3
4101 #define VP_ERR_FAB_LOGOUT 4
4102 #define VP_ERR_ADAP_NORESOURCES 5
4103 struct qla_hw_data *hw;
4104 struct scsi_qlt_host vha_tgt;
4105 struct req_que *req;
4106 int fw_heartbeat_counter;
4107 int seconds_since_last_heartbeat;
4108 struct fc_host_statistics fc_host_stat;
4109 struct qla_statistics qla_stats;
4110 struct bidi_statistics bidi_stats;
4111
4112 atomic_t vref_count;
4113 struct qla8044_reset_template reset_tmplt;
4114 struct qla_tgt_counters tgt_counters;
4115 uint16_t bbcr;
4116 struct name_list_extended gnl;
4117 /* Count of active session/fcport */
4118 int fcport_count;
4119 wait_queue_head_t fcport_waitQ;
4120 wait_queue_head_t vref_waitq;
4121 } scsi_qla_host_t;
4122
4123 struct qla27xx_image_status {
4124 uint8_t image_status_mask;
4125 uint16_t generation_number;
4126 uint8_t reserved[3];
4127 uint8_t ver_minor;
4128 uint8_t ver_major;
4129 uint32_t checksum;
4130 uint32_t signature;
4131 } __packed;
4132
4133 #define SET_VP_IDX 1
4134 #define SET_AL_PA 2
4135 #define RESET_VP_IDX 3
4136 #define RESET_AL_PA 4
4137 struct qla_tgt_vp_map {
4138 uint8_t idx;
4139 scsi_qla_host_t *vha;
4140 };
4141
4142 struct qla2_sgx {
4143 dma_addr_t dma_addr; /* OUT */
4144 uint32_t dma_len; /* OUT */
4145
4146 uint32_t tot_bytes; /* IN */
4147 struct scatterlist *cur_sg; /* IN */
4148
4149 /* for book keeping, bzero on initial invocation */
4150 uint32_t bytes_consumed;
4151 uint32_t num_bytes;
4152 uint32_t tot_partial;
4153
4154 /* for debugging */
4155 uint32_t num_sg;
4156 srb_t *sp;
4157 };
4158
4159 /*
4160 * Macros to help code, maintain, etc.
4161 */
4162 #define LOOP_TRANSITION(ha) \
4163 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4164 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4165 atomic_read(&ha->loop_state) == LOOP_DOWN)
4166
4167 #define STATE_TRANSITION(ha) \
4168 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4169 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4170
4171 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4172 atomic_inc(&__vha->vref_count); \
4173 mb(); \
4174 if (__vha->flags.delete_progress) { \
4175 atomic_dec(&__vha->vref_count); \
4176 wake_up(&__vha->vref_waitq); \
4177 __bail = 1; \
4178 } else { \
4179 __bail = 0; \
4180 } \
4181 } while (0)
4182
4183 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4184 atomic_dec(&__vha->vref_count); \
4185 wake_up(&__vha->vref_waitq); \
4186 } while (0) \
4187
4188 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4189 atomic_inc(&__qpair->ref_count); \
4190 mb(); \
4191 if (__qpair->delete_in_progress) { \
4192 atomic_dec(&__qpair->ref_count); \
4193 __bail = 1; \
4194 } else { \
4195 __bail = 0; \
4196 } \
4197 } while (0)
4198
4199 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4200 atomic_dec(&__qpair->ref_count); \
4201
4202 /*
4203 * qla2x00 local function return status codes
4204 */
4205 #define MBS_MASK 0x3fff
4206
4207 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4208 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4209 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4210 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4211 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4212 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4213 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4214 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4215 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4216 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4217
4218 #define QLA_FUNCTION_TIMEOUT 0x100
4219 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4220 #define QLA_FUNCTION_FAILED 0x102
4221 #define QLA_MEMORY_ALLOC_FAILED 0x103
4222 #define QLA_LOCK_TIMEOUT 0x104
4223 #define QLA_ABORTED 0x105
4224 #define QLA_SUSPENDED 0x106
4225 #define QLA_BUSY 0x107
4226 #define QLA_ALREADY_REGISTERED 0x109
4227
4228 #define NVRAM_DELAY() udelay(10)
4229
4230 /*
4231 * Flash support definitions
4232 */
4233 #define OPTROM_SIZE_2300 0x20000
4234 #define OPTROM_SIZE_2322 0x100000
4235 #define OPTROM_SIZE_24XX 0x100000
4236 #define OPTROM_SIZE_25XX 0x200000
4237 #define OPTROM_SIZE_81XX 0x400000
4238 #define OPTROM_SIZE_82XX 0x800000
4239 #define OPTROM_SIZE_83XX 0x1000000
4240
4241 #define OPTROM_BURST_SIZE 0x1000
4242 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4243
4244 #define QLA_DSDS_PER_IOCB 37
4245
4246 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4247
4248 #define QLA_SG_ALL 1024
4249
4250 enum nexus_wait_type {
4251 WAIT_HOST = 0,
4252 WAIT_TARGET,
4253 WAIT_LUN,
4254 };
4255
4256 #include "qla_gbl.h"
4257 #include "qla_dbg.h"
4258 #include "qla_inline.h"
4259 #endif
Linux with added FPC-III support