drivers/scsi/ufs/ufshci.h

   1 /*
   2  * Universal Flash Storage Host controller driver
   3  *
   4  * This code is based on drivers/scsi/ufs/ufshci.h
   5  * Copyright (C) 2011-2013 Samsung India Software Operations
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version 2
  14  * of the License, or (at your option) any later version.
  15  * See the COPYING file in the top-level directory or visit
  16  * <http://www.gnu.org/licenses/gpl-2.0.html>
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * This program is provided "AS IS" and "WITH ALL FAULTS" and
  24  * without warranty of any kind. You are solely responsible for
  25  * determining the appropriateness of using and distributing
  26  * the program and assume all risks associated with your exercise
  27  * of rights with respect to the program, including but not limited
  28  * to infringement of third party rights, the risks and costs of
  29  * program errors, damage to or loss of data, programs or equipment,
  30  * and unavailability or interruption of operations. Under no
  31  * circumstances will the contributor of this Program be liable for
  32  * any damages of any kind arising from your use or distribution of
  33  * this program.
  34  */
  35
  36 #ifndef _UFSHCI_H
  37 #define _UFSHCI_H
  38
  39 enum {
  40         TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  41         TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  42         ALIGNED_UPIU_SIZE               = 512,
  43 };
  44
  45 /* UFSHCI Registers */
  46 enum {
  47         REG_CONTROLLER_CAPABILITIES             = 0x00,
  48         REG_UFS_VERSION                         = 0x08,
  49         REG_CONTROLLER_DEV_ID                   = 0x10,
  50         REG_CONTROLLER_PROD_ID                  = 0x14,
  51         REG_INTERRUPT_STATUS                    = 0x20,
  52         REG_INTERRUPT_ENABLE                    = 0x24,
  53         REG_CONTROLLER_STATUS                   = 0x30,
  54         REG_CONTROLLER_ENABLE                   = 0x34,
  55         REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  56         REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  57         REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  58         REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  59         REG_UIC_ERROR_CODE_DME                  = 0x48,
  60         REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  61         REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  62         REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  63         REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  64         REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  65         REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  66         REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  67         REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  68         REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  69         REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  70         REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  71         REG_UIC_COMMAND                         = 0x90,
  72         REG_UIC_COMMAND_ARG_1                   = 0x94,
  73         REG_UIC_COMMAND_ARG_2                   = 0x98,
  74         REG_UIC_COMMAND_ARG_3                   = 0x9C,
  75
  76         UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  77
  78         REG_UFS_CCAP                            = 0x100,
  79         REG_UFS_CRYPTOCAP                       = 0x104,
  80
  81         UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  82 };
  83
  84 /* Controller capability masks */
  85 enum {
  86         MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  87         MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  88         MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  89         MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  90         MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  91 };
  92
  93 #define UFS_MASK(mask, offset)          ((mask) << (offset))
  94
  95 /* UFS Version 08h */
  96 #define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
  97 #define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
  98
  99 /* Controller UFSHCI version */
 100 enum {
 101         UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
 102         UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
 103         UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
 104         UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
 105 };
 106
 107 /*
 108  * HCDDID - Host Controller Identification Descriptor
 109  *        - Device ID and Device Class 10h
 110  */
 111 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
 112 #define DEVICE_ID       UFS_MASK(0xFF, 24)
 113
 114 /*
 115  * HCPMID - Host Controller Identification Descriptor
 116  *        - Product/Manufacturer ID  14h
 117  */
 118 #define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 119 #define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 120
 121 #define UFS_BIT(x)      (1L << (x))
 122
 123 #define UTP_TRANSFER_REQ_COMPL                  UFS_BIT(0)
 124 #define UIC_DME_END_PT_RESET                    UFS_BIT(1)
 125 #define UIC_ERROR                               UFS_BIT(2)
 126 #define UIC_TEST_MODE                           UFS_BIT(3)
 127 #define UIC_POWER_MODE                          UFS_BIT(4)
 128 #define UIC_HIBERNATE_EXIT                      UFS_BIT(5)
 129 #define UIC_HIBERNATE_ENTER                     UFS_BIT(6)
 130 #define UIC_LINK_LOST                           UFS_BIT(7)
 131 #define UIC_LINK_STARTUP                        UFS_BIT(8)
 132 #define UTP_TASK_REQ_COMPL                      UFS_BIT(9)
 133 #define UIC_COMMAND_COMPL                       UFS_BIT(10)
 134 #define DEVICE_FATAL_ERROR                      UFS_BIT(11)
 135 #define CONTROLLER_FATAL_ERROR                  UFS_BIT(16)
 136 #define SYSTEM_BUS_FATAL_ERROR                  UFS_BIT(17)
 137
 138 #define UFSHCD_UIC_PWR_MASK     (UIC_HIBERNATE_ENTER |\
 139                                 UIC_HIBERNATE_EXIT |\
 140                                 UIC_POWER_MODE)
 141
 142 #define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 143
 144 #define UFSHCD_ERROR_MASK       (UIC_ERROR |\
 145                                 DEVICE_FATAL_ERROR |\
 146                                 CONTROLLER_FATAL_ERROR |\
 147                                 SYSTEM_BUS_FATAL_ERROR)
 148
 149 #define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 150                                 CONTROLLER_FATAL_ERROR |\
 151                                 SYSTEM_BUS_FATAL_ERROR)
 152
 153 /* HCS - Host Controller Status 30h */
 154 #define DEVICE_PRESENT                          UFS_BIT(0)
 155 #define UTP_TRANSFER_REQ_LIST_READY             UFS_BIT(1)
 156 #define UTP_TASK_REQ_LIST_READY                 UFS_BIT(2)
 157 #define UIC_COMMAND_READY                       UFS_BIT(3)
 158 #define HOST_ERROR_INDICATOR                    UFS_BIT(4)
 159 #define DEVICE_ERROR_INDICATOR                  UFS_BIT(5)
 160 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 161
 162 enum {
 163         PWR_OK          = 0x0,
 164         PWR_LOCAL       = 0x01,
 165         PWR_REMOTE      = 0x02,
 166         PWR_BUSY        = 0x03,
 167         PWR_ERROR_CAP   = 0x04,
 168         PWR_FATAL_ERROR = 0x05,
 169 };
 170
 171 /* HCE - Host Controller Enable 34h */
 172 #define CONTROLLER_ENABLE       UFS_BIT(0)
 173 #define CONTROLLER_DISABLE      0x0
 174
 175 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 176 #define UIC_PHY_ADAPTER_LAYER_ERROR                     UFS_BIT(31)
 177 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 178 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 179
 180 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 181 #define UIC_DATA_LINK_LAYER_ERROR               UFS_BIT(31)
 182 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0x7FFF
 183 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       0x2000
 184 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 185 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 186
 187 /* UECN - Host UIC Error Code Network Layer 40h */
 188 #define UIC_NETWORK_LAYER_ERROR                 UFS_BIT(31)
 189 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 190
 191 /* UECT - Host UIC Error Code Transport Layer 44h */
 192 #define UIC_TRANSPORT_LAYER_ERROR               UFS_BIT(31)
 193 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 194
 195 /* UECDME - Host UIC Error Code DME 48h */
 196 #define UIC_DME_ERROR                   UFS_BIT(31)
 197 #define UIC_DME_ERROR_CODE_MASK         0x1
 198
 199 #define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 200 #define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 201 #define INT_AGGR_COUNTER_AND_TIMER_RESET        UFS_BIT(16)
 202 #define INT_AGGR_STATUS_BIT                     UFS_BIT(20)
 203 #define INT_AGGR_PARAM_WRITE                    UFS_BIT(24)
 204 #define INT_AGGR_ENABLE                         UFS_BIT(31)
 205
 206 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 207 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      UFS_BIT(0)
 208
 209 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 210 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT          UFS_BIT(0)
 211
 212 /* UICCMD - UIC Command */
 213 #define COMMAND_OPCODE_MASK             0xFF
 214 #define GEN_SELECTOR_INDEX_MASK         0xFFFF
 215
 216 #define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 217 #define RESET_LEVEL                     0xFF
 218
 219 #define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 220 #define CONFIG_RESULT_CODE_MASK         0xFF
 221 #define GENERIC_ERROR_CODE_MASK         0xFF
 222
 223 /* GenSelectorIndex calculation macros for M-PHY attributes */
 224 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 225 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 226
 227 #define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 228                                          ((sel) & 0xFFFF))
 229 #define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 230 #define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 231 #define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 232
 233 /* Link Status*/
 234 enum link_status {
 235         UFSHCD_LINK_IS_DOWN     = 1,
 236         UFSHCD_LINK_IS_UP       = 2,
 237 };
 238
 239 /* UIC Commands */
 240 enum uic_cmd_dme {
 241         UIC_CMD_DME_GET                 = 0x01,
 242         UIC_CMD_DME_SET                 = 0x02,
 243         UIC_CMD_DME_PEER_GET            = 0x03,
 244         UIC_CMD_DME_PEER_SET            = 0x04,
 245         UIC_CMD_DME_POWERON             = 0x10,
 246         UIC_CMD_DME_POWEROFF            = 0x11,
 247         UIC_CMD_DME_ENABLE              = 0x12,
 248         UIC_CMD_DME_RESET               = 0x14,
 249         UIC_CMD_DME_END_PT_RST          = 0x15,
 250         UIC_CMD_DME_LINK_STARTUP        = 0x16,
 251         UIC_CMD_DME_HIBER_ENTER         = 0x17,
 252         UIC_CMD_DME_HIBER_EXIT          = 0x18,
 253         UIC_CMD_DME_TEST_MODE           = 0x1A,
 254 };
 255
 256 /* UIC Config result code / Generic error code */
 257 enum {
 258         UIC_CMD_RESULT_SUCCESS                  = 0x00,
 259         UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 260         UIC_CMD_RESULT_FAILURE                  = 0x01,
 261         UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 262         UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 263         UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 264         UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 265         UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 266         UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 267         UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 268         UIC_CMD_RESULT_BUSY                     = 0x09,
 269         UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 270 };
 271
 272 #define MASK_UIC_COMMAND_RESULT                 0xFF
 273
 274 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 275 #define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 276
 277 /* Interrupt disable masks */
 278 enum {
 279         /* Interrupt disable mask for UFSHCI v1.0 */
 280         INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 281         INTERRUPT_MASK_RW_VER_10        = 0x30000,
 282
 283         /* Interrupt disable mask for UFSHCI v1.1 */
 284         INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 285
 286         /* Interrupt disable mask for UFSHCI v2.1 */
 287         INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 288 };
 289
 290 /*
 291  * Request Descriptor Definitions
 292  */
 293
 294 /* Transfer request command type */
 295 enum {
 296         UTP_CMD_TYPE_SCSI               = 0x0,
 297         UTP_CMD_TYPE_UFS                = 0x1,
 298         UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 299 };
 300
 301 /* To accommodate UFS2.0 required Command type */
 302 enum {
 303         UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 304 };
 305
 306 enum {
 307         UTP_SCSI_COMMAND                = 0x00000000,
 308         UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 309         UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 310         UTP_REQ_DESC_INT_CMD            = 0x01000000,
 311 };
 312
 313 /* UTP Transfer Request Data Direction (DD) */
 314 enum {
 315         UTP_NO_DATA_TRANSFER    = 0x00000000,
 316         UTP_HOST_TO_DEVICE      = 0x02000000,
 317         UTP_DEVICE_TO_HOST      = 0x04000000,
 318 };
 319
 320 /* Overall command status values */
 321 enum {
 322         OCS_SUCCESS                     = 0x0,
 323         OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 324         OCS_INVALID_PRDT_ATTR           = 0x2,
 325         OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 326         OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 327         OCS_PEER_COMM_FAILURE           = 0x5,
 328         OCS_ABORTED                     = 0x6,
 329         OCS_FATAL_ERROR                 = 0x7,
 330         OCS_INVALID_COMMAND_STATUS      = 0x0F,
 331         MASK_OCS                        = 0x0F,
 332 };
 333
 334 /* The maximum length of the data byte count field in the PRDT is 256KB */
 335 #define PRDT_DATA_BYTE_COUNT_MAX        (256 * 1024)
 336 /* The granularity of the data byte count field in the PRDT is 32-bit */
 337 #define PRDT_DATA_BYTE_COUNT_PAD        4
 338
 339 /**
 340  * struct ufshcd_sg_entry - UFSHCI PRD Entry
 341  * @base_addr: Lower 32bit physical address DW-0
 342  * @upper_addr: Upper 32bit physical address DW-1
 343  * @reserved: Reserved for future use DW-2
 344  * @size: size of physical segment DW-3
 345  */
 346 struct ufshcd_sg_entry {
 347         __le32    base_addr;
 348         __le32    upper_addr;
 349         __le32    reserved;
 350         __le32    size;
 351 };
 352
 353 /**
 354  * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
 355  * @command_upiu: Command UPIU Frame address
 356  * @response_upiu: Response UPIU Frame address
 357  * @prd_table: Physical Region Descriptor
 358  */
 359 struct utp_transfer_cmd_desc {
 360         u8 command_upiu[ALIGNED_UPIU_SIZE];
 361         u8 response_upiu[ALIGNED_UPIU_SIZE];
 362         struct ufshcd_sg_entry    prd_table[SG_ALL];
 363 };
 364
 365 /**
 366  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 367  * @dword0: Descriptor Header DW0
 368  * @dword1: Descriptor Header DW1
 369  * @dword2: Descriptor Header DW2
 370  * @dword3: Descriptor Header DW3
 371  */
 372 struct request_desc_header {
 373         __le32 dword_0;
 374         __le32 dword_1;
 375         __le32 dword_2;
 376         __le32 dword_3;
 377 };
 378
 379 /**
 380  * struct utp_transfer_req_desc - UTRD structure
 381  * @header: UTRD header DW-0 to DW-3
 382  * @command_desc_base_addr_lo: UCD base address low DW-4
 383  * @command_desc_base_addr_hi: UCD base address high DW-5
 384  * @response_upiu_length: response UPIU length DW-6
 385  * @response_upiu_offset: response UPIU offset DW-6
 386  * @prd_table_length: Physical region descriptor length DW-7
 387  * @prd_table_offset: Physical region descriptor offset DW-7
 388  */
 389 struct utp_transfer_req_desc {
 390
 391         /* DW 0-3 */
 392         struct request_desc_header header;
 393
 394         /* DW 4-5*/
 395         __le32  command_desc_base_addr_lo;
 396         __le32  command_desc_base_addr_hi;
 397
 398         /* DW 6 */
 399         __le16  response_upiu_length;
 400         __le16  response_upiu_offset;
 401
 402         /* DW 7 */
 403         __le16  prd_table_length;
 404         __le16  prd_table_offset;
 405 };
 406
 407 /**
 408  * struct utp_task_req_desc - UTMRD structure
 409  * @header: UTMRD header DW-0 to DW-3
 410  * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
 411  * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
 412  */
 413 struct utp_task_req_desc {
 414
 415         /* DW 0-3 */
 416         struct request_desc_header header;
 417
 418         /* DW 4-11 */
 419         __le32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
 420
 421         /* DW 12-19 */
 422         __le32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
 423 };
 424
 425 #endif /* End of Header */