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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / drivers / spi / spi-bcm-qspi.c
blobb19722ba908c1be3855e42d21b25f2e6fb38eae8
1 /*
2 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
3 *
4 * Copyright 2016 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation (the "GPL").
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License version 2 (GPLv2) for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * version 2 (GPLv2) along with this source code.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/ioport.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/sysfs.h>
35 #include <linux/types.h>
36 #include "spi-bcm-qspi.h"
37
38 #define DRIVER_NAME "bcm_qspi"
39
40
41 /* BSPI register offsets */
42 #define BSPI_REVISION_ID 0x000
43 #define BSPI_SCRATCH 0x004
44 #define BSPI_MAST_N_BOOT_CTRL 0x008
45 #define BSPI_BUSY_STATUS 0x00c
46 #define BSPI_INTR_STATUS 0x010
47 #define BSPI_B0_STATUS 0x014
48 #define BSPI_B0_CTRL 0x018
49 #define BSPI_B1_STATUS 0x01c
50 #define BSPI_B1_CTRL 0x020
51 #define BSPI_STRAP_OVERRIDE_CTRL 0x024
52 #define BSPI_FLEX_MODE_ENABLE 0x028
53 #define BSPI_BITS_PER_CYCLE 0x02c
54 #define BSPI_BITS_PER_PHASE 0x030
55 #define BSPI_CMD_AND_MODE_BYTE 0x034
56 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
57 #define BSPI_BSPI_XOR_VALUE 0x03c
58 #define BSPI_BSPI_XOR_ENABLE 0x040
59 #define BSPI_BSPI_PIO_MODE_ENABLE 0x044
60 #define BSPI_BSPI_PIO_IODIR 0x048
61 #define BSPI_BSPI_PIO_DATA 0x04c
62
63 /* RAF register offsets */
64 #define BSPI_RAF_START_ADDR 0x100
65 #define BSPI_RAF_NUM_WORDS 0x104
66 #define BSPI_RAF_CTRL 0x108
67 #define BSPI_RAF_FULLNESS 0x10c
68 #define BSPI_RAF_WATERMARK 0x110
69 #define BSPI_RAF_STATUS 0x114
70 #define BSPI_RAF_READ_DATA 0x118
71 #define BSPI_RAF_WORD_CNT 0x11c
72 #define BSPI_RAF_CURR_ADDR 0x120
73
74 /* Override mode masks */
75 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
76 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
77 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
78 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
79 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
80
81 #define BSPI_ADDRLEN_3BYTES 3
82 #define BSPI_ADDRLEN_4BYTES 4
83
84 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
85
86 #define BSPI_RAF_CTRL_START_MASK BIT(0)
87 #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
88
89 #define BSPI_BPP_MODE_SELECT_MASK BIT(8)
90 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
91
92 #define BSPI_READ_LENGTH 512
93
94 /* MSPI register offsets */
95 #define MSPI_SPCR0_LSB 0x000
96 #define MSPI_SPCR0_MSB 0x004
97 #define MSPI_SPCR1_LSB 0x008
98 #define MSPI_SPCR1_MSB 0x00c
99 #define MSPI_NEWQP 0x010
100 #define MSPI_ENDQP 0x014
101 #define MSPI_SPCR2 0x018
102 #define MSPI_MSPI_STATUS 0x020
103 #define MSPI_CPTQP 0x024
104 #define MSPI_SPCR3 0x028
105 #define MSPI_TXRAM 0x040
106 #define MSPI_RXRAM 0x0c0
107 #define MSPI_CDRAM 0x140
108 #define MSPI_WRITE_LOCK 0x180
109
110 #define MSPI_MASTER_BIT BIT(7)
111
112 #define MSPI_NUM_CDRAM 16
113 #define MSPI_CDRAM_CONT_BIT BIT(7)
114 #define MSPI_CDRAM_BITSE_BIT BIT(6)
115 #define MSPI_CDRAM_PCS 0xf
116
117 #define MSPI_SPCR2_SPE BIT(6)
118 #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
119
120 #define MSPI_MSPI_STATUS_SPIF BIT(0)
121
122 #define INTR_BASE_BIT_SHIFT 0x02
123 #define INTR_COUNT 0x07
124
125 #define NUM_CHIPSELECT 4
126 #define QSPI_SPBR_MIN 8U
127 #define QSPI_SPBR_MAX 255U
128
129 #define OPCODE_DIOR 0xBB
130 #define OPCODE_QIOR 0xEB
131 #define OPCODE_DIOR_4B 0xBC
132 #define OPCODE_QIOR_4B 0xEC
133
134 #define MAX_CMD_SIZE 6
135
136 #define ADDR_4MB_MASK GENMASK(22, 0)
137
138 /* stop at end of transfer, no other reason */
139 #define TRANS_STATUS_BREAK_NONE 0
140 /* stop at end of spi_message */
141 #define TRANS_STATUS_BREAK_EOM 1
142 /* stop at end of spi_transfer if delay */
143 #define TRANS_STATUS_BREAK_DELAY 2
144 /* stop at end of spi_transfer if cs_change */
145 #define TRANS_STATUS_BREAK_CS_CHANGE 4
146 /* stop if we run out of bytes */
147 #define TRANS_STATUS_BREAK_NO_BYTES 8
148
149 /* events that make us stop filling TX slots */
150 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
151 TRANS_STATUS_BREAK_DELAY | \
152 TRANS_STATUS_BREAK_CS_CHANGE)
153
154 /* events that make us deassert CS */
155 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
156 TRANS_STATUS_BREAK_CS_CHANGE)
157
158 struct bcm_qspi_parms {
159 u32 speed_hz;
160 u8 mode;
161 u8 bits_per_word;
162 };
163
164 struct bcm_xfer_mode {
165 bool flex_mode;
166 unsigned int width;
167 unsigned int addrlen;
168 unsigned int hp;
169 };
170
171 enum base_type {
172 MSPI,
173 BSPI,
174 CHIP_SELECT,
175 BASEMAX,
176 };
177
178 enum irq_source {
179 SINGLE_L2,
180 MUXED_L1,
181 };
182
183 struct bcm_qspi_irq {
184 const char *irq_name;
185 const irq_handler_t irq_handler;
186 int irq_source;
187 u32 mask;
188 };
189
190 struct bcm_qspi_dev_id {
191 const struct bcm_qspi_irq *irqp;
192 void *dev;
193 };
194
195
196 struct qspi_trans {
197 struct spi_transfer *trans;
198 int byte;
199 bool mspi_last_trans;
200 };
201
202 struct bcm_qspi {
203 struct platform_device *pdev;
204 struct spi_master *master;
205 struct clk *clk;
206 u32 base_clk;
207 u32 max_speed_hz;
208 void __iomem *base[BASEMAX];
209
210 /* Some SoCs provide custom interrupt status register(s) */
211 struct bcm_qspi_soc_intc *soc_intc;
212
213 struct bcm_qspi_parms last_parms;
214 struct qspi_trans trans_pos;
215 int curr_cs;
216 int bspi_maj_rev;
217 int bspi_min_rev;
218 int bspi_enabled;
219 struct spi_flash_read_message *bspi_rf_msg;
220 u32 bspi_rf_msg_idx;
221 u32 bspi_rf_msg_len;
222 u32 bspi_rf_msg_status;
223 struct bcm_xfer_mode xfer_mode;
224 u32 s3_strap_override_ctrl;
225 bool bspi_mode;
226 bool big_endian;
227 int num_irqs;
228 struct bcm_qspi_dev_id *dev_ids;
229 struct completion mspi_done;
230 struct completion bspi_done;
231 };
232
233 static inline bool has_bspi(struct bcm_qspi *qspi)
234 {
235 return qspi->bspi_mode;
236 }
237
238 /* Read qspi controller register*/
239 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
240 unsigned int offset)
241 {
242 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
243 }
244
245 /* Write qspi controller register*/
246 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
247 unsigned int offset, unsigned int data)
248 {
249 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
250 }
251
252 /* BSPI helpers */
253 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
254 {
255 int i;
256
257 /* this should normally finish within 10us */
258 for (i = 0; i < 1000; i++) {
259 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
260 return 0;
261 udelay(1);
262 }
263 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
264 return -EIO;
265 }
266
267 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
268 {
269 if (qspi->bspi_maj_rev < 4)
270 return true;
271 return false;
272 }
273
274 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
275 {
276 bcm_qspi_bspi_busy_poll(qspi);
277 /* Force rising edge for the b0/b1 'flush' field */
278 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
279 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
280 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
281 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
282 }
283
284 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
285 {
286 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
287 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
288 }
289
290 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
291 {
292 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
293
294 /* BSPI v3 LR is LE only, convert data to host endianness */
295 if (bcm_qspi_bspi_ver_three(qspi))
296 data = le32_to_cpu(data);
297
298 return data;
299 }
300
301 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
302 {
303 bcm_qspi_bspi_busy_poll(qspi);
304 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
305 BSPI_RAF_CTRL_START_MASK);
306 }
307
308 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
309 {
310 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
311 BSPI_RAF_CTRL_CLEAR_MASK);
312 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
313 }
314
315 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
316 {
317 u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
318 u32 data = 0;
319
320 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
321 qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
322 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
323 data = bcm_qspi_bspi_lr_read_fifo(qspi);
324 if (likely(qspi->bspi_rf_msg_len >= 4) &&
325 IS_ALIGNED((uintptr_t)buf, 4)) {
326 buf[qspi->bspi_rf_msg_idx++] = data;
327 qspi->bspi_rf_msg_len -= 4;
328 } else {
329 /* Read out remaining bytes, make sure*/
330 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
331
332 data = cpu_to_le32(data);
333 while (qspi->bspi_rf_msg_len) {
334 *cbuf++ = (u8)data;
335 data >>= 8;
336 qspi->bspi_rf_msg_len--;
337 }
338 }
339 }
340 }
341
342 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
343 int bpp, int bpc, int flex_mode)
344 {
345 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
346 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
347 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
348 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
349 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
350 }
351
352 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width,
353 int addrlen, int hp)
354 {
355 int bpc = 0, bpp = 0;
356 u8 command = SPINOR_OP_READ_FAST;
357 int flex_mode = 1, rv = 0;
358 bool spans_4byte = false;
359
360 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
361 width, addrlen, hp);
362
363 if (addrlen == BSPI_ADDRLEN_4BYTES) {
364 bpp = BSPI_BPP_ADDR_SELECT_MASK;
365 spans_4byte = true;
366 }
367
368 bpp |= 8;
369
370 switch (width) {
371 case SPI_NBITS_SINGLE:
372 if (addrlen == BSPI_ADDRLEN_3BYTES)
373 /* default mode, does not need flex_cmd */
374 flex_mode = 0;
375 else
376 command = SPINOR_OP_READ_FAST_4B;
377 break;
378 case SPI_NBITS_DUAL:
379 bpc = 0x00000001;
380 if (hp) {
381 bpc |= 0x00010100; /* address and mode are 2-bit */
382 bpp = BSPI_BPP_MODE_SELECT_MASK;
383 command = OPCODE_DIOR;
384 if (spans_4byte)
385 command = OPCODE_DIOR_4B;
386 } else {
387 command = SPINOR_OP_READ_1_1_2;
388 if (spans_4byte)
389 command = SPINOR_OP_READ_1_1_2_4B;
390 }
391 break;
392 case SPI_NBITS_QUAD:
393 bpc = 0x00000002;
394 if (hp) {
395 bpc |= 0x00020200; /* address and mode are 4-bit */
396 bpp = 4; /* dummy cycles */
397 bpp |= BSPI_BPP_ADDR_SELECT_MASK;
398 command = OPCODE_QIOR;
399 if (spans_4byte)
400 command = OPCODE_QIOR_4B;
401 } else {
402 command = SPINOR_OP_READ_1_1_4;
403 if (spans_4byte)
404 command = SPINOR_OP_READ_1_1_4_4B;
405 }
406 break;
407 default:
408 rv = -EINVAL;
409 break;
410 }
411
412 if (rv == 0)
413 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc,
414 flex_mode);
415
416 return rv;
417 }
418
419 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
420 int addrlen, int hp)
421 {
422 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
423
424 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
425 width, addrlen, hp);
426
427 switch (width) {
428 case SPI_NBITS_SINGLE:
429 /* clear quad/dual mode */
430 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
431 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
432 break;
433
434 case SPI_NBITS_QUAD:
435 /* clear dual mode and set quad mode */
436 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
437 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
438 break;
439 case SPI_NBITS_DUAL:
440 /* clear quad mode set dual mode */
441 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
442 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
443 break;
444 default:
445 return -EINVAL;
446 }
447
448 if (addrlen == BSPI_ADDRLEN_4BYTES)
449 /* set 4byte mode*/
450 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
451 else
452 /* clear 4 byte mode */
453 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
454
455 /* set the override mode */
456 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
457 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
458 bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0);
459
460 return 0;
461 }
462
463 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
464 int width, int addrlen, int hp)
465 {
466 int error = 0;
467
468 /* default mode */
469 qspi->xfer_mode.flex_mode = true;
470
471 if (!bcm_qspi_bspi_ver_three(qspi)) {
472 u32 val, mask;
473
474 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
475 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
476 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
477 qspi->xfer_mode.flex_mode = false;
478 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE,
479 0);
480
481 if ((val | qspi->s3_strap_override_ctrl) &
482 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL)
483 width = SPI_NBITS_DUAL;
484 else if ((val | qspi->s3_strap_override_ctrl) &
485 BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD)
486 width = SPI_NBITS_QUAD;
487
488 error = bcm_qspi_bspi_set_override(qspi, width, addrlen,
489 hp);
490 }
491 }
492
493 if (qspi->xfer_mode.flex_mode)
494 error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp);
495
496 if (error) {
497 dev_warn(&qspi->pdev->dev,
498 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
499 width, addrlen, hp);
500 } else if (qspi->xfer_mode.width != width ||
501 qspi->xfer_mode.addrlen != addrlen ||
502 qspi->xfer_mode.hp != hp) {
503 qspi->xfer_mode.width = width;
504 qspi->xfer_mode.addrlen = addrlen;
505 qspi->xfer_mode.hp = hp;
506 dev_dbg(&qspi->pdev->dev,
507 "cs:%d %d-lane output, %d-byte address%s\n",
508 qspi->curr_cs,
509 qspi->xfer_mode.width,
510 qspi->xfer_mode.addrlen,
511 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
512 }
513
514 return error;
515 }
516
517 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
518 {
519 if (!has_bspi(qspi) || (qspi->bspi_enabled))
520 return;
521
522 qspi->bspi_enabled = 1;
523 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
524 return;
525
526 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
527 udelay(1);
528 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
529 udelay(1);
530 }
531
532 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
533 {
534 if (!has_bspi(qspi) || (!qspi->bspi_enabled))
535 return;
536
537 qspi->bspi_enabled = 0;
538 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
539 return;
540
541 bcm_qspi_bspi_busy_poll(qspi);
542 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
543 udelay(1);
544 }
545
546 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
547 {
548 u32 data = 0;
549
550 if (qspi->curr_cs == cs)
551 return;
552 if (qspi->base[CHIP_SELECT]) {
553 data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
554 data = (data & ~0xff) | (1 << cs);
555 bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
556 usleep_range(10, 20);
557 }
558 qspi->curr_cs = cs;
559 }
560
561 /* MSPI helpers */
562 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
563 const struct bcm_qspi_parms *xp)
564 {
565 u32 spcr, spbr = 0;
566
567 if (xp->speed_hz)
568 spbr = qspi->base_clk / (2 * xp->speed_hz);
569
570 spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
571 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
572
573 spcr = MSPI_MASTER_BIT;
574 /* for 16 bit the data should be zero */
575 if (xp->bits_per_word != 16)
576 spcr |= xp->bits_per_word << 2;
577 spcr |= xp->mode & 3;
578 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
579
580 qspi->last_parms = *xp;
581 }
582
583 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
584 struct spi_device *spi,
585 struct spi_transfer *trans)
586 {
587 struct bcm_qspi_parms xp;
588
589 xp.speed_hz = trans->speed_hz;
590 xp.bits_per_word = trans->bits_per_word;
591 xp.mode = spi->mode;
592
593 bcm_qspi_hw_set_parms(qspi, &xp);
594 }
595
596 static int bcm_qspi_setup(struct spi_device *spi)
597 {
598 struct bcm_qspi_parms *xp;
599
600 if (spi->bits_per_word > 16)
601 return -EINVAL;
602
603 xp = spi_get_ctldata(spi);
604 if (!xp) {
605 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
606 if (!xp)
607 return -ENOMEM;
608 spi_set_ctldata(spi, xp);
609 }
610 xp->speed_hz = spi->max_speed_hz;
611 xp->mode = spi->mode;
612
613 if (spi->bits_per_word)
614 xp->bits_per_word = spi->bits_per_word;
615 else
616 xp->bits_per_word = 8;
617
618 return 0;
619 }
620
621 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
622 struct qspi_trans *qt)
623 {
624 if (qt->mspi_last_trans &&
625 spi_transfer_is_last(qspi->master, qt->trans))
626 return true;
627 else
628 return false;
629 }
630
631 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
632 struct qspi_trans *qt, int flags)
633 {
634 int ret = TRANS_STATUS_BREAK_NONE;
635
636 /* count the last transferred bytes */
637 if (qt->trans->bits_per_word <= 8)
638 qt->byte++;
639 else
640 qt->byte += 2;
641
642 if (qt->byte >= qt->trans->len) {
643 /* we're at the end of the spi_transfer */
644 /* in TX mode, need to pause for a delay or CS change */
645 if (qt->trans->delay_usecs &&
646 (flags & TRANS_STATUS_BREAK_DELAY))
647 ret |= TRANS_STATUS_BREAK_DELAY;
648 if (qt->trans->cs_change &&
649 (flags & TRANS_STATUS_BREAK_CS_CHANGE))
650 ret |= TRANS_STATUS_BREAK_CS_CHANGE;
651 if (ret)
652 goto done;
653
654 dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
655 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
656 ret = TRANS_STATUS_BREAK_EOM;
657 else
658 ret = TRANS_STATUS_BREAK_NO_BYTES;
659
660 qt->trans = NULL;
661 }
662
663 done:
664 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
665 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
666 return ret;
667 }
668
669 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
670 {
671 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
672
673 /* mask out reserved bits */
674 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
675 }
676
677 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
678 {
679 u32 reg_offset = MSPI_RXRAM;
680 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
681 u32 msb_offset = reg_offset + (slot << 3);
682
683 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
684 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
685 }
686
687 static void read_from_hw(struct bcm_qspi *qspi, int slots)
688 {
689 struct qspi_trans tp;
690 int slot;
691
692 bcm_qspi_disable_bspi(qspi);
693
694 if (slots > MSPI_NUM_CDRAM) {
695 /* should never happen */
696 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
697 return;
698 }
699
700 tp = qspi->trans_pos;
701
702 for (slot = 0; slot < slots; slot++) {
703 if (tp.trans->bits_per_word <= 8) {
704 u8 *buf = tp.trans->rx_buf;
705
706 if (buf)
707 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
708 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
709 buf ? buf[tp.byte] : 0xff);
710 } else {
711 u16 *buf = tp.trans->rx_buf;
712
713 if (buf)
714 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
715 slot);
716 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
717 buf ? buf[tp.byte] : 0xffff);
718 }
719
720 update_qspi_trans_byte_count(qspi, &tp,
721 TRANS_STATUS_BREAK_NONE);
722 }
723
724 qspi->trans_pos = tp;
725 }
726
727 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
728 u8 val)
729 {
730 u32 reg_offset = MSPI_TXRAM + (slot << 3);
731
732 /* mask out reserved bits */
733 bcm_qspi_write(qspi, MSPI, reg_offset, val);
734 }
735
736 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
737 u16 val)
738 {
739 u32 reg_offset = MSPI_TXRAM;
740 u32 msb_offset = reg_offset + (slot << 3);
741 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
742
743 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
744 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
745 }
746
747 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
748 {
749 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
750 }
751
752 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
753 {
754 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
755 }
756
757 /* Return number of slots written */
758 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
759 {
760 struct qspi_trans tp;
761 int slot = 0, tstatus = 0;
762 u32 mspi_cdram = 0;
763
764 bcm_qspi_disable_bspi(qspi);
765 tp = qspi->trans_pos;
766 bcm_qspi_update_parms(qspi, spi, tp.trans);
767
768 /* Run until end of transfer or reached the max data */
769 while (!tstatus && slot < MSPI_NUM_CDRAM) {
770 if (tp.trans->bits_per_word <= 8) {
771 const u8 *buf = tp.trans->tx_buf;
772 u8 val = buf ? buf[tp.byte] : 0xff;
773
774 write_txram_slot_u8(qspi, slot, val);
775 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
776 } else {
777 const u16 *buf = tp.trans->tx_buf;
778 u16 val = buf ? buf[tp.byte / 2] : 0xffff;
779
780 write_txram_slot_u16(qspi, slot, val);
781 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
782 }
783 mspi_cdram = MSPI_CDRAM_CONT_BIT;
784 mspi_cdram |= (~(1 << spi->chip_select) &
785 MSPI_CDRAM_PCS);
786 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
787 MSPI_CDRAM_BITSE_BIT);
788
789 write_cdram_slot(qspi, slot, mspi_cdram);
790
791 tstatus = update_qspi_trans_byte_count(qspi, &tp,
792 TRANS_STATUS_BREAK_TX);
793 slot++;
794 }
795
796 if (!slot) {
797 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
798 goto done;
799 }
800
801 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
802 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
803 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
804
805 if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
806 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
807 ~MSPI_CDRAM_CONT_BIT;
808 write_cdram_slot(qspi, slot - 1, mspi_cdram);
809 }
810
811 if (has_bspi(qspi))
812 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
813
814 /* Must flush previous writes before starting MSPI operation */
815 mb();
816 /* Set cont | spe | spifie */
817 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
818
819 done:
820 return slot;
821 }
822
823 static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
824 struct spi_flash_read_message *msg)
825 {
826 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
827 u32 addr = 0, len, rdlen, len_words;
828 int ret = 0;
829 unsigned long timeo = msecs_to_jiffies(100);
830 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
831
832 if (bcm_qspi_bspi_ver_three(qspi))
833 if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
834 return -EIO;
835
836 bcm_qspi_chip_select(qspi, spi->chip_select);
837 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
838
839 /*
840 * when using flex mode we need to send
841 * the upper address byte to bspi
842 */
843 if (bcm_qspi_bspi_ver_three(qspi) == false) {
844 addr = msg->from & 0xff000000;
845 bcm_qspi_write(qspi, BSPI,
846 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
847 }
848
849 if (!qspi->xfer_mode.flex_mode)
850 addr = msg->from;
851 else
852 addr = msg->from & 0x00ffffff;
853
854 if (bcm_qspi_bspi_ver_three(qspi) == true)
855 addr = (addr + 0xc00000) & 0xffffff;
856
857 /*
858 * read into the entire buffer by breaking the reads
859 * into RAF buffer read lengths
860 */
861 len = msg->len;
862 qspi->bspi_rf_msg_idx = 0;
863
864 do {
865 if (len > BSPI_READ_LENGTH)
866 rdlen = BSPI_READ_LENGTH;
867 else
868 rdlen = len;
869
870 reinit_completion(&qspi->bspi_done);
871 bcm_qspi_enable_bspi(qspi);
872 len_words = (rdlen + 3) >> 2;
873 qspi->bspi_rf_msg = msg;
874 qspi->bspi_rf_msg_status = 0;
875 qspi->bspi_rf_msg_len = rdlen;
876 dev_dbg(&qspi->pdev->dev,
877 "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
878 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
879 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
880 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
881 if (qspi->soc_intc) {
882 /*
883 * clear soc MSPI and BSPI interrupts and enable
884 * BSPI interrupts.
885 */
886 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
887 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
888 }
889
890 /* Must flush previous writes before starting BSPI operation */
891 mb();
892 bcm_qspi_bspi_lr_start(qspi);
893 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
894 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
895 ret = -ETIMEDOUT;
896 break;
897 }
898
899 /* set msg return length */
900 msg->retlen += rdlen;
901 addr += rdlen;
902 len -= rdlen;
903 } while (len);
904
905 return ret;
906 }
907
908 static int bcm_qspi_transfer_one(struct spi_master *master,
909 struct spi_device *spi,
910 struct spi_transfer *trans)
911 {
912 struct bcm_qspi *qspi = spi_master_get_devdata(master);
913 int slots;
914 unsigned long timeo = msecs_to_jiffies(100);
915
916 bcm_qspi_chip_select(qspi, spi->chip_select);
917 qspi->trans_pos.trans = trans;
918 qspi->trans_pos.byte = 0;
919
920 while (qspi->trans_pos.byte < trans->len) {
921 reinit_completion(&qspi->mspi_done);
922
923 slots = write_to_hw(qspi, spi);
924 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
925 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
926 return -ETIMEDOUT;
927 }
928
929 read_from_hw(qspi, slots);
930 }
931
932 return 0;
933 }
934
935 static int bcm_qspi_mspi_flash_read(struct spi_device *spi,
936 struct spi_flash_read_message *msg)
937 {
938 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
939 struct spi_transfer t[2];
940 u8 cmd[6];
941 int ret;
942
943 memset(cmd, 0, sizeof(cmd));
944 memset(t, 0, sizeof(t));
945
946 /* tx */
947 /* opcode is in cmd[0] */
948 cmd[0] = msg->read_opcode;
949 cmd[1] = msg->from >> (msg->addr_width * 8 - 8);
950 cmd[2] = msg->from >> (msg->addr_width * 8 - 16);
951 cmd[3] = msg->from >> (msg->addr_width * 8 - 24);
952 cmd[4] = msg->from >> (msg->addr_width * 8 - 32);
953 t[0].tx_buf = cmd;
954 t[0].len = msg->addr_width + msg->dummy_bytes + 1;
955 t[0].bits_per_word = spi->bits_per_word;
956 t[0].tx_nbits = msg->opcode_nbits;
957 /* lets mspi know that this is not last transfer */
958 qspi->trans_pos.mspi_last_trans = false;
959 ret = bcm_qspi_transfer_one(spi->master, spi, &t[0]);
960
961 /* rx */
962 qspi->trans_pos.mspi_last_trans = true;
963 if (!ret) {
964 /* rx */
965 t[1].rx_buf = msg->buf;
966 t[1].len = msg->len;
967 t[1].rx_nbits = msg->data_nbits;
968 t[1].bits_per_word = spi->bits_per_word;
969 ret = bcm_qspi_transfer_one(spi->master, spi, &t[1]);
970 }
971
972 if (!ret)
973 msg->retlen = msg->len;
974
975 return ret;
976 }
977
978 static int bcm_qspi_flash_read(struct spi_device *spi,
979 struct spi_flash_read_message *msg)
980 {
981 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
982 int ret = 0;
983 bool mspi_read = false;
984 u32 io_width, addrlen, addr, len;
985 u_char *buf;
986
987 buf = msg->buf;
988 addr = msg->from;
989 len = msg->len;
990
991 if (bcm_qspi_bspi_ver_three(qspi) == true) {
992 /*
993 * The address coming into this function is a raw flash offset.
994 * But for BSPI <= V3, we need to convert it to a remapped BSPI
995 * address. If it crosses a 4MB boundary, just revert back to
996 * using MSPI.
997 */
998 addr = (addr + 0xc00000) & 0xffffff;
999
1000 if ((~ADDR_4MB_MASK & addr) ^
1001 (~ADDR_4MB_MASK & (addr + len - 1)))
1002 mspi_read = true;
1003 }
1004
1005 /* non-aligned and very short transfers are handled by MSPI */
1006 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
1007 len < 4)
1008 mspi_read = true;
1009
1010 if (mspi_read)
1011 return bcm_qspi_mspi_flash_read(spi, msg);
1012
1013 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
1014 addrlen = msg->addr_width;
1015 ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1);
1016
1017 if (!ret)
1018 ret = bcm_qspi_bspi_flash_read(spi, msg);
1019
1020 return ret;
1021 }
1022
1023 static void bcm_qspi_cleanup(struct spi_device *spi)
1024 {
1025 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1026
1027 kfree(xp);
1028 }
1029
1030 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1031 {
1032 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1033 struct bcm_qspi *qspi = qspi_dev_id->dev;
1034 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1035
1036 if (status & MSPI_MSPI_STATUS_SPIF) {
1037 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1038 /* clear interrupt */
1039 status &= ~MSPI_MSPI_STATUS_SPIF;
1040 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1041 if (qspi->soc_intc)
1042 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1043 complete(&qspi->mspi_done);
1044 return IRQ_HANDLED;
1045 }
1046
1047 return IRQ_NONE;
1048 }
1049
1050 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1051 {
1052 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1053 struct bcm_qspi *qspi = qspi_dev_id->dev;
1054 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1055 u32 status = qspi_dev_id->irqp->mask;
1056
1057 if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
1058 bcm_qspi_bspi_lr_data_read(qspi);
1059 if (qspi->bspi_rf_msg_len == 0) {
1060 qspi->bspi_rf_msg = NULL;
1061 if (qspi->soc_intc) {
1062 /* disable soc BSPI interrupt */
1063 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1064 false);
1065 /* indicate done */
1066 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1067 }
1068
1069 if (qspi->bspi_rf_msg_status)
1070 bcm_qspi_bspi_lr_clear(qspi);
1071 else
1072 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1073 }
1074
1075 if (qspi->soc_intc)
1076 /* clear soc BSPI interrupt */
1077 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1078 }
1079
1080 status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1081 if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
1082 complete(&qspi->bspi_done);
1083
1084 return IRQ_HANDLED;
1085 }
1086
1087 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1088 {
1089 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1090 struct bcm_qspi *qspi = qspi_dev_id->dev;
1091 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1092
1093 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1094 qspi->bspi_rf_msg_status = -EIO;
1095 if (qspi->soc_intc)
1096 /* clear soc interrupt */
1097 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1098
1099 complete(&qspi->bspi_done);
1100 return IRQ_HANDLED;
1101 }
1102
1103 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1104 {
1105 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1106 struct bcm_qspi *qspi = qspi_dev_id->dev;
1107 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1108 irqreturn_t ret = IRQ_NONE;
1109
1110 if (soc_intc) {
1111 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1112
1113 if (status & MSPI_DONE)
1114 ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1115 else if (status & BSPI_DONE)
1116 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1117 else if (status & BSPI_ERR)
1118 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1119 }
1120
1121 return ret;
1122 }
1123
1124 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1125 {
1126 .irq_name = "spi_lr_fullness_reached",
1127 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1128 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1129 },
1130 {
1131 .irq_name = "spi_lr_session_aborted",
1132 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1133 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1134 },
1135 {
1136 .irq_name = "spi_lr_impatient",
1137 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1138 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1139 },
1140 {
1141 .irq_name = "spi_lr_session_done",
1142 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1143 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1144 },
1145 #ifdef QSPI_INT_DEBUG
1146 /* this interrupt is for debug purposes only, dont request irq */
1147 {
1148 .irq_name = "spi_lr_overread",
1149 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1150 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1151 },
1152 #endif
1153 {
1154 .irq_name = "mspi_done",
1155 .irq_handler = bcm_qspi_mspi_l2_isr,
1156 .mask = INTR_MSPI_DONE_MASK,
1157 },
1158 {
1159 .irq_name = "mspi_halted",
1160 .irq_handler = bcm_qspi_mspi_l2_isr,
1161 .mask = INTR_MSPI_HALTED_MASK,
1162 },
1163 {
1164 /* single muxed L1 interrupt source */
1165 .irq_name = "spi_l1_intr",
1166 .irq_handler = bcm_qspi_l1_isr,
1167 .irq_source = MUXED_L1,
1168 .mask = QSPI_INTERRUPTS_ALL,
1169 },
1170 };
1171
1172 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1173 {
1174 u32 val = 0;
1175
1176 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1177 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1178 qspi->bspi_min_rev = val & 0xff;
1179 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1180 /* Force mapping of BSPI address -> flash offset */
1181 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1182 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1183 }
1184 qspi->bspi_enabled = 1;
1185 bcm_qspi_disable_bspi(qspi);
1186 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1187 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1188 }
1189
1190 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1191 {
1192 struct bcm_qspi_parms parms;
1193
1194 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1195 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1196 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1197 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1198 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1199
1200 parms.mode = SPI_MODE_3;
1201 parms.bits_per_word = 8;
1202 parms.speed_hz = qspi->max_speed_hz;
1203 bcm_qspi_hw_set_parms(qspi, &parms);
1204
1205 if (has_bspi(qspi))
1206 bcm_qspi_bspi_init(qspi);
1207 }
1208
1209 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1210 {
1211 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1212 if (has_bspi(qspi))
1213 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1214
1215 }
1216
1217 static const struct of_device_id bcm_qspi_of_match[] = {
1218 { .compatible = "brcm,spi-bcm-qspi" },
1219 {},
1220 };
1221 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1222
1223 int bcm_qspi_probe(struct platform_device *pdev,
1224 struct bcm_qspi_soc_intc *soc_intc)
1225 {
1226 struct device *dev = &pdev->dev;
1227 struct bcm_qspi *qspi;
1228 struct spi_master *master;
1229 struct resource *res;
1230 int irq, ret = 0, num_ints = 0;
1231 u32 val;
1232 const char *name = NULL;
1233 int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1234
1235 /* We only support device-tree instantiation */
1236 if (!dev->of_node)
1237 return -ENODEV;
1238
1239 if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1240 return -ENODEV;
1241
1242 master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
1243 if (!master) {
1244 dev_err(dev, "error allocating spi_master\n");
1245 return -ENOMEM;
1246 }
1247
1248 qspi = spi_master_get_devdata(master);
1249 qspi->pdev = pdev;
1250 qspi->trans_pos.trans = NULL;
1251 qspi->trans_pos.byte = 0;
1252 qspi->trans_pos.mspi_last_trans = true;
1253 qspi->master = master;
1254
1255 master->bus_num = -1;
1256 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1257 master->setup = bcm_qspi_setup;
1258 master->transfer_one = bcm_qspi_transfer_one;
1259 master->spi_flash_read = bcm_qspi_flash_read;
1260 master->cleanup = bcm_qspi_cleanup;
1261 master->dev.of_node = dev->of_node;
1262 master->num_chipselect = NUM_CHIPSELECT;
1263
1264 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1265
1266 if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1267 master->num_chipselect = val;
1268
1269 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1270 if (!res)
1271 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1272 "mspi");
1273
1274 if (res) {
1275 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1276 if (IS_ERR(qspi->base[MSPI])) {
1277 ret = PTR_ERR(qspi->base[MSPI]);
1278 goto qspi_probe_err;
1279 }
1280 } else {
1281 goto qspi_probe_err;
1282 }
1283
1284 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1285 if (res) {
1286 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1287 if (IS_ERR(qspi->base[BSPI])) {
1288 ret = PTR_ERR(qspi->base[BSPI]);
1289 goto qspi_probe_err;
1290 }
1291 qspi->bspi_mode = true;
1292 } else {
1293 qspi->bspi_mode = false;
1294 }
1295
1296 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1297
1298 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1299 if (res) {
1300 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1301 if (IS_ERR(qspi->base[CHIP_SELECT])) {
1302 ret = PTR_ERR(qspi->base[CHIP_SELECT]);
1303 goto qspi_probe_err;
1304 }
1305 }
1306
1307 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1308 GFP_KERNEL);
1309 if (!qspi->dev_ids) {
1310 ret = -ENOMEM;
1311 goto qspi_probe_err;
1312 }
1313
1314 for (val = 0; val < num_irqs; val++) {
1315 irq = -1;
1316 name = qspi_irq_tab[val].irq_name;
1317 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1318 /* get the l2 interrupts */
1319 irq = platform_get_irq_byname(pdev, name);
1320 } else if (!num_ints && soc_intc) {
1321 /* all mspi, bspi intrs muxed to one L1 intr */
1322 irq = platform_get_irq(pdev, 0);
1323 }
1324
1325 if (irq >= 0) {
1326 ret = devm_request_irq(&pdev->dev, irq,
1327 qspi_irq_tab[val].irq_handler, 0,
1328 name,
1329 &qspi->dev_ids[val]);
1330 if (ret < 0) {
1331 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1332 goto qspi_probe_err;
1333 }
1334
1335 qspi->dev_ids[val].dev = qspi;
1336 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1337 num_ints++;
1338 dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1339 qspi_irq_tab[val].irq_name,
1340 irq);
1341 }
1342 }
1343
1344 if (!num_ints) {
1345 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1346 ret = -EINVAL;
1347 goto qspi_probe_err;
1348 }
1349
1350 /*
1351 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1352 * in specific ways
1353 */
1354 if (soc_intc) {
1355 qspi->soc_intc = soc_intc;
1356 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1357 } else {
1358 qspi->soc_intc = NULL;
1359 }
1360
1361 qspi->clk = devm_clk_get(&pdev->dev, NULL);
1362 if (IS_ERR(qspi->clk)) {
1363 dev_warn(dev, "unable to get clock\n");
1364 ret = PTR_ERR(qspi->clk);
1365 goto qspi_probe_err;
1366 }
1367
1368 ret = clk_prepare_enable(qspi->clk);
1369 if (ret) {
1370 dev_err(dev, "failed to prepare clock\n");
1371 goto qspi_probe_err;
1372 }
1373
1374 qspi->base_clk = clk_get_rate(qspi->clk);
1375 qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
1376
1377 bcm_qspi_hw_init(qspi);
1378 init_completion(&qspi->mspi_done);
1379 init_completion(&qspi->bspi_done);
1380 qspi->curr_cs = -1;
1381
1382 platform_set_drvdata(pdev, qspi);
1383
1384 qspi->xfer_mode.width = -1;
1385 qspi->xfer_mode.addrlen = -1;
1386 qspi->xfer_mode.hp = -1;
1387
1388 ret = devm_spi_register_master(&pdev->dev, master);
1389 if (ret < 0) {
1390 dev_err(dev, "can't register master\n");
1391 goto qspi_reg_err;
1392 }
1393
1394 return 0;
1395
1396 qspi_reg_err:
1397 bcm_qspi_hw_uninit(qspi);
1398 clk_disable_unprepare(qspi->clk);
1399 qspi_probe_err:
1400 spi_master_put(master);
1401 kfree(qspi->dev_ids);
1402 return ret;
1403 }
1404 /* probe function to be called by SoC specific platform driver probe */
1405 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1406
1407 int bcm_qspi_remove(struct platform_device *pdev)
1408 {
1409 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1410
1411 bcm_qspi_hw_uninit(qspi);
1412 clk_disable_unprepare(qspi->clk);
1413 kfree(qspi->dev_ids);
1414 spi_unregister_master(qspi->master);
1415
1416 return 0;
1417 }
1418 /* function to be called by SoC specific platform driver remove() */
1419 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1420
1421 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1422 {
1423 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1424
1425 spi_master_suspend(qspi->master);
1426 clk_disable(qspi->clk);
1427 bcm_qspi_hw_uninit(qspi);
1428
1429 return 0;
1430 };
1431
1432 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1433 {
1434 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1435 int ret = 0;
1436
1437 bcm_qspi_hw_init(qspi);
1438 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1439 if (qspi->soc_intc)
1440 /* enable MSPI interrupt */
1441 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1442 true);
1443
1444 ret = clk_enable(qspi->clk);
1445 if (!ret)
1446 spi_master_resume(qspi->master);
1447
1448 return ret;
1449 }
1450
1451 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1452
1453 /* pm_ops to be called by SoC specific platform driver */
1454 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1455
1456 MODULE_AUTHOR("Kamal Dasu");
1457 MODULE_DESCRIPTION("Broadcom QSPI driver");
1458 MODULE_LICENSE("GPL v2");
1459 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support