| blob | 15508adcdfde5451a8d8a230bf0f2e3c29cbd7a4 |
1 /*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5250 clock controller.
10 */
12 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
13 #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
15 /* core clocks */
16 #define CLK_FIN_PLL 1
17 #define CLK_FOUT_APLL 2
18 #define CLK_FOUT_MPLL 3
19 #define CLK_FOUT_BPLL 4
20 #define CLK_FOUT_GPLL 5
21 #define CLK_FOUT_CPLL 6
22 #define CLK_FOUT_EPLL 7
23 #define CLK_FOUT_VPLL 8
24 #define CLK_ARM_CLK 9
26 /* gate for special clocks (sclk) */
27 #define CLK_SCLK_CAM_BAYER 128
28 #define CLK_SCLK_CAM0 129
29 #define CLK_SCLK_CAM1 130
30 #define CLK_SCLK_GSCL_WA 131
31 #define CLK_SCLK_GSCL_WB 132
32 #define CLK_SCLK_FIMD1 133
33 #define CLK_SCLK_MIPI1 134
34 #define CLK_SCLK_DP 135
35 #define CLK_SCLK_HDMI 136
36 #define CLK_SCLK_PIXEL 137
37 #define CLK_SCLK_AUDIO0 138
38 #define CLK_SCLK_MMC0 139
39 #define CLK_SCLK_MMC1 140
40 #define CLK_SCLK_MMC2 141
41 #define CLK_SCLK_MMC3 142
42 #define CLK_SCLK_SATA 143
43 #define CLK_SCLK_USB3 144
44 #define CLK_SCLK_JPEG 145
45 #define CLK_SCLK_UART0 146
46 #define CLK_SCLK_UART1 147
47 #define CLK_SCLK_UART2 148
48 #define CLK_SCLK_UART3 149
49 #define CLK_SCLK_PWM 150
50 #define CLK_SCLK_AUDIO1 151
51 #define CLK_SCLK_AUDIO2 152
52 #define CLK_SCLK_SPDIF 153
53 #define CLK_SCLK_SPI0 154
54 #define CLK_SCLK_SPI1 155
55 #define CLK_SCLK_SPI2 156
56 #define CLK_DIV_I2S1 157
57 #define CLK_DIV_I2S2 158
58 #define CLK_SCLK_HDMIPHY 159
59 #define CLK_DIV_PCM0 160
61 /* gate clocks */
62 #define CLK_GSCL0 256
63 #define CLK_GSCL1 257
64 #define CLK_GSCL2 258
65 #define CLK_GSCL3 259
66 #define CLK_GSCL_WA 260
67 #define CLK_GSCL_WB 261
68 #define CLK_SMMU_GSCL0 262
69 #define CLK_SMMU_GSCL1 263
70 #define CLK_SMMU_GSCL2 264
71 #define CLK_SMMU_GSCL3 265
72 #define CLK_MFC 266
73 #define CLK_SMMU_MFCL 267
74 #define CLK_SMMU_MFCR 268
75 #define CLK_ROTATOR 269
76 #define CLK_JPEG 270
77 #define CLK_MDMA1 271
78 #define CLK_SMMU_ROTATOR 272
79 #define CLK_SMMU_JPEG 273
80 #define CLK_SMMU_MDMA1 274
81 #define CLK_PDMA0 275
82 #define CLK_PDMA1 276
83 #define CLK_SATA 277
84 #define CLK_USBOTG 278
85 #define CLK_MIPI_HSI 279
86 #define CLK_SDMMC0 280
87 #define CLK_SDMMC1 281
88 #define CLK_SDMMC2 282
89 #define CLK_SDMMC3 283
90 #define CLK_SROMC 284
91 #define CLK_USB2 285
92 #define CLK_USB3 286
93 #define CLK_SATA_PHYCTRL 287
94 #define CLK_SATA_PHYI2C 288
95 #define CLK_UART0 289
96 #define CLK_UART1 290
97 #define CLK_UART2 291
98 #define CLK_UART3 292
99 #define CLK_UART4 293
100 #define CLK_I2C0 294
101 #define CLK_I2C1 295
102 #define CLK_I2C2 296
103 #define CLK_I2C3 297
104 #define CLK_I2C4 298
105 #define CLK_I2C5 299
106 #define CLK_I2C6 300
107 #define CLK_I2C7 301
108 #define CLK_I2C_HDMI 302
109 #define CLK_ADC 303
110 #define CLK_SPI0 304
111 #define CLK_SPI1 305
112 #define CLK_SPI2 306
113 #define CLK_I2S1 307
114 #define CLK_I2S2 308
115 #define CLK_PCM1 309
116 #define CLK_PCM2 310
117 #define CLK_PWM 311
118 #define CLK_SPDIF 312
119 #define CLK_AC97 313
120 #define CLK_HSI2C0 314
121 #define CLK_HSI2C1 315
122 #define CLK_HSI2C2 316
123 #define CLK_HSI2C3 317
124 #define CLK_CHIPID 318
125 #define CLK_SYSREG 319
126 #define CLK_PMU 320
127 #define CLK_CMU_TOP 321
128 #define CLK_CMU_CORE 322
129 #define CLK_CMU_MEM 323
130 #define CLK_TZPC0 324
131 #define CLK_TZPC1 325
132 #define CLK_TZPC2 326
133 #define CLK_TZPC3 327
134 #define CLK_TZPC4 328
135 #define CLK_TZPC5 329
136 #define CLK_TZPC6 330
137 #define CLK_TZPC7 331
138 #define CLK_TZPC8 332
139 #define CLK_TZPC9 333
140 #define CLK_HDMI_CEC 334
141 #define CLK_MCT 335
142 #define CLK_WDT 336
143 #define CLK_RTC 337
144 #define CLK_TMU 338
145 #define CLK_FIMD1 339
146 #define CLK_MIE1 340
147 #define CLK_DSIM0 341
148 #define CLK_DP 342
149 #define CLK_MIXER 343
150 #define CLK_HDMI 344
151 #define CLK_G2D 345
152 #define CLK_MDMA0 346
153 #define CLK_SMMU_MDMA0 347
154 #define CLK_SSS 348
155 #define CLK_G3D 349
156 #define CLK_SMMU_TV 350
157 #define CLK_SMMU_FIMD1 351
158 #define CLK_SMMU_2D 352
159 #define CLK_SMMU_FIMC_ISP 353
160 #define CLK_SMMU_FIMC_DRC 354
161 #define CLK_SMMU_FIMC_SCC 355
162 #define CLK_SMMU_FIMC_SCP 356
163 #define CLK_SMMU_FIMC_FD 357
164 #define CLK_SMMU_FIMC_MCU 358
165 #define CLK_SMMU_FIMC_ODC 359
166 #define CLK_SMMU_FIMC_DIS0 360
167 #define CLK_SMMU_FIMC_DIS1 361
168 #define CLK_SMMU_FIMC_3DNR 362
169 #define CLK_SMMU_FIMC_LITE0 363
170 #define CLK_SMMU_FIMC_LITE1 364
171 #define CLK_CAMIF_TOP 365
173 /* mux clocks */
174 #define CLK_MOUT_HDMI 1024
175 #define CLK_MOUT_GPLL 1025
176 #define CLK_MOUT_ACLK200_DISP1_SUB 1026
177 #define CLK_MOUT_ACLK300_DISP1_SUB 1027
179 /* must be greater than maximal clock id */
180 #define CLK_NR_CLKS 1028