| blob | 6dac6c091dd29ad479b0faee396ec55f266bf428 |
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
15 #ifndef _DT_BINDINGS_CLK_MT8135_H
16 #define _DT_BINDINGS_CLK_MT8135_H
18 /* TOPCKGEN */
20 #define CLK_TOP_DSI0_LNTC_DSICLK 1
21 #define CLK_TOP_HDMITX_CLKDIG_CTS 2
22 #define CLK_TOP_CLKPH_MCK 3
23 #define CLK_TOP_CPUM_TCK_IN 4
24 #define CLK_TOP_MAINPLL_806M 5
25 #define CLK_TOP_MAINPLL_537P3M 6
26 #define CLK_TOP_MAINPLL_322P4M 7
27 #define CLK_TOP_MAINPLL_230P3M 8
28 #define CLK_TOP_UNIVPLL_624M 9
29 #define CLK_TOP_UNIVPLL_416M 10
30 #define CLK_TOP_UNIVPLL_249P6M 11
31 #define CLK_TOP_UNIVPLL_178P3M 12
32 #define CLK_TOP_UNIVPLL_48M 13
33 #define CLK_TOP_MMPLL_D2 14
34 #define CLK_TOP_MMPLL_D3 15
35 #define CLK_TOP_MMPLL_D5 16
36 #define CLK_TOP_MMPLL_D7 17
37 #define CLK_TOP_MMPLL_D4 18
38 #define CLK_TOP_MMPLL_D6 19
39 #define CLK_TOP_SYSPLL_D2 20
40 #define CLK_TOP_SYSPLL_D4 21
41 #define CLK_TOP_SYSPLL_D6 22
42 #define CLK_TOP_SYSPLL_D8 23
43 #define CLK_TOP_SYSPLL_D10 24
44 #define CLK_TOP_SYSPLL_D12 25
45 #define CLK_TOP_SYSPLL_D16 26
46 #define CLK_TOP_SYSPLL_D24 27
47 #define CLK_TOP_SYSPLL_D3 28
48 #define CLK_TOP_SYSPLL_D2P5 29
49 #define CLK_TOP_SYSPLL_D5 30
50 #define CLK_TOP_SYSPLL_D3P5 31
51 #define CLK_TOP_UNIVPLL1_D2 32
52 #define CLK_TOP_UNIVPLL1_D4 33
53 #define CLK_TOP_UNIVPLL1_D6 34
54 #define CLK_TOP_UNIVPLL1_D8 35
55 #define CLK_TOP_UNIVPLL1_D10 36
56 #define CLK_TOP_UNIVPLL2_D2 37
57 #define CLK_TOP_UNIVPLL2_D4 38
58 #define CLK_TOP_UNIVPLL2_D6 39
59 #define CLK_TOP_UNIVPLL2_D8 40
60 #define CLK_TOP_UNIVPLL_D3 41
61 #define CLK_TOP_UNIVPLL_D5 42
62 #define CLK_TOP_UNIVPLL_D7 43
63 #define CLK_TOP_UNIVPLL_D10 44
64 #define CLK_TOP_UNIVPLL_D26 45
65 #define CLK_TOP_APLL 46
66 #define CLK_TOP_APLL_D4 47
67 #define CLK_TOP_APLL_D8 48
68 #define CLK_TOP_APLL_D16 49
69 #define CLK_TOP_APLL_D24 50
70 #define CLK_TOP_LVDSPLL_D2 51
71 #define CLK_TOP_LVDSPLL_D4 52
72 #define CLK_TOP_LVDSPLL_D8 53
73 #define CLK_TOP_LVDSTX_CLKDIG_CT 54
74 #define CLK_TOP_VPLL_DPIX 55
75 #define CLK_TOP_TVHDMI_H 56
76 #define CLK_TOP_HDMITX_CLKDIG_D2 57
77 #define CLK_TOP_HDMITX_CLKDIG_D3 58
78 #define CLK_TOP_TVHDMI_D2 59
79 #define CLK_TOP_TVHDMI_D4 60
80 #define CLK_TOP_MEMPLL_MCK_D4 61
81 #define CLK_TOP_AXI_SEL 62
82 #define CLK_TOP_SMI_SEL 63
83 #define CLK_TOP_MFG_SEL 64
84 #define CLK_TOP_IRDA_SEL 65
85 #define CLK_TOP_CAM_SEL 66
86 #define CLK_TOP_AUD_INTBUS_SEL 67
87 #define CLK_TOP_JPG_SEL 68
88 #define CLK_TOP_DISP_SEL 69
89 #define CLK_TOP_MSDC30_1_SEL 70
90 #define CLK_TOP_MSDC30_2_SEL 71
91 #define CLK_TOP_MSDC30_3_SEL 72
92 #define CLK_TOP_MSDC30_4_SEL 73
93 #define CLK_TOP_USB20_SEL 74
94 #define CLK_TOP_VENC_SEL 75
95 #define CLK_TOP_SPI_SEL 76
96 #define CLK_TOP_UART_SEL 77
97 #define CLK_TOP_MEM_SEL 78
98 #define CLK_TOP_CAMTG_SEL 79
99 #define CLK_TOP_AUDIO_SEL 80
100 #define CLK_TOP_FIX_SEL 81
101 #define CLK_TOP_VDEC_SEL 82
102 #define CLK_TOP_DDRPHYCFG_SEL 83
103 #define CLK_TOP_DPILVDS_SEL 84
104 #define CLK_TOP_PMICSPI_SEL 85
105 #define CLK_TOP_MSDC30_0_SEL 86
106 #define CLK_TOP_SMI_MFG_AS_SEL 87
107 #define CLK_TOP_GCPU_SEL 88
108 #define CLK_TOP_DPI1_SEL 89
109 #define CLK_TOP_CCI_SEL 90
110 #define CLK_TOP_APLL_SEL 91
111 #define CLK_TOP_HDMIPLL_SEL 92
112 #define CLK_TOP_NR_CLK 93
114 /* APMIXED_SYS */
116 #define CLK_APMIXED_ARMPLL1 1
117 #define CLK_APMIXED_ARMPLL2 2
118 #define CLK_APMIXED_MAINPLL 3
119 #define CLK_APMIXED_UNIVPLL 4
120 #define CLK_APMIXED_MMPLL 5
121 #define CLK_APMIXED_MSDCPLL 6
122 #define CLK_APMIXED_TVDPLL 7
123 #define CLK_APMIXED_LVDSPLL 8
124 #define CLK_APMIXED_AUDPLL 9
125 #define CLK_APMIXED_VDECPLL 10
126 #define CLK_APMIXED_NR_CLK 11
128 /* INFRA_SYS */
130 #define CLK_INFRA_PMIC_WRAP 1
131 #define CLK_INFRA_PMICSPI 2
132 #define CLK_INFRA_CCIF1_AP_CTRL 3
133 #define CLK_INFRA_CCIF0_AP_CTRL 4
134 #define CLK_INFRA_KP 5
135 #define CLK_INFRA_CPUM 6
136 #define CLK_INFRA_M4U 7
137 #define CLK_INFRA_MFGAXI 8
138 #define CLK_INFRA_DEVAPC 9
139 #define CLK_INFRA_AUDIO 10
140 #define CLK_INFRA_MFG_BUS 11
141 #define CLK_INFRA_SMI 12
142 #define CLK_INFRA_DBGCLK 13
143 #define CLK_INFRA_NR_CLK 14
145 /* PERI_SYS */
147 #define CLK_PERI_I2C5 1
148 #define CLK_PERI_I2C4 2
149 #define CLK_PERI_I2C3 3
150 #define CLK_PERI_I2C2 4
151 #define CLK_PERI_I2C1 5
152 #define CLK_PERI_I2C0 6
153 #define CLK_PERI_UART3 7
154 #define CLK_PERI_UART2 8
155 #define CLK_PERI_UART1 9
156 #define CLK_PERI_UART0 10
157 #define CLK_PERI_IRDA 11
158 #define CLK_PERI_NLI 12
159 #define CLK_PERI_MD_HIF 13
160 #define CLK_PERI_AP_HIF 14
161 #define CLK_PERI_MSDC30_3 15
162 #define CLK_PERI_MSDC30_2 16
163 #define CLK_PERI_MSDC30_1 17
164 #define CLK_PERI_MSDC20_2 18
165 #define CLK_PERI_MSDC20_1 19
166 #define CLK_PERI_AP_DMA 20
167 #define CLK_PERI_USB1 21
168 #define CLK_PERI_USB0 22
169 #define CLK_PERI_PWM 23
170 #define CLK_PERI_PWM7 24
171 #define CLK_PERI_PWM6 25
172 #define CLK_PERI_PWM5 26
173 #define CLK_PERI_PWM4 27
174 #define CLK_PERI_PWM3 28
175 #define CLK_PERI_PWM2 29
176 #define CLK_PERI_PWM1 30
177 #define CLK_PERI_THERM 31
178 #define CLK_PERI_NFI 32
179 #define CLK_PERI_USBSLV 33
180 #define CLK_PERI_USB1_MCU 34
181 #define CLK_PERI_USB0_MCU 35
182 #define CLK_PERI_GCPU 36
183 #define CLK_PERI_FHCTL 37
184 #define CLK_PERI_SPI1 38
185 #define CLK_PERI_AUXADC 39
186 #define CLK_PERI_PERI_PWRAP 40
187 #define CLK_PERI_I2C6 41
188 #define CLK_PERI_UART0_SEL 42
189 #define CLK_PERI_UART1_SEL 43
190 #define CLK_PERI_UART2_SEL 44
191 #define CLK_PERI_UART3_SEL 45
192 #define CLK_PERI_NR_CLK 46