x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / include / dt-bindings / clock / r8a7743-cpg-mssr.h
blobe1d1f3c6a99ea95c72bd3500cead514aef40d3f8
1 /*
2 * Copyright (C) 2016 Cogent Embedded Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9 #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
10 #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
12 #include <dt-bindings/clock/renesas-cpg-mssr.h>
14 /* r8a7743 CPG Core Clocks */
15 #define R8A7743_CLK_Z 0
16 #define R8A7743_CLK_ZG 1
17 #define R8A7743_CLK_ZTR 2
18 #define R8A7743_CLK_ZTRD2 3
19 #define R8A7743_CLK_ZT 4
20 #define R8A7743_CLK_ZX 5
21 #define R8A7743_CLK_ZS 6
22 #define R8A7743_CLK_HP 7
23 #define R8A7743_CLK_B 9
24 #define R8A7743_CLK_LB 10
25 #define R8A7743_CLK_P 11
26 #define R8A7743_CLK_CL 12
27 #define R8A7743_CLK_M2 13
28 #define R8A7743_CLK_ZB3 15
29 #define R8A7743_CLK_ZB3D2 16
30 #define R8A7743_CLK_DDR 17
31 #define R8A7743_CLK_SDH 18
32 #define R8A7743_CLK_SD0 19
33 #define R8A7743_CLK_SD2 20
34 #define R8A7743_CLK_SD3 21
35 #define R8A7743_CLK_MMC0 22
36 #define R8A7743_CLK_MP 23
37 #define R8A7743_CLK_QSPI 26
38 #define R8A7743_CLK_CP 27
39 #define R8A7743_CLK_RCAN 28
40 #define R8A7743_CLK_R 29
41 #define R8A7743_CLK_OSC 30
43 #endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */