include/dt-bindings/clock/r8a7794-clock.h

   1 /*
   2  * Copyright (C) 2014 Renesas Electronics Corporation
   3  * Copyright 2013 Ideas On Board SPRL
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
  12 #define __DT_BINDINGS_CLOCK_R8A7794_H__
  13
  14 /* CPG */
  15 #define R8A7794_CLK_MAIN                0
  16 #define R8A7794_CLK_PLL0                1
  17 #define R8A7794_CLK_PLL1                2
  18 #define R8A7794_CLK_PLL3                3
  19 #define R8A7794_CLK_LB                  4
  20 #define R8A7794_CLK_QSPI                5
  21 #define R8A7794_CLK_SDH                 6
  22 #define R8A7794_CLK_SD0                 7
  23 #define R8A7794_CLK_RCAN                8
  24
  25 /* MSTP0 */
  26 #define R8A7794_CLK_MSIOF0              0
  27
  28 /* MSTP1 */
  29 #define R8A7794_CLK_VCP0                1
  30 #define R8A7794_CLK_VPC0                3
  31 #define R8A7794_CLK_TMU1                11
  32 #define R8A7794_CLK_3DG                 12
  33 #define R8A7794_CLK_2DDMAC              15
  34 #define R8A7794_CLK_FDP1_0              19
  35 #define R8A7794_CLK_TMU3                21
  36 #define R8A7794_CLK_TMU2                22
  37 #define R8A7794_CLK_CMT0                24
  38 #define R8A7794_CLK_TMU0                25
  39 #define R8A7794_CLK_VSP1_DU0            28
  40 #define R8A7794_CLK_VSP1_S              31
  41
  42 /* MSTP2 */
  43 #define R8A7794_CLK_SCIFA2              2
  44 #define R8A7794_CLK_SCIFA1              3
  45 #define R8A7794_CLK_SCIFA0              4
  46 #define R8A7794_CLK_MSIOF2              5
  47 #define R8A7794_CLK_SCIFB0              6
  48 #define R8A7794_CLK_SCIFB1              7
  49 #define R8A7794_CLK_MSIOF1              8
  50 #define R8A7794_CLK_SCIFB2              16
  51 #define R8A7794_CLK_SYS_DMAC1           18
  52 #define R8A7794_CLK_SYS_DMAC0           19
  53
  54 /* MSTP3 */
  55 #define R8A7794_CLK_SDHI2               11
  56 #define R8A7794_CLK_SDHI1               12
  57 #define R8A7794_CLK_SDHI0               14
  58 #define R8A7794_CLK_MMCIF0              15
  59 #define R8A7794_CLK_IIC0                18
  60 #define R8A7794_CLK_IIC1                23
  61 #define R8A7794_CLK_CMT1                29
  62 #define R8A7794_CLK_USBDMAC0            30
  63 #define R8A7794_CLK_USBDMAC1            31
  64
  65 /* MSTP4 */
  66 #define R8A7794_CLK_IRQC                7
  67
  68 /* MSTP5 */
  69 #define R8A7794_CLK_AUDIO_DMAC0         2
  70 #define R8A7794_CLK_PWM                 23
  71
  72 /* MSTP7 */
  73 #define R8A7794_CLK_EHCI                3
  74 #define R8A7794_CLK_HSUSB               4
  75 #define R8A7794_CLK_HSCIF2              13
  76 #define R8A7794_CLK_SCIF5               14
  77 #define R8A7794_CLK_SCIF4               15
  78 #define R8A7794_CLK_HSCIF1              16
  79 #define R8A7794_CLK_HSCIF0              17
  80 #define R8A7794_CLK_SCIF3               18
  81 #define R8A7794_CLK_SCIF2               19
  82 #define R8A7794_CLK_SCIF1               20
  83 #define R8A7794_CLK_SCIF0               21
  84 #define R8A7794_CLK_DU0                 24
  85
  86 /* MSTP8 */
  87 #define R8A7794_CLK_VIN1                10
  88 #define R8A7794_CLK_VIN0                11
  89 #define R8A7794_CLK_ETHERAVB            12
  90 #define R8A7794_CLK_ETHER               13
  91
  92 /* MSTP9 */
  93 #define R8A7794_CLK_GPIO6               5
  94 #define R8A7794_CLK_GPIO5               7
  95 #define R8A7794_CLK_GPIO4               8
  96 #define R8A7794_CLK_GPIO3               9
  97 #define R8A7794_CLK_GPIO2               10
  98 #define R8A7794_CLK_GPIO1               11
  99 #define R8A7794_CLK_GPIO0               12
 100 #define R8A7794_CLK_RCAN1               15
 101 #define R8A7794_CLK_RCAN0               16
 102 #define R8A7794_CLK_QSPI_MOD            17
 103 #define R8A7794_CLK_I2C5                25
 104 #define R8A7794_CLK_I2C4                27
 105 #define R8A7794_CLK_I2C3                28
 106 #define R8A7794_CLK_I2C2                29
 107 #define R8A7794_CLK_I2C1                30
 108 #define R8A7794_CLK_I2C0                31
 109
 110 /* MSTP10 */
 111 #define R8A7794_CLK_SSI_ALL             5
 112 #define R8A7794_CLK_SSI9                6
 113 #define R8A7794_CLK_SSI8                7
 114 #define R8A7794_CLK_SSI7                8
 115 #define R8A7794_CLK_SSI6                9
 116 #define R8A7794_CLK_SSI5                10
 117 #define R8A7794_CLK_SSI4                11
 118 #define R8A7794_CLK_SSI3                12
 119 #define R8A7794_CLK_SSI2                13
 120 #define R8A7794_CLK_SSI1                14
 121 #define R8A7794_CLK_SSI0                15
 122 #define R8A7794_CLK_SCU_ALL             17
 123 #define R8A7794_CLK_SCU_DVC1            18
 124 #define R8A7794_CLK_SCU_DVC0            19
 125 #define R8A7794_CLK_SCU_CTU1_MIX1       20
 126 #define R8A7794_CLK_SCU_CTU0_MIX0       21
 127 #define R8A7794_CLK_SCU_SRC6            25
 128 #define R8A7794_CLK_SCU_SRC5            26
 129 #define R8A7794_CLK_SCU_SRC4            27
 130 #define R8A7794_CLK_SCU_SRC3            28
 131 #define R8A7794_CLK_SCU_SRC2            29
 132 #define R8A7794_CLK_SCU_SRC1            30
 133
 134 /* MSTP11 */
 135 #define R8A7794_CLK_SCIFA3              6
 136 #define R8A7794_CLK_SCIFA4              7
 137 #define R8A7794_CLK_SCIFA5              8
 138
 139 #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */