| blob | 9350a5527a36c9dd05537b9f04792ebfbdb100ca |
1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Shawn Lin <shawn.lin@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
19 /* pll id */
20 #define PLL_APLL 0
21 #define PLL_DPLL 1
22 #define PLL_GPLL 2
23 #define ARMCLK 3
25 /* sclk gates (special clocks) */
26 #define SCLK_SPI0 65
27 #define SCLK_NANDC 67
28 #define SCLK_SDMMC 68
29 #define SCLK_SDIO 69
30 #define SCLK_EMMC 71
31 #define SCLK_UART0 72
32 #define SCLK_UART1 73
33 #define SCLK_UART2 74
34 #define SCLK_I2S0 75
35 #define SCLK_I2S1 76
36 #define SCLK_I2S2 77
37 #define SCLK_TIMER0 78
38 #define SCLK_TIMER1 79
39 #define SCLK_SFC 80
40 #define SCLK_SDMMC_DRV 81
41 #define SCLK_SDIO_DRV 82
42 #define SCLK_EMMC_DRV 83
43 #define SCLK_SDMMC_SAMPLE 84
44 #define SCLK_SDIO_SAMPLE 85
45 #define SCLK_EMMC_SAMPLE 86
47 /* aclk gates */
48 #define ACLK_DMAC 192
49 #define ACLK_PRE 193
50 #define ACLK_CORE 194
51 #define ACLK_ENMCORE 195
53 /* pclk gates */
54 #define PCLK_GPIO1 256
55 #define PCLK_GPIO2 257
56 #define PCLK_GPIO3 258
57 #define PCLK_GRF 259
58 #define PCLK_I2C1 260
59 #define PCLK_I2C2 261
60 #define PCLK_I2C3 262
61 #define PCLK_SPI 263
62 #define PCLK_SFC 264
63 #define PCLK_UART0 265
64 #define PCLK_UART1 266
65 #define PCLK_UART2 267
66 #define PCLK_TSADC 268
67 #define PCLK_PWM 269
68 #define PCLK_TIMER 270
69 #define PCLK_PERI 271
71 /* hclk gates */
72 #define HCLK_I2S0_8CH 320
73 #define HCLK_I2S1_8CH 321
74 #define HCLK_I2S2_2CH 322
75 #define HCLK_NANDC 323
76 #define HCLK_SDMMC 324
77 #define HCLK_SDIO 325
78 #define HCLK_EMMC 326
79 #define HCLK_PERI 327
80 #define HCLK_SFC 328
82 #define CLK_NR_CLKS (HCLK_SFC + 1)
84 /* reset id */
85 #define SRST_CORE_PO_AD 0
86 #define SRST_CORE_AD 1
87 #define SRST_L2_AD 2
88 #define SRST_CPU_NIU_AD 3
89 #define SRST_CORE_PO 4
90 #define SRST_CORE 5
91 #define SRST_L2 6
92 #define SRST_CORE_DBG 8
93 #define PRST_DBG 9
94 #define RST_DAP 10
95 #define PRST_DBG_NIU 11
96 #define ARST_STRC_SYS_AD 15
98 #define SRST_DDRPHY_CLKDIV 16
99 #define SRST_DDRPHY 17
100 #define PRST_DDRPHY 18
101 #define PRST_HDMIPHY 19
102 #define PRST_VDACPHY 20
103 #define PRST_VADCPHY 21
104 #define PRST_MIPI_CSI_PHY 22
105 #define PRST_MIPI_DSI_PHY 23
106 #define PRST_ACODEC 24
107 #define ARST_BUS_NIU 25
108 #define PRST_TOP_NIU 26
109 #define ARST_INTMEM 27
110 #define HRST_ROM 28
111 #define ARST_DMAC 29
112 #define SRST_MSCH_NIU 30
113 #define PRST_MSCH_NIU 31
115 #define PRST_DDRUPCTL 32
116 #define NRST_DDRUPCTL 33
117 #define PRST_DDRMON 34
118 #define HRST_I2S0_8CH 35
119 #define MRST_I2S0_8CH 36
120 #define HRST_I2S1_2CH 37
121 #define MRST_IS21_2CH 38
122 #define HRST_I2S2_2CH 39
123 #define MRST_I2S2_2CH 40
124 #define HRST_CRYPTO 41
125 #define SRST_CRYPTO 42
126 #define PRST_SPI 43
127 #define SRST_SPI 44
128 #define PRST_UART0 45
129 #define PRST_UART1 46
130 #define PRST_UART2 47
132 #define SRST_UART0 48
133 #define SRST_UART1 49
134 #define SRST_UART2 50
135 #define PRST_I2C1 51
136 #define PRST_I2C2 52
137 #define PRST_I2C3 53
138 #define SRST_I2C1 54
139 #define SRST_I2C2 55
140 #define SRST_I2C3 56
141 #define PRST_PWM1 58
142 #define SRST_PWM1 60
143 #define PRST_WDT 61
144 #define PRST_GPIO1 62
145 #define PRST_GPIO2 63
147 #define PRST_GPIO3 64
148 #define PRST_GRF 65
149 #define PRST_EFUSE 66
150 #define PRST_EFUSE512 67
151 #define PRST_TIMER0 68
152 #define SRST_TIMER0 69
153 #define SRST_TIMER1 70
154 #define PRST_TSADC 71
155 #define SRST_TSADC 72
156 #define PRST_SARADC 73
157 #define SRST_SARADC 74
158 #define HRST_SYSBUS 75
159 #define PRST_USBGRF 76
161 #define ARST_PERIPH_NIU 80
162 #define HRST_PERIPH_NIU 81
163 #define PRST_PERIPH_NIU 82
164 #define HRST_PERIPH 83
165 #define HRST_SDMMC 84
166 #define HRST_SDIO 85
167 #define HRST_EMMC 86
168 #define HRST_NANDC 87
169 #define NRST_NANDC 88
170 #define HRST_SFC 89
171 #define SRST_SFC 90
172 #define ARST_GMAC 91
173 #define HRST_OTG 92
174 #define SRST_OTG 93
175 #define SRST_OTG_ADP 94
176 #define HRST_HOST0 95
178 #define HRST_HOST0_AUX 96
179 #define HRST_HOST0_ARB 97
180 #define SRST_HOST0_EHCIPHY 98
181 #define SRST_HOST0_UTMI 99
182 #define SRST_USBPOR 100
183 #define SRST_UTMI0 101
184 #define SRST_UTMI1 102
186 #define ARST_VIO0_NIU 102
187 #define ARST_VIO1_NIU 103
188 #define HRST_VIO_NIU 104
189 #define PRST_VIO_NIU 105
190 #define ARST_VOP 106
191 #define HRST_VOP 107
192 #define DRST_VOP 108
193 #define ARST_IEP 109
194 #define HRST_IEP 110
195 #define ARST_RGA 111
196 #define HRST_RGA 112
197 #define SRST_RGA 113
198 #define PRST_CVBS 114
199 #define PRST_HDMI 115
200 #define SRST_HDMI 116
201 #define PRST_MIPI_DSI 117
203 #define ARST_ISP_NIU 118
204 #define HRST_ISP_NIU 119
205 #define HRST_ISP 120
206 #define SRST_ISP 121
207 #define ARST_VIP0 122
208 #define HRST_VIP0 123
209 #define PRST_VIP0 124
210 #define ARST_VIP1 125
211 #define HRST_VIP1 126
212 #define PRST_VIP1 127
213 #define ARST_VIP2 128
214 #define HRST_VIP2 129
215 #define PRST_VIP2 120
216 #define ARST_VIP3 121
217 #define HRST_VIP3 122
218 #define PRST_VIP4 123
220 #define PRST_CIF1TO4 124
221 #define SRST_CVBS_CLK 125
222 #define HRST_CVBS 126
224 #define ARST_VPU_NIU 140
225 #define HRST_VPU_NIU 141
226 #define ARST_VPU 142
227 #define HRST_VPU 143
228 #define ARST_RKVDEC_NIU 144
229 #define HRST_RKVDEC_NIU 145
230 #define ARST_RKVDEC 146
231 #define HRST_RKVDEC 147
232 #define SRST_RKVDEC_CABAC 148
233 #define SRST_RKVDEC_CORE 149
234 #define ARST_RKVENC_NIU 150
235 #define HRST_RKVENC_NIU 151
236 #define ARST_RKVENC 152
237 #define HRST_RKVENC 153
238 #define SRST_RKVENC_CORE 154
240 #define SRST_DSP_CORE 156
241 #define SRST_DSP_SYS 157
242 #define SRST_DSP_GLOBAL 158
243 #define SRST_DSP_OECM 159
244 #define PRST_DSP_IOP_NIU 160
245 #define ARST_DSP_EPP_NIU 161
246 #define ARST_DSP_EDP_NIU 162
247 #define PRST_DSP_DBG_NIU 163
248 #define PRST_DSP_CFG_NIU 164
249 #define PRST_DSP_GRF 165
250 #define PRST_DSP_MAILBOX 166
251 #define PRST_DSP_INTC 167
252 #define PRST_DSP_PFM_MON 169
253 #define SRST_DSP_PFM_MON 170
254 #define ARST_DSP_EDAP_NIU 171
256 #define SRST_PMU 172
257 #define SRST_PMU_I2C0 173
258 #define PRST_PMU_I2C0 174
259 #define PRST_PMU_GPIO0 175
260 #define PRST_PMU_INTMEM 176
261 #define PRST_PMU_PWM0 177
262 #define SRST_PMU_PWM0 178
263 #define PRST_PMU_GRF 179
264 #define SRST_PMU_NIU 180
265 #define SRST_PMU_PVTM 181
266 #define ARST_DSP_EDP_PERF 184
267 #define ARST_DSP_EPP_PERF 185