x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / include / dt-bindings / clock / s3c2410.h
blob352a7673fc69939a2c7f71679856732f654dddf1
1 /*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
9 */
11 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
12 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
15 * Let each exported clock get a unique index, which is used on DT-enabled
16 * platforms to lookup the clock from a clock specifier. These indices are
17 * therefore considered an ABI and so must not be changed. This implies
18 * that new clocks should be added either in free spaces between clock groups
19 * or at the end.
22 /* Core clocks. */
24 /* id 1 is reserved */
25 #define MPLL 2
26 #define UPLL 3
27 #define FCLK 4
28 #define HCLK 5
29 #define PCLK 6
30 #define UCLK 7
31 #define ARMCLK 8
33 /* pclk-gates */
34 #define PCLK_UART0 16
35 #define PCLK_UART1 17
36 #define PCLK_UART2 18
37 #define PCLK_I2C 19
38 #define PCLK_SDI 20
39 #define PCLK_SPI 21
40 #define PCLK_ADC 22
41 #define PCLK_AC97 23
42 #define PCLK_I2S 24
43 #define PCLK_PWM 25
44 #define PCLK_RTC 26
45 #define PCLK_GPIO 27
48 /* hclk-gates */
49 #define HCLK_LCD 32
50 #define HCLK_USBH 33
51 #define HCLK_USBD 34
52 #define HCLK_NAND 35
53 #define HCLK_CAM 36
56 #define CAMIF 40
59 /* Total number of clocks. */
60 #define NR_CLKS (CAMIF + 1)
62 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */