include/dt-bindings/clock/s3c2443.h

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
   9  */
  10
  11 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
  12 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
  13
  14 /*
  15  * Let each exported clock get a unique index, which is used on DT-enabled
  16  * platforms to lookup the clock from a clock specifier. These indices are
  17  * therefore considered an ABI and so must not be changed. This implies
  18  * that new clocks should be added either in free spaces between clock groups
  19  * or at the end.
  20  */
  21
  22 /* Core clocks. */
  23 #define MSYSCLK                 1
  24 #define ESYSCLK                 2
  25 #define ARMDIV                  3
  26 #define ARMCLK                  4
  27 #define HCLK                    5
  28 #define PCLK                    6
  29
  30 /* Special clocks */
  31 #define SCLK_HSSPI0             16
  32 #define SCLK_FIMD               17
  33 #define SCLK_I2S0               18
  34 #define SCLK_I2S1               19
  35 #define SCLK_HSMMC1             20
  36 #define SCLK_HSMMC_EXT          21
  37 #define SCLK_CAM                22
  38 #define SCLK_UART               23
  39 #define SCLK_USBH               24
  40
  41 /* Muxes */
  42 #define MUX_HSSPI0              32
  43 #define MUX_HSSPI1              33
  44 #define MUX_HSMMC0              34
  45 #define MUX_HSMMC1              35
  46
  47 /* hclk-gates */
  48 #define HCLK_DMA0               48
  49 #define HCLK_DMA1               49
  50 #define HCLK_DMA2               50
  51 #define HCLK_DMA3               51
  52 #define HCLK_DMA4               52
  53 #define HCLK_DMA5               53
  54 #define HCLK_DMA6               54
  55 #define HCLK_DMA7               55
  56 #define HCLK_CAM                56
  57 #define HCLK_LCD                57
  58 #define HCLK_USBH               58
  59 #define HCLK_USBD               59
  60 #define HCLK_IROM               60
  61 #define HCLK_HSMMC0             61
  62 #define HCLK_HSMMC1             62
  63 #define HCLK_CFC                63
  64 #define HCLK_SSMC               64
  65 #define HCLK_DRAM               65
  66 #define HCLK_2D                 66
  67
  68 /* pclk-gates */
  69 #define PCLK_UART0              72
  70 #define PCLK_UART1              73
  71 #define PCLK_UART2              74
  72 #define PCLK_UART3              75
  73 #define PCLK_I2C0               76
  74 #define PCLK_SDI                77
  75 #define PCLK_SPI0               78
  76 #define PCLK_ADC                79
  77 #define PCLK_AC97               80
  78 #define PCLK_I2S0               81
  79 #define PCLK_PWM                82
  80 #define PCLK_WDT                83
  81 #define PCLK_RTC                84
  82 #define PCLK_GPIO               85
  83 #define PCLK_SPI1               86
  84 #define PCLK_CHIPID             87
  85 #define PCLK_I2C1               88
  86 #define PCLK_I2S1               89
  87 #define PCLK_PCM                90
  88
  89 /* Total number of clocks. */
  90 #define NR_CLKS                 (PCLK_PCM + 1)
  91
  92 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */