include/dt-bindings/clock/tegra20-car.h

   1 /*
   2  * This header provides constants for binding nvidia,tegra20-car.
   3  *
   4  * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
   5  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
   6  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
   7  * this case, those clocks are assigned IDs above 95 in order to highlight
   8  * this issue. Implementations that interpret these clock IDs as bit values
   9  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10  * explicitly handle these special cases.
  11  *
  12  * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
  13  * above.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
  17 #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
  18
  19 #define TEGRA20_CLK_CPU 0
  20 /* 1 */
  21 /* 2 */
  22 #define TEGRA20_CLK_AC97 3
  23 #define TEGRA20_CLK_RTC 4
  24 #define TEGRA20_CLK_TIMER 5
  25 #define TEGRA20_CLK_UARTA 6
  26 /* 7 (register bit affects uart2 and vfir) */
  27 #define TEGRA20_CLK_GPIO 8
  28 #define TEGRA20_CLK_SDMMC2 9
  29 /* 10 (register bit affects spdif_in and spdif_out) */
  30 #define TEGRA20_CLK_I2S1 11
  31 #define TEGRA20_CLK_I2C1 12
  32 #define TEGRA20_CLK_NDFLASH 13
  33 #define TEGRA20_CLK_SDMMC1 14
  34 #define TEGRA20_CLK_SDMMC4 15
  35 #define TEGRA20_CLK_TWC 16
  36 #define TEGRA20_CLK_PWM 17
  37 #define TEGRA20_CLK_I2S2 18
  38 #define TEGRA20_CLK_EPP 19
  39 /* 20 (register bit affects vi and vi_sensor) */
  40 #define TEGRA20_CLK_GR2D 21
  41 #define TEGRA20_CLK_USBD 22
  42 #define TEGRA20_CLK_ISP 23
  43 #define TEGRA20_CLK_GR3D 24
  44 #define TEGRA20_CLK_IDE 25
  45 #define TEGRA20_CLK_DISP2 26
  46 #define TEGRA20_CLK_DISP1 27
  47 #define TEGRA20_CLK_HOST1X 28
  48 #define TEGRA20_CLK_VCP 29
  49 /* 30 */
  50 #define TEGRA20_CLK_CACHE2 31
  51
  52 #define TEGRA20_CLK_MC 32
  53 #define TEGRA20_CLK_AHBDMA 33
  54 #define TEGRA20_CLK_APBDMA 34
  55 /* 35 */
  56 #define TEGRA20_CLK_KBC 36
  57 #define TEGRA20_CLK_STAT_MON 37
  58 #define TEGRA20_CLK_PMC 38
  59 #define TEGRA20_CLK_FUSE 39
  60 #define TEGRA20_CLK_KFUSE 40
  61 #define TEGRA20_CLK_SBC1 41
  62 #define TEGRA20_CLK_NOR 42
  63 #define TEGRA20_CLK_SPI 43
  64 #define TEGRA20_CLK_SBC2 44
  65 #define TEGRA20_CLK_XIO 45
  66 #define TEGRA20_CLK_SBC3 46
  67 #define TEGRA20_CLK_DVC 47
  68 #define TEGRA20_CLK_DSI 48
  69 /* 49 (register bit affects tvo and cve) */
  70 #define TEGRA20_CLK_MIPI 50
  71 #define TEGRA20_CLK_HDMI 51
  72 #define TEGRA20_CLK_CSI 52
  73 #define TEGRA20_CLK_TVDAC 53
  74 #define TEGRA20_CLK_I2C2 54
  75 #define TEGRA20_CLK_UARTC 55
  76 /* 56 */
  77 #define TEGRA20_CLK_EMC 57
  78 #define TEGRA20_CLK_USB2 58
  79 #define TEGRA20_CLK_USB3 59
  80 #define TEGRA20_CLK_MPE 60
  81 #define TEGRA20_CLK_VDE 61
  82 #define TEGRA20_CLK_BSEA 62
  83 #define TEGRA20_CLK_BSEV 63
  84
  85 #define TEGRA20_CLK_SPEEDO 64
  86 #define TEGRA20_CLK_UARTD 65
  87 #define TEGRA20_CLK_UARTE 66
  88 #define TEGRA20_CLK_I2C3 67
  89 #define TEGRA20_CLK_SBC4 68
  90 #define TEGRA20_CLK_SDMMC3 69
  91 #define TEGRA20_CLK_PEX 70
  92 #define TEGRA20_CLK_OWR 71
  93 #define TEGRA20_CLK_AFI 72
  94 #define TEGRA20_CLK_CSITE 73
  95 /* 74 */
  96 #define TEGRA20_CLK_AVPUCQ 75
  97 #define TEGRA20_CLK_LA 76
  98 /* 77 */
  99 /* 78 */
 100 /* 79 */
 101 /* 80 */
 102 /* 81 */
 103 /* 82 */
 104 /* 83 */
 105 #define TEGRA20_CLK_IRAMA 84
 106 #define TEGRA20_CLK_IRAMB 85
 107 #define TEGRA20_CLK_IRAMC 86
 108 #define TEGRA20_CLK_IRAMD 87
 109 #define TEGRA20_CLK_CRAM2 88
 110 #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
 111 #define TEGRA20_CLK_CLK_D 90
 112 /* 91 */
 113 #define TEGRA20_CLK_CSUS 92
 114 #define TEGRA20_CLK_CDEV2 93
 115 #define TEGRA20_CLK_CDEV1 94
 116 /* 95 */
 117
 118 #define TEGRA20_CLK_UARTB 96
 119 #define TEGRA20_CLK_VFIR 97
 120 #define TEGRA20_CLK_SPDIF_IN 98
 121 #define TEGRA20_CLK_SPDIF_OUT 99
 122 #define TEGRA20_CLK_VI 100
 123 #define TEGRA20_CLK_VI_SENSOR 101
 124 #define TEGRA20_CLK_TVO 102
 125 #define TEGRA20_CLK_CVE 103
 126 #define TEGRA20_CLK_OSC 104
 127 #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
 128 #define TEGRA20_CLK_CLK_M 106
 129 #define TEGRA20_CLK_SCLK 107
 130 #define TEGRA20_CLK_CCLK 108
 131 #define TEGRA20_CLK_HCLK 109
 132 #define TEGRA20_CLK_PCLK 110
 133 #define TEGRA20_CLK_BLINK 111
 134 #define TEGRA20_CLK_PLL_A 112
 135 #define TEGRA20_CLK_PLL_A_OUT0 113
 136 #define TEGRA20_CLK_PLL_C 114
 137 #define TEGRA20_CLK_PLL_C_OUT1 115
 138 #define TEGRA20_CLK_PLL_D 116
 139 #define TEGRA20_CLK_PLL_D_OUT0 117
 140 #define TEGRA20_CLK_PLL_E 118
 141 #define TEGRA20_CLK_PLL_M 119
 142 #define TEGRA20_CLK_PLL_M_OUT1 120
 143 #define TEGRA20_CLK_PLL_P 121
 144 #define TEGRA20_CLK_PLL_P_OUT1 122
 145 #define TEGRA20_CLK_PLL_P_OUT2 123
 146 #define TEGRA20_CLK_PLL_P_OUT3 124
 147 #define TEGRA20_CLK_PLL_P_OUT4 125
 148 #define TEGRA20_CLK_PLL_S 126
 149 #define TEGRA20_CLK_PLL_U 127
 150
 151 #define TEGRA20_CLK_PLL_X 128
 152 #define TEGRA20_CLK_COP 129 /* a/k/a avp */
 153 #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
 154 #define TEGRA20_CLK_PLL_REF 131
 155 #define TEGRA20_CLK_TWD 132
 156 #define TEGRA20_CLK_CLK_MAX 133
 157
 158 #endif  /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */