include/dt-bindings/clock/tegra30-car.h

   1 /*
   2  * This header provides constants for binding nvidia,tegra30-car.
   3  *
   4  * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
   5  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
   6  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
   7  * this case, those clocks are assigned IDs above 160 in order to highlight
   8  * this issue. Implementations that interpret these clock IDs as bit values
   9  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10  * explicitly handle these special cases.
  11  *
  12  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  13  * above.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  17 #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  18
  19 #define TEGRA30_CLK_CPU 0
  20 /* 1 */
  21 /* 2 */
  22 /* 3 */
  23 #define TEGRA30_CLK_RTC 4
  24 #define TEGRA30_CLK_TIMER 5
  25 #define TEGRA30_CLK_UARTA 6
  26 /* 7 (register bit affects uartb and vfir) */
  27 #define TEGRA30_CLK_GPIO 8
  28 #define TEGRA30_CLK_SDMMC2 9
  29 /* 10 (register bit affects spdif_in and spdif_out) */
  30 #define TEGRA30_CLK_I2S1 11
  31 #define TEGRA30_CLK_I2C1 12
  32 #define TEGRA30_CLK_NDFLASH 13
  33 #define TEGRA30_CLK_SDMMC1 14
  34 #define TEGRA30_CLK_SDMMC4 15
  35 /* 16 */
  36 #define TEGRA30_CLK_PWM 17
  37 #define TEGRA30_CLK_I2S2 18
  38 #define TEGRA30_CLK_EPP 19
  39 /* 20 (register bit affects vi and vi_sensor) */
  40 #define TEGRA30_CLK_GR2D 21
  41 #define TEGRA30_CLK_USBD 22
  42 #define TEGRA30_CLK_ISP 23
  43 #define TEGRA30_CLK_GR3D 24
  44 /* 25 */
  45 #define TEGRA30_CLK_DISP2 26
  46 #define TEGRA30_CLK_DISP1 27
  47 #define TEGRA30_CLK_HOST1X 28
  48 #define TEGRA30_CLK_VCP 29
  49 #define TEGRA30_CLK_I2S0 30
  50 #define TEGRA30_CLK_COP_CACHE 31
  51
  52 #define TEGRA30_CLK_MC 32
  53 #define TEGRA30_CLK_AHBDMA 33
  54 #define TEGRA30_CLK_APBDMA 34
  55 /* 35 */
  56 #define TEGRA30_CLK_KBC 36
  57 #define TEGRA30_CLK_STATMON 37
  58 #define TEGRA30_CLK_PMC 38
  59 /* 39 (register bit affects fuse and fuse_burn) */
  60 #define TEGRA30_CLK_KFUSE 40
  61 #define TEGRA30_CLK_SBC1 41
  62 #define TEGRA30_CLK_NOR 42
  63 /* 43 */
  64 #define TEGRA30_CLK_SBC2 44
  65 /* 45 */
  66 #define TEGRA30_CLK_SBC3 46
  67 #define TEGRA30_CLK_I2C5 47
  68 #define TEGRA30_CLK_DSIA 48
  69 /* 49 (register bit affects cve and tvo) */
  70 #define TEGRA30_CLK_MIPI 50
  71 #define TEGRA30_CLK_HDMI 51
  72 #define TEGRA30_CLK_CSI 52
  73 #define TEGRA30_CLK_TVDAC 53
  74 #define TEGRA30_CLK_I2C2 54
  75 #define TEGRA30_CLK_UARTC 55
  76 /* 56 */
  77 #define TEGRA30_CLK_EMC 57
  78 #define TEGRA30_CLK_USB2 58
  79 #define TEGRA30_CLK_USB3 59
  80 #define TEGRA30_CLK_MPE 60
  81 #define TEGRA30_CLK_VDE 61
  82 #define TEGRA30_CLK_BSEA 62
  83 #define TEGRA30_CLK_BSEV 63
  84
  85 #define TEGRA30_CLK_SPEEDO 64
  86 #define TEGRA30_CLK_UARTD 65
  87 #define TEGRA30_CLK_UARTE 66
  88 #define TEGRA30_CLK_I2C3 67
  89 #define TEGRA30_CLK_SBC4 68
  90 #define TEGRA30_CLK_SDMMC3 69
  91 #define TEGRA30_CLK_PCIE 70
  92 #define TEGRA30_CLK_OWR 71
  93 #define TEGRA30_CLK_AFI 72
  94 #define TEGRA30_CLK_CSITE 73
  95 /* 74 */
  96 #define TEGRA30_CLK_AVPUCQ 75
  97 #define TEGRA30_CLK_LA 76
  98 /* 77 */
  99 /* 78 */
 100 #define TEGRA30_CLK_DTV 79
 101 #define TEGRA30_CLK_NDSPEED 80
 102 #define TEGRA30_CLK_I2CSLOW 81
 103 #define TEGRA30_CLK_DSIB 82
 104 /* 83 */
 105 #define TEGRA30_CLK_IRAMA 84
 106 #define TEGRA30_CLK_IRAMB 85
 107 #define TEGRA30_CLK_IRAMC 86
 108 #define TEGRA30_CLK_IRAMD 87
 109 #define TEGRA30_CLK_CRAM2 88
 110 /* 89 */
 111 #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
 112 /* 91 */
 113 #define TEGRA30_CLK_CSUS 92
 114 #define TEGRA30_CLK_CDEV2 93
 115 #define TEGRA30_CLK_CDEV1 94
 116 /* 95 */
 117
 118 #define TEGRA30_CLK_CPU_G 96
 119 #define TEGRA30_CLK_CPU_LP 97
 120 #define TEGRA30_CLK_GR3D2 98
 121 #define TEGRA30_CLK_MSELECT 99
 122 #define TEGRA30_CLK_TSENSOR 100
 123 #define TEGRA30_CLK_I2S3 101
 124 #define TEGRA30_CLK_I2S4 102
 125 #define TEGRA30_CLK_I2C4 103
 126 #define TEGRA30_CLK_SBC5 104
 127 #define TEGRA30_CLK_SBC6 105
 128 #define TEGRA30_CLK_D_AUDIO 106
 129 #define TEGRA30_CLK_APBIF 107
 130 #define TEGRA30_CLK_DAM0 108
 131 #define TEGRA30_CLK_DAM1 109
 132 #define TEGRA30_CLK_DAM2 110
 133 #define TEGRA30_CLK_HDA2CODEC_2X 111
 134 #define TEGRA30_CLK_ATOMICS 112
 135 #define TEGRA30_CLK_AUDIO0_2X 113
 136 #define TEGRA30_CLK_AUDIO1_2X 114
 137 #define TEGRA30_CLK_AUDIO2_2X 115
 138 #define TEGRA30_CLK_AUDIO3_2X 116
 139 #define TEGRA30_CLK_AUDIO4_2X 117
 140 #define TEGRA30_CLK_SPDIF_2X 118
 141 #define TEGRA30_CLK_ACTMON 119
 142 #define TEGRA30_CLK_EXTERN1 120
 143 #define TEGRA30_CLK_EXTERN2 121
 144 #define TEGRA30_CLK_EXTERN3 122
 145 #define TEGRA30_CLK_SATA_OOB 123
 146 #define TEGRA30_CLK_SATA 124
 147 #define TEGRA30_CLK_HDA 125
 148 /* 126 */
 149 #define TEGRA30_CLK_SE 127
 150
 151 #define TEGRA30_CLK_HDA2HDMI 128
 152 #define TEGRA30_CLK_SATA_COLD 129
 153 /* 130 */
 154 /* 131 */
 155 /* 132 */
 156 /* 133 */
 157 /* 134 */
 158 /* 135 */
 159 /* 136 */
 160 /* 137 */
 161 /* 138 */
 162 /* 139 */
 163 /* 140 */
 164 /* 141 */
 165 /* 142 */
 166 /* 143 */
 167 /* 144 */
 168 /* 145 */
 169 /* 146 */
 170 /* 147 */
 171 /* 148 */
 172 /* 149 */
 173 /* 150 */
 174 /* 151 */
 175 /* 152 */
 176 /* 153 */
 177 /* 154 */
 178 /* 155 */
 179 /* 156 */
 180 /* 157 */
 181 /* 158 */
 182 /* 159 */
 183
 184 #define TEGRA30_CLK_UARTB 160
 185 #define TEGRA30_CLK_VFIR 161
 186 #define TEGRA30_CLK_SPDIF_IN 162
 187 #define TEGRA30_CLK_SPDIF_OUT 163
 188 #define TEGRA30_CLK_VI 164
 189 #define TEGRA30_CLK_VI_SENSOR 165
 190 #define TEGRA30_CLK_FUSE 166
 191 #define TEGRA30_CLK_FUSE_BURN 167
 192 #define TEGRA30_CLK_CVE 168
 193 #define TEGRA30_CLK_TVO 169
 194 #define TEGRA30_CLK_CLK_32K 170
 195 #define TEGRA30_CLK_CLK_M 171
 196 #define TEGRA30_CLK_CLK_M_DIV2 172
 197 #define TEGRA30_CLK_CLK_M_DIV4 173
 198 #define TEGRA30_CLK_PLL_REF 174
 199 #define TEGRA30_CLK_PLL_C 175
 200 #define TEGRA30_CLK_PLL_C_OUT1 176
 201 #define TEGRA30_CLK_PLL_M 177
 202 #define TEGRA30_CLK_PLL_M_OUT1 178
 203 #define TEGRA30_CLK_PLL_P 179
 204 #define TEGRA30_CLK_PLL_P_OUT1 180
 205 #define TEGRA30_CLK_PLL_P_OUT2 181
 206 #define TEGRA30_CLK_PLL_P_OUT3 182
 207 #define TEGRA30_CLK_PLL_P_OUT4 183
 208 #define TEGRA30_CLK_PLL_A 184
 209 #define TEGRA30_CLK_PLL_A_OUT0 185
 210 #define TEGRA30_CLK_PLL_D 186
 211 #define TEGRA30_CLK_PLL_D_OUT0 187
 212 #define TEGRA30_CLK_PLL_D2 188
 213 #define TEGRA30_CLK_PLL_D2_OUT0 189
 214 #define TEGRA30_CLK_PLL_U 190
 215 #define TEGRA30_CLK_PLL_X 191
 216
 217 #define TEGRA30_CLK_PLL_X_OUT0 192
 218 #define TEGRA30_CLK_PLL_E 193
 219 #define TEGRA30_CLK_SPDIF_IN_SYNC 194
 220 #define TEGRA30_CLK_I2S0_SYNC 195
 221 #define TEGRA30_CLK_I2S1_SYNC 196
 222 #define TEGRA30_CLK_I2S2_SYNC 197
 223 #define TEGRA30_CLK_I2S3_SYNC 198
 224 #define TEGRA30_CLK_I2S4_SYNC 199
 225 #define TEGRA30_CLK_VIMCLK_SYNC 200
 226 #define TEGRA30_CLK_AUDIO0 201
 227 #define TEGRA30_CLK_AUDIO1 202
 228 #define TEGRA30_CLK_AUDIO2 203
 229 #define TEGRA30_CLK_AUDIO3 204
 230 #define TEGRA30_CLK_AUDIO4 205
 231 #define TEGRA30_CLK_SPDIF 206
 232 #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
 233 #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
 234 #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
 235 #define TEGRA30_CLK_SCLK 210
 236 #define TEGRA30_CLK_BLINK 211
 237 #define TEGRA30_CLK_CCLK_G 212
 238 #define TEGRA30_CLK_CCLK_LP 213
 239 #define TEGRA30_CLK_TWD 214
 240 #define TEGRA30_CLK_CML0 215
 241 #define TEGRA30_CLK_CML1 216
 242 #define TEGRA30_CLK_HCLK 217
 243 #define TEGRA30_CLK_PCLK 218
 244 /* 219 */
 245 /* 220 */
 246 /* 221 */
 247 /* 222 */
 248 /* 223 */
 249
 250 /* 288 */
 251 /* 289 */
 252 /* 290 */
 253 /* 291 */
 254 /* 292 */
 255 /* 293 */
 256 /* 294 */
 257 /* 295 */
 258 /* 296 */
 259 /* 297 */
 260 /* 298 */
 261 /* 299 */
 262 #define TEGRA30_CLK_CLK_OUT_1_MUX 300
 263 #define TEGRA30_CLK_CLK_OUT_2_MUX 301
 264 #define TEGRA30_CLK_CLK_OUT_3_MUX 302
 265 #define TEGRA30_CLK_AUDIO0_MUX 303
 266 #define TEGRA30_CLK_AUDIO1_MUX 304
 267 #define TEGRA30_CLK_AUDIO2_MUX 305
 268 #define TEGRA30_CLK_AUDIO3_MUX 306
 269 #define TEGRA30_CLK_AUDIO4_MUX 307
 270 #define TEGRA30_CLK_SPDIF_MUX 308
 271 #define TEGRA30_CLK_CLK_MAX 309
 272
 273 #endif  /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */