include/video/imx-ipu-v3.h

   1 /*
   2  * Copyright 2005-2009 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU Lesser General
   5  * Public License.  You may obtain a copy of the GNU Lesser General
   6  * Public License Version 2.1 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/lgpl-license.html
   9  * http://www.gnu.org/copyleft/lgpl.html
  10  */
  11
  12 #ifndef __DRM_IPU_H__
  13 #define __DRM_IPU_H__
  14
  15 #include <linux/types.h>
  16 #include <linux/videodev2.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/fb.h>
  19 #include <linux/of.h>
  20 #include <media/v4l2-mediabus.h>
  21 #include <video/videomode.h>
  22
  23 struct ipu_soc;
  24
  25 enum ipuv3_type {
  26         IPUV3EX,
  27         IPUV3M,
  28         IPUV3H,
  29 };
  30
  31 #define IPU_PIX_FMT_GBR24       v4l2_fourcc('G', 'B', 'R', '3')
  32
  33 /*
  34  * Bitfield of Display Interface signal polarities.
  35  */
  36 struct ipu_di_signal_cfg {
  37         unsigned data_pol:1;    /* true = inverted */
  38         unsigned clk_pol:1;     /* true = rising edge */
  39         unsigned enable_pol:1;
  40
  41         struct videomode mode;
  42
  43         u32 bus_format;
  44         u32 v_to_h_sync;
  45
  46 #define IPU_DI_CLKMODE_SYNC     (1 << 0)
  47 #define IPU_DI_CLKMODE_EXT      (1 << 1)
  48         unsigned long clkflags;
  49
  50         u8 hsync_pin;
  51         u8 vsync_pin;
  52 };
  53
  54 /*
  55  * Enumeration of CSI destinations
  56  */
  57 enum ipu_csi_dest {
  58         IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
  59         IPU_CSI_DEST_IC,        /* to Image Converter */
  60         IPU_CSI_DEST_VDIC,  /* to VDIC */
  61 };
  62
  63 /*
  64  * Enumeration of IPU rotation modes
  65  */
  66 #define IPU_ROT_BIT_VFLIP (1 << 0)
  67 #define IPU_ROT_BIT_HFLIP (1 << 1)
  68 #define IPU_ROT_BIT_90    (1 << 2)
  69
  70 enum ipu_rotate_mode {
  71         IPU_ROTATE_NONE = 0,
  72         IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
  73         IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
  74         IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
  75         IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
  76         IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
  77         IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
  78         IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
  79                               IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
  80 };
  81
  82 /* 90-degree rotations require the IRT unit */
  83 #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
  84
  85 enum ipu_color_space {
  86         IPUV3_COLORSPACE_RGB,
  87         IPUV3_COLORSPACE_YUV,
  88         IPUV3_COLORSPACE_UNKNOWN,
  89 };
  90
  91 /*
  92  * Enumeration of VDI MOTION select
  93  */
  94 enum ipu_motion_sel {
  95         MOTION_NONE = 0,
  96         LOW_MOTION,
  97         MED_MOTION,
  98         HIGH_MOTION,
  99 };
 100
 101 struct ipuv3_channel;
 102
 103 enum ipu_channel_irq {
 104         IPU_IRQ_EOF = 0,
 105         IPU_IRQ_NFACK = 64,
 106         IPU_IRQ_NFB4EOF = 128,
 107         IPU_IRQ_EOS = 192,
 108 };
 109
 110 /*
 111  * Enumeration of IDMAC channels
 112  */
 113 #define IPUV3_CHANNEL_CSI0                       0
 114 #define IPUV3_CHANNEL_CSI1                       1
 115 #define IPUV3_CHANNEL_CSI2                       2
 116 #define IPUV3_CHANNEL_CSI3                       3
 117 #define IPUV3_CHANNEL_VDI_MEM_IC_VF              5
 118 /*
 119  * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
 120  * but the direct CSI->VDI linking is handled the same way as IDMAC
 121  * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
 122  * these channel names are used to support the direct CSI->VDI link.
 123  */
 124 #define IPUV3_CHANNEL_CSI_DIRECT                 6
 125 #define IPUV3_CHANNEL_CSI_VDI_PREV               7
 126 #define IPUV3_CHANNEL_MEM_VDI_PREV               8
 127 #define IPUV3_CHANNEL_MEM_VDI_CUR                9
 128 #define IPUV3_CHANNEL_MEM_VDI_NEXT              10
 129 #define IPUV3_CHANNEL_MEM_IC_PP                 11
 130 #define IPUV3_CHANNEL_MEM_IC_PRP_VF             12
 131 #define IPUV3_CHANNEL_VDI_MEM_RECENT            13
 132 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF           14
 133 #define IPUV3_CHANNEL_G_MEM_IC_PP               15
 134 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA     17
 135 #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA         18
 136 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
 137 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM            20
 138 #define IPUV3_CHANNEL_IC_PRP_VF_MEM             21
 139 #define IPUV3_CHANNEL_IC_PP_MEM                 22
 140 #define IPUV3_CHANNEL_MEM_BG_SYNC               23
 141 #define IPUV3_CHANNEL_MEM_BG_ASYNC              24
 142 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB       25
 143 #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB       26
 144 #define IPUV3_CHANNEL_MEM_FG_SYNC               27
 145 #define IPUV3_CHANNEL_MEM_DC_SYNC               28
 146 #define IPUV3_CHANNEL_MEM_FG_ASYNC              29
 147 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA         31
 148 #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA        33
 149 #define IPUV3_CHANNEL_DC_MEM_READ               40
 150 #define IPUV3_CHANNEL_MEM_DC_ASYNC              41
 151 #define IPUV3_CHANNEL_MEM_DC_COMMAND            42
 152 #define IPUV3_CHANNEL_MEM_DC_COMMAND2           43
 153 #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK        44
 154 #define IPUV3_CHANNEL_MEM_ROT_ENC               45
 155 #define IPUV3_CHANNEL_MEM_ROT_VF                46
 156 #define IPUV3_CHANNEL_MEM_ROT_PP                47
 157 #define IPUV3_CHANNEL_ROT_ENC_MEM               48
 158 #define IPUV3_CHANNEL_ROT_VF_MEM                49
 159 #define IPUV3_CHANNEL_ROT_PP_MEM                50
 160 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA         51
 161 #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA        52
 162 #define IPUV3_NUM_CHANNELS                      64
 163
 164 int ipu_map_irq(struct ipu_soc *ipu, int irq);
 165 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 166                 enum ipu_channel_irq irq);
 167
 168 #define IPU_IRQ_DP_SF_START             (448 + 2)
 169 #define IPU_IRQ_DP_SF_END               (448 + 3)
 170 #define IPU_IRQ_BG_SF_END               IPU_IRQ_DP_SF_END,
 171 #define IPU_IRQ_DC_FC_0                 (448 + 8)
 172 #define IPU_IRQ_DC_FC_1                 (448 + 9)
 173 #define IPU_IRQ_DC_FC_2                 (448 + 10)
 174 #define IPU_IRQ_DC_FC_3                 (448 + 11)
 175 #define IPU_IRQ_DC_FC_4                 (448 + 12)
 176 #define IPU_IRQ_DC_FC_6                 (448 + 13)
 177 #define IPU_IRQ_VSYNC_PRE_0             (448 + 14)
 178 #define IPU_IRQ_VSYNC_PRE_1             (448 + 15)
 179
 180 /*
 181  * IPU Common functions
 182  */
 183 int ipu_get_num(struct ipu_soc *ipu);
 184 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
 185 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
 186 void ipu_dump(struct ipu_soc *ipu);
 187
 188 /*
 189  * IPU Image DMA Controller (idmac) functions
 190  */
 191 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
 192 void ipu_idmac_put(struct ipuv3_channel *);
 193
 194 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
 195 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
 196 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
 197 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
 198 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
 199
 200 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 201                 bool doublebuffer);
 202 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
 203 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
 204 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
 205 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
 206 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
 207 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
 208 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
 209 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
 210
 211 /*
 212  * IPU Channel Parameter Memory (cpmem) functions
 213  */
 214 struct ipu_rgb {
 215         struct fb_bitfield      red;
 216         struct fb_bitfield      green;
 217         struct fb_bitfield      blue;
 218         struct fb_bitfield      transp;
 219         int                     bits_per_pixel;
 220 };
 221
 222 struct ipu_image {
 223         struct v4l2_pix_format pix;
 224         struct v4l2_rect rect;
 225         dma_addr_t phys0;
 226         dma_addr_t phys1;
 227 };
 228
 229 void ipu_cpmem_zero(struct ipuv3_channel *ch);
 230 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
 231 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
 232 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
 233 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
 234 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
 235 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 236 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
 237 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
 238 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
 239 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
 240 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
 241                             enum ipu_rotate_mode rot);
 242 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
 243                              const struct ipu_rgb *rgb);
 244 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
 245 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
 246 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
 247                                    unsigned int uv_stride,
 248                                    unsigned int u_offset,
 249                                    unsigned int v_offset);
 250 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
 251 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
 252 void ipu_cpmem_dump(struct ipuv3_channel *ch);
 253
 254 /*
 255  * IPU Display Controller (dc) functions
 256  */
 257 struct ipu_dc;
 258 struct ipu_di;
 259 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
 260 void ipu_dc_put(struct ipu_dc *dc);
 261 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 262                 u32 pixel_fmt, u32 width);
 263 void ipu_dc_enable(struct ipu_soc *ipu);
 264 void ipu_dc_enable_channel(struct ipu_dc *dc);
 265 void ipu_dc_disable_channel(struct ipu_dc *dc);
 266 void ipu_dc_disable(struct ipu_soc *ipu);
 267
 268 /*
 269  * IPU Display Interface (di) functions
 270  */
 271 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
 272 void ipu_di_put(struct ipu_di *);
 273 int ipu_di_disable(struct ipu_di *);
 274 int ipu_di_enable(struct ipu_di *);
 275 int ipu_di_get_num(struct ipu_di *);
 276 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
 277 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
 278
 279 /*
 280  * IPU Display Multi FIFO Controller (dmfc) functions
 281  */
 282 struct dmfc_channel;
 283 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
 284 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
 285 void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
 286 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
 287 void ipu_dmfc_put(struct dmfc_channel *dmfc);
 288
 289 /*
 290  * IPU Display Processor (dp) functions
 291  */
 292 #define IPU_DP_FLOW_SYNC_BG     0
 293 #define IPU_DP_FLOW_SYNC_FG     1
 294 #define IPU_DP_FLOW_ASYNC0_BG   2
 295 #define IPU_DP_FLOW_ASYNC0_FG   3
 296 #define IPU_DP_FLOW_ASYNC1_BG   4
 297 #define IPU_DP_FLOW_ASYNC1_FG   5
 298
 299 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
 300 void ipu_dp_put(struct ipu_dp *);
 301 int ipu_dp_enable(struct ipu_soc *ipu);
 302 int ipu_dp_enable_channel(struct ipu_dp *dp);
 303 void ipu_dp_disable_channel(struct ipu_dp *dp);
 304 void ipu_dp_disable(struct ipu_soc *ipu);
 305 int ipu_dp_setup_channel(struct ipu_dp *dp,
 306                 enum ipu_color_space in, enum ipu_color_space out);
 307 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
 308 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
 309                 bool bg_chan);
 310
 311 /*
 312  * IPU CMOS Sensor Interface (csi) functions
 313  */
 314 struct ipu_csi;
 315 int ipu_csi_init_interface(struct ipu_csi *csi,
 316                            struct v4l2_mbus_config *mbus_cfg,
 317                            struct v4l2_mbus_framefmt *mbus_fmt);
 318 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
 319 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
 320 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
 321 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
 322 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
 323                                 u32 r_value, u32 g_value, u32 b_value,
 324                                 u32 pix_clk);
 325 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
 326                               struct v4l2_mbus_framefmt *mbus_fmt);
 327 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
 328                           u32 max_ratio, u32 id);
 329 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
 330 int ipu_csi_enable(struct ipu_csi *csi);
 331 int ipu_csi_disable(struct ipu_csi *csi);
 332 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
 333 void ipu_csi_put(struct ipu_csi *csi);
 334 void ipu_csi_dump(struct ipu_csi *csi);
 335
 336 /*
 337  * IPU Image Converter (ic) functions
 338  */
 339 enum ipu_ic_task {
 340         IC_TASK_ENCODER,
 341         IC_TASK_VIEWFINDER,
 342         IC_TASK_POST_PROCESSOR,
 343         IC_NUM_TASKS,
 344 };
 345
 346 struct ipu_ic;
 347 int ipu_ic_task_init(struct ipu_ic *ic,
 348                      int in_width, int in_height,
 349                      int out_width, int out_height,
 350                      enum ipu_color_space in_cs,
 351                      enum ipu_color_space out_cs);
 352 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
 353                               enum ipu_color_space in_g_cs,
 354                               bool galpha_en, u32 galpha,
 355                               bool colorkey_en, u32 colorkey);
 356 void ipu_ic_task_enable(struct ipu_ic *ic);
 357 void ipu_ic_task_disable(struct ipu_ic *ic);
 358 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
 359                           u32 width, u32 height, int burst_size,
 360                           enum ipu_rotate_mode rot);
 361 int ipu_ic_enable(struct ipu_ic *ic);
 362 int ipu_ic_disable(struct ipu_ic *ic);
 363 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
 364 void ipu_ic_put(struct ipu_ic *ic);
 365 void ipu_ic_dump(struct ipu_ic *ic);
 366
 367 /*
 368  * IPU Video De-Interlacer (vdi) functions
 369  */
 370 struct ipu_vdi;
 371 void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
 372 void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
 373 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
 374 void ipu_vdi_unsetup(struct ipu_vdi *vdi);
 375 int ipu_vdi_enable(struct ipu_vdi *vdi);
 376 int ipu_vdi_disable(struct ipu_vdi *vdi);
 377 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
 378 void ipu_vdi_put(struct ipu_vdi *vdi);
 379
 380 /*
 381  * IPU Sensor Multiple FIFO Controller (SMFC) functions
 382  */
 383 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
 384 void ipu_smfc_put(struct ipu_smfc *smfc);
 385 int ipu_smfc_enable(struct ipu_smfc *smfc);
 386 int ipu_smfc_disable(struct ipu_smfc *smfc);
 387 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
 388 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
 389 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
 390
 391 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
 392 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
 393 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
 394 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
 395 bool ipu_pixelformat_is_planar(u32 pixelformat);
 396 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 397                             bool hflip, bool vflip);
 398 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 399                             bool hflip, bool vflip);
 400
 401 struct ipu_client_platformdata {
 402         int csi;
 403         int di;
 404         int dc;
 405         int dp;
 406         int dma[2];
 407         struct device_node *of_node;
 408 };
 409
 410 #endif /* __DRM_IPU_H__ */