arm64: defconfig: defconfig update for 3.19
[linux/fpc-iii.git] / arch / x86 / kvm / lapic.h
blobc674fce53cf90c0defe160673d418b992065efb6
1 #ifndef __KVM_X86_LAPIC_H
2 #define __KVM_X86_LAPIC_H
4 #include "iodev.h"
6 #include <linux/kvm_host.h>
8 #define KVM_APIC_INIT 0
9 #define KVM_APIC_SIPI 1
11 struct kvm_timer {
12 struct hrtimer timer;
13 s64 period; /* unit: ns */
14 u32 timer_mode;
15 u32 timer_mode_mask;
16 u64 tscdeadline;
17 atomic_t pending; /* accumulated triggered timers */
20 struct kvm_lapic {
21 unsigned long base_address;
22 struct kvm_io_device dev;
23 struct kvm_timer lapic_timer;
24 u32 divide_count;
25 struct kvm_vcpu *vcpu;
26 bool sw_enabled;
27 bool irr_pending;
28 /* Number of bits set in ISR. */
29 s16 isr_count;
30 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
31 int highest_isr_cache;
32 /**
33 * APIC register page. The layout matches the register layout seen by
34 * the guest 1:1, because it is accessed by the vmx microcode.
35 * Note: Only one register, the TPR, is used by the microcode.
37 void *regs;
38 gpa_t vapic_addr;
39 struct gfn_to_hva_cache vapic_cache;
40 unsigned long pending_events;
41 unsigned int sipi_vector;
43 int kvm_create_lapic(struct kvm_vcpu *vcpu);
44 void kvm_free_lapic(struct kvm_vcpu *vcpu);
46 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
47 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
48 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
49 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
50 void kvm_lapic_reset(struct kvm_vcpu *vcpu);
51 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
52 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
53 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
54 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
55 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
56 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
58 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr);
59 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
60 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest);
61 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda);
62 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
63 unsigned long *dest_map);
64 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
66 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
67 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map);
69 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
70 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
71 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
72 struct kvm_lapic_state *s);
73 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
75 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
76 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
78 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
79 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
81 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
82 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
83 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
85 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
86 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
88 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
89 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
91 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
93 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
96 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
97 void kvm_lapic_init(void);
99 static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
101 return *((u32 *) (apic->regs + reg_off));
104 extern struct static_key kvm_no_apic_vcpu;
106 static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu)
108 if (static_key_false(&kvm_no_apic_vcpu))
109 return vcpu->arch.apic;
110 return true;
113 extern struct static_key_deferred apic_hw_disabled;
115 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
117 if (static_key_false(&apic_hw_disabled.key))
118 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
119 return MSR_IA32_APICBASE_ENABLE;
122 extern struct static_key_deferred apic_sw_disabled;
124 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
126 if (static_key_false(&apic_sw_disabled.key))
127 return apic->sw_enabled;
128 return true;
131 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
133 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
136 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
138 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
141 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
143 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
146 static inline bool kvm_apic_vid_enabled(struct kvm *kvm)
148 return kvm_x86_ops->vm_has_apicv(kvm);
151 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
153 u16 cid;
154 ldr >>= 32 - map->ldr_bits;
155 cid = (ldr >> map->cid_shift) & map->cid_mask;
157 return cid;
160 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
162 ldr >>= (32 - map->ldr_bits);
163 return ldr & map->lid_mask;
166 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
168 return vcpu->arch.apic->pending_events;
171 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
173 #endif