2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
39 unsigned force_split
: 1;
45 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
46 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
47 * entries change the page attribute in parallel to some other cpu
48 * splitting a large page entry along with changing the attribute.
50 static DEFINE_SPINLOCK(cpa_lock
);
52 #define CPA_FLUSHTLB 1
54 #define CPA_PAGES_ARRAY 4
57 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
59 void update_page_count(int level
, unsigned long pages
)
61 /* Protect against CPA */
63 direct_pages_count
[level
] += pages
;
64 spin_unlock(&pgd_lock
);
67 static void split_page_count(int level
)
69 direct_pages_count
[level
]--;
70 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
73 void arch_report_meminfo(struct seq_file
*m
)
75 seq_printf(m
, "DirectMap4k: %8lu kB\n",
76 direct_pages_count
[PG_LEVEL_4K
] << 2);
77 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
78 seq_printf(m
, "DirectMap2M: %8lu kB\n",
79 direct_pages_count
[PG_LEVEL_2M
] << 11);
81 seq_printf(m
, "DirectMap4M: %8lu kB\n",
82 direct_pages_count
[PG_LEVEL_2M
] << 12);
86 seq_printf(m
, "DirectMap1G: %8lu kB\n",
87 direct_pages_count
[PG_LEVEL_1G
] << 20);
91 static inline void split_page_count(int level
) { }
96 static inline unsigned long highmap_start_pfn(void)
98 return __pa_symbol(_text
) >> PAGE_SHIFT
;
101 static inline unsigned long highmap_end_pfn(void)
103 return __pa_symbol(roundup(_brk_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 # define debug_pagealloc 1
111 # define debug_pagealloc 0
115 within(unsigned long addr
, unsigned long start
, unsigned long end
)
117 return addr
>= start
&& addr
< end
;
125 * clflush_cache_range - flush a cache range with clflush
126 * @vaddr: virtual start address
127 * @size: number of bytes to flush
129 * clflushopt is an unordered instruction which needs fencing with mfence or
130 * sfence to avoid ordering issues.
132 void clflush_cache_range(void *vaddr
, unsigned int size
)
134 void *vend
= vaddr
+ size
- 1;
138 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
141 * Flush any possible final partial cacheline:
147 EXPORT_SYMBOL_GPL(clflush_cache_range
);
149 static void __cpa_flush_all(void *arg
)
151 unsigned long cache
= (unsigned long)arg
;
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
159 if (cache
&& boot_cpu_data
.x86
>= 4)
163 static void cpa_flush_all(unsigned long cache
)
165 BUG_ON(irqs_disabled());
167 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
170 static void __cpa_flush_range(void *arg
)
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
180 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
182 unsigned int i
, level
;
185 BUG_ON(irqs_disabled());
186 WARN_ON(PAGE_ALIGN(start
) != start
);
188 on_each_cpu(__cpa_flush_range
, NULL
, 1);
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
199 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
200 pte_t
*pte
= lookup_address(addr
, &level
);
203 * Only flush present addresses:
205 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
206 clflush_cache_range((void *) addr
, PAGE_SIZE
);
210 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
,
211 int in_flags
, struct page
**pages
)
213 unsigned int i
, level
;
214 unsigned long do_wbinvd
= cache
&& numpages
>= 1024; /* 4M threshold */
216 BUG_ON(irqs_disabled());
218 on_each_cpu(__cpa_flush_all
, (void *) do_wbinvd
, 1);
220 if (!cache
|| do_wbinvd
)
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
229 for (i
= 0; i
< numpages
; i
++) {
233 if (in_flags
& CPA_PAGES_ARRAY
)
234 addr
= (unsigned long)page_address(pages
[i
]);
238 pte
= lookup_address(addr
, &level
);
241 * Only flush present addresses:
243 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
244 clflush_cache_range((void *)addr
, PAGE_SIZE
);
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
254 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
257 pgprot_t forbidden
= __pgprot(0);
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
263 #ifdef CONFIG_PCI_BIOS
264 if (pcibios_enabled
&& within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
265 pgprot_val(forbidden
) |= _PAGE_NX
;
269 * The kernel text needs to be executable for obvious reasons
270 * Does not cover __inittext since that is gone later on. On
271 * 64bit we do not enforce !NX on the low mapping
273 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
274 pgprot_val(forbidden
) |= _PAGE_NX
;
277 * The .rodata section needs to be read-only. Using the pfn
278 * catches all aliases.
280 if (within(pfn
, __pa_symbol(__start_rodata
) >> PAGE_SHIFT
,
281 __pa_symbol(__end_rodata
) >> PAGE_SHIFT
))
282 pgprot_val(forbidden
) |= _PAGE_RW
;
284 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
286 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
287 * kernel text mappings for the large page aligned text, rodata sections
288 * will be always read-only. For the kernel identity mappings covering
289 * the holes caused by this alignment can be anything that user asks.
291 * This will preserve the large page mappings for kernel text/data
294 if (kernel_set_to_readonly
&&
295 within(address
, (unsigned long)_text
,
296 (unsigned long)__end_rodata_hpage_align
)) {
300 * Don't enforce the !RW mapping for the kernel text mapping,
301 * if the current mapping is already using small page mapping.
302 * No need to work hard to preserve large page mappings in this
305 * This also fixes the Linux Xen paravirt guest boot failure
306 * (because of unexpected read-only mappings for kernel identity
307 * mappings). In this paravirt guest case, the kernel text
308 * mapping and the kernel identity mapping share the same
309 * page-table pages. Thus we can't really use different
310 * protections for the kernel text and identity mappings. Also,
311 * these shared mappings are made of small page mappings.
312 * Thus this don't enforce !RW mapping for small page kernel
313 * text mapping logic will help Linux Xen parvirt guest boot
316 if (lookup_address(address
, &level
) && (level
!= PG_LEVEL_4K
))
317 pgprot_val(forbidden
) |= _PAGE_RW
;
321 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
327 * Lookup the page table entry for a virtual address in a specific pgd.
328 * Return a pointer to the entry and the level of the mapping.
330 pte_t
*lookup_address_in_pgd(pgd_t
*pgd
, unsigned long address
,
336 *level
= PG_LEVEL_NONE
;
341 pud
= pud_offset(pgd
, address
);
345 *level
= PG_LEVEL_1G
;
346 if (pud_large(*pud
) || !pud_present(*pud
))
349 pmd
= pmd_offset(pud
, address
);
353 *level
= PG_LEVEL_2M
;
354 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
357 *level
= PG_LEVEL_4K
;
359 return pte_offset_kernel(pmd
, address
);
363 * Lookup the page table entry for a virtual address. Return a pointer
364 * to the entry and the level of the mapping.
366 * Note: We return pud and pmd either when the entry is marked large
367 * or when the present bit is not set. Otherwise we would return a
368 * pointer to a nonexisting mapping.
370 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
372 return lookup_address_in_pgd(pgd_offset_k(address
), address
, level
);
374 EXPORT_SYMBOL_GPL(lookup_address
);
376 static pte_t
*_lookup_address_cpa(struct cpa_data
*cpa
, unsigned long address
,
380 return lookup_address_in_pgd(cpa
->pgd
+ pgd_index(address
),
383 return lookup_address(address
, level
);
387 * Lookup the PMD entry for a virtual address. Return a pointer to the entry
388 * or NULL if not present.
390 pmd_t
*lookup_pmd_address(unsigned long address
)
395 pgd
= pgd_offset_k(address
);
399 pud
= pud_offset(pgd
, address
);
400 if (pud_none(*pud
) || pud_large(*pud
) || !pud_present(*pud
))
403 return pmd_offset(pud
, address
);
407 * This is necessary because __pa() does not work on some
408 * kinds of memory, like vmalloc() or the alloc_remap()
409 * areas on 32-bit NUMA systems. The percpu areas can
410 * end up in this kind of memory, for instance.
412 * This could be optimized, but it is only intended to be
413 * used at inititalization time, and keeping it
414 * unoptimized should increase the testing coverage for
415 * the more obscure platforms.
417 phys_addr_t
slow_virt_to_phys(void *__virt_addr
)
419 unsigned long virt_addr
= (unsigned long)__virt_addr
;
420 phys_addr_t phys_addr
;
421 unsigned long offset
;
427 pte
= lookup_address(virt_addr
, &level
);
429 psize
= page_level_size(level
);
430 pmask
= page_level_mask(level
);
431 offset
= virt_addr
& ~pmask
;
432 phys_addr
= (phys_addr_t
)pte_pfn(*pte
) << PAGE_SHIFT
;
433 return (phys_addr
| offset
);
435 EXPORT_SYMBOL_GPL(slow_virt_to_phys
);
438 * Set the new pmd in all the pgds we know about:
440 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
443 set_pte_atomic(kpte
, pte
);
445 if (!SHARED_KERNEL_PMD
) {
448 list_for_each_entry(page
, &pgd_list
, lru
) {
453 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
454 pud
= pud_offset(pgd
, address
);
455 pmd
= pmd_offset(pud
, address
);
456 set_pte_atomic((pte_t
*)pmd
, pte
);
463 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
464 struct cpa_data
*cpa
)
466 unsigned long nextpage_addr
, numpages
, pmask
, psize
, addr
, pfn
;
467 pte_t new_pte
, old_pte
, *tmp
;
468 pgprot_t old_prot
, new_prot
, req_prot
;
472 if (cpa
->force_split
)
475 spin_lock(&pgd_lock
);
477 * Check for races, another CPU might have split this page
480 tmp
= _lookup_address_cpa(cpa
, address
, &level
);
489 psize
= page_level_size(level
);
490 pmask
= page_level_mask(level
);
498 * Calculate the number of pages, which fit into this large
499 * page starting at address:
501 nextpage_addr
= (address
+ psize
) & pmask
;
502 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
503 if (numpages
< cpa
->numpages
)
504 cpa
->numpages
= numpages
;
507 * We are safe now. Check whether the new pgprot is the same:
508 * Convert protection attributes to 4k-format, as cpa->mask* are set
512 old_prot
= req_prot
= pgprot_large_2_4k(pte_pgprot(old_pte
));
514 pgprot_val(req_prot
) &= ~pgprot_val(cpa
->mask_clr
);
515 pgprot_val(req_prot
) |= pgprot_val(cpa
->mask_set
);
518 * req_prot is in format of 4k pages. It must be converted to large
519 * page format: the caching mode includes the PAT bit located at
520 * different bit positions in the two formats.
522 req_prot
= pgprot_4k_2_large(req_prot
);
525 * Set the PSE and GLOBAL flags only if the PRESENT flag is
526 * set otherwise pmd_present/pmd_huge will return true even on
527 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
528 * for the ancient hardware that doesn't support it.
530 if (pgprot_val(req_prot
) & _PAGE_PRESENT
)
531 pgprot_val(req_prot
) |= _PAGE_PSE
| _PAGE_GLOBAL
;
533 pgprot_val(req_prot
) &= ~(_PAGE_PSE
| _PAGE_GLOBAL
);
535 req_prot
= canon_pgprot(req_prot
);
538 * old_pte points to the large page base address. So we need
539 * to add the offset of the virtual address:
541 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
544 new_prot
= static_protections(req_prot
, address
, pfn
);
547 * We need to check the full range, whether
548 * static_protection() requires a different pgprot for one of
549 * the pages in the range we try to preserve:
551 addr
= address
& pmask
;
552 pfn
= pte_pfn(old_pte
);
553 for (i
= 0; i
< (psize
>> PAGE_SHIFT
); i
++, addr
+= PAGE_SIZE
, pfn
++) {
554 pgprot_t chk_prot
= static_protections(req_prot
, addr
, pfn
);
556 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
561 * If there are no changes, return. maxpages has been updated
564 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
570 * We need to change the attributes. Check, whether we can
571 * change the large page in one go. We request a split, when
572 * the address is not aligned and the number of pages is
573 * smaller than the number of pages in the large page. Note
574 * that we limited the number of possible pages already to
575 * the number of pages in the large page.
577 if (address
== (address
& pmask
) && cpa
->numpages
== (psize
>> PAGE_SHIFT
)) {
579 * The address is aligned and the number of pages
580 * covers the full page.
582 new_pte
= pfn_pte(pte_pfn(old_pte
), new_prot
);
583 __set_pmd_pte(kpte
, address
, new_pte
);
584 cpa
->flags
|= CPA_FLUSHTLB
;
589 spin_unlock(&pgd_lock
);
595 __split_large_page(struct cpa_data
*cpa
, pte_t
*kpte
, unsigned long address
,
598 pte_t
*pbase
= (pte_t
*)page_address(base
);
599 unsigned long pfn
, pfninc
= 1;
600 unsigned int i
, level
;
604 spin_lock(&pgd_lock
);
606 * Check for races, another CPU might have split this page
609 tmp
= _lookup_address_cpa(cpa
, address
, &level
);
611 spin_unlock(&pgd_lock
);
615 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
616 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
618 /* promote PAT bit to correct position */
619 if (level
== PG_LEVEL_2M
)
620 ref_prot
= pgprot_large_2_4k(ref_prot
);
623 if (level
== PG_LEVEL_1G
) {
624 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
626 * Set the PSE flags only if the PRESENT flag is set
627 * otherwise pmd_present/pmd_huge will return true
628 * even on a non present pmd.
630 if (pgprot_val(ref_prot
) & _PAGE_PRESENT
)
631 pgprot_val(ref_prot
) |= _PAGE_PSE
;
633 pgprot_val(ref_prot
) &= ~_PAGE_PSE
;
638 * Set the GLOBAL flags only if the PRESENT flag is set
639 * otherwise pmd/pte_present will return true even on a non
640 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
641 * for the ancient hardware that doesn't support it.
643 if (pgprot_val(ref_prot
) & _PAGE_PRESENT
)
644 pgprot_val(ref_prot
) |= _PAGE_GLOBAL
;
646 pgprot_val(ref_prot
) &= ~_PAGE_GLOBAL
;
649 * Get the target pfn from the original entry:
651 pfn
= pte_pfn(*kpte
);
652 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
653 set_pte(&pbase
[i
], pfn_pte(pfn
, canon_pgprot(ref_prot
)));
655 if (pfn_range_is_mapped(PFN_DOWN(__pa(address
)),
656 PFN_DOWN(__pa(address
)) + 1))
657 split_page_count(level
);
660 * Install the new, split up pagetable.
662 * We use the standard kernel pagetable protections for the new
663 * pagetable protections, the actual ptes set above control the
664 * primary protection behavior:
666 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
669 * Intel Atom errata AAH41 workaround.
671 * The real fix should be in hw or in a microcode update, but
672 * we also probabilistically try to reduce the window of having
673 * a large TLB mixed with 4K TLBs while instruction fetches are
677 spin_unlock(&pgd_lock
);
682 static int split_large_page(struct cpa_data
*cpa
, pte_t
*kpte
,
683 unsigned long address
)
687 if (!debug_pagealloc
)
688 spin_unlock(&cpa_lock
);
689 base
= alloc_pages(GFP_KERNEL
| __GFP_NOTRACK
, 0);
690 if (!debug_pagealloc
)
691 spin_lock(&cpa_lock
);
695 if (__split_large_page(cpa
, kpte
, address
, base
))
701 static bool try_to_free_pte_page(pte_t
*pte
)
705 for (i
= 0; i
< PTRS_PER_PTE
; i
++)
706 if (!pte_none(pte
[i
]))
709 free_page((unsigned long)pte
);
713 static bool try_to_free_pmd_page(pmd_t
*pmd
)
717 for (i
= 0; i
< PTRS_PER_PMD
; i
++)
718 if (!pmd_none(pmd
[i
]))
721 free_page((unsigned long)pmd
);
725 static bool try_to_free_pud_page(pud_t
*pud
)
729 for (i
= 0; i
< PTRS_PER_PUD
; i
++)
730 if (!pud_none(pud
[i
]))
733 free_page((unsigned long)pud
);
737 static bool unmap_pte_range(pmd_t
*pmd
, unsigned long start
, unsigned long end
)
739 pte_t
*pte
= pte_offset_kernel(pmd
, start
);
741 while (start
< end
) {
742 set_pte(pte
, __pte(0));
748 if (try_to_free_pte_page((pte_t
*)pmd_page_vaddr(*pmd
))) {
755 static void __unmap_pmd_range(pud_t
*pud
, pmd_t
*pmd
,
756 unsigned long start
, unsigned long end
)
758 if (unmap_pte_range(pmd
, start
, end
))
759 if (try_to_free_pmd_page((pmd_t
*)pud_page_vaddr(*pud
)))
763 static void unmap_pmd_range(pud_t
*pud
, unsigned long start
, unsigned long end
)
765 pmd_t
*pmd
= pmd_offset(pud
, start
);
768 * Not on a 2MB page boundary?
770 if (start
& (PMD_SIZE
- 1)) {
771 unsigned long next_page
= (start
+ PMD_SIZE
) & PMD_MASK
;
772 unsigned long pre_end
= min_t(unsigned long, end
, next_page
);
774 __unmap_pmd_range(pud
, pmd
, start
, pre_end
);
781 * Try to unmap in 2M chunks.
783 while (end
- start
>= PMD_SIZE
) {
787 __unmap_pmd_range(pud
, pmd
, start
, start
+ PMD_SIZE
);
797 return __unmap_pmd_range(pud
, pmd
, start
, end
);
800 * Try again to free the PMD page if haven't succeeded above.
803 if (try_to_free_pmd_page((pmd_t
*)pud_page_vaddr(*pud
)))
807 static void unmap_pud_range(pgd_t
*pgd
, unsigned long start
, unsigned long end
)
809 pud_t
*pud
= pud_offset(pgd
, start
);
812 * Not on a GB page boundary?
814 if (start
& (PUD_SIZE
- 1)) {
815 unsigned long next_page
= (start
+ PUD_SIZE
) & PUD_MASK
;
816 unsigned long pre_end
= min_t(unsigned long, end
, next_page
);
818 unmap_pmd_range(pud
, start
, pre_end
);
825 * Try to unmap in 1G chunks?
827 while (end
- start
>= PUD_SIZE
) {
832 unmap_pmd_range(pud
, start
, start
+ PUD_SIZE
);
842 unmap_pmd_range(pud
, start
, end
);
845 * No need to try to free the PUD page because we'll free it in
846 * populate_pgd's error path
850 static void unmap_pgd_range(pgd_t
*root
, unsigned long addr
, unsigned long end
)
852 pgd_t
*pgd_entry
= root
+ pgd_index(addr
);
854 unmap_pud_range(pgd_entry
, addr
, end
);
856 if (try_to_free_pud_page((pud_t
*)pgd_page_vaddr(*pgd_entry
)))
857 pgd_clear(pgd_entry
);
860 static int alloc_pte_page(pmd_t
*pmd
)
862 pte_t
*pte
= (pte_t
*)get_zeroed_page(GFP_KERNEL
| __GFP_NOTRACK
);
866 set_pmd(pmd
, __pmd(__pa(pte
) | _KERNPG_TABLE
));
870 static int alloc_pmd_page(pud_t
*pud
)
872 pmd_t
*pmd
= (pmd_t
*)get_zeroed_page(GFP_KERNEL
| __GFP_NOTRACK
);
876 set_pud(pud
, __pud(__pa(pmd
) | _KERNPG_TABLE
));
880 static void populate_pte(struct cpa_data
*cpa
,
881 unsigned long start
, unsigned long end
,
882 unsigned num_pages
, pmd_t
*pmd
, pgprot_t pgprot
)
886 pte
= pte_offset_kernel(pmd
, start
);
888 while (num_pages
-- && start
< end
) {
890 /* deal with the NX bit */
891 if (!(pgprot_val(pgprot
) & _PAGE_NX
))
892 cpa
->pfn
&= ~_PAGE_NX
;
894 set_pte(pte
, pfn_pte(cpa
->pfn
>> PAGE_SHIFT
, pgprot
));
897 cpa
->pfn
+= PAGE_SIZE
;
902 static int populate_pmd(struct cpa_data
*cpa
,
903 unsigned long start
, unsigned long end
,
904 unsigned num_pages
, pud_t
*pud
, pgprot_t pgprot
)
906 unsigned int cur_pages
= 0;
911 * Not on a 2M boundary?
913 if (start
& (PMD_SIZE
- 1)) {
914 unsigned long pre_end
= start
+ (num_pages
<< PAGE_SHIFT
);
915 unsigned long next_page
= (start
+ PMD_SIZE
) & PMD_MASK
;
917 pre_end
= min_t(unsigned long, pre_end
, next_page
);
918 cur_pages
= (pre_end
- start
) >> PAGE_SHIFT
;
919 cur_pages
= min_t(unsigned int, num_pages
, cur_pages
);
924 pmd
= pmd_offset(pud
, start
);
926 if (alloc_pte_page(pmd
))
929 populate_pte(cpa
, start
, pre_end
, cur_pages
, pmd
, pgprot
);
935 * We mapped them all?
937 if (num_pages
== cur_pages
)
940 pmd_pgprot
= pgprot_4k_2_large(pgprot
);
942 while (end
- start
>= PMD_SIZE
) {
945 * We cannot use a 1G page so allocate a PMD page if needed.
948 if (alloc_pmd_page(pud
))
951 pmd
= pmd_offset(pud
, start
);
953 set_pmd(pmd
, __pmd(cpa
->pfn
| _PAGE_PSE
|
954 massage_pgprot(pmd_pgprot
)));
957 cpa
->pfn
+= PMD_SIZE
;
958 cur_pages
+= PMD_SIZE
>> PAGE_SHIFT
;
962 * Map trailing 4K pages.
965 pmd
= pmd_offset(pud
, start
);
967 if (alloc_pte_page(pmd
))
970 populate_pte(cpa
, start
, end
, num_pages
- cur_pages
,
976 static int populate_pud(struct cpa_data
*cpa
, unsigned long start
, pgd_t
*pgd
,
984 end
= start
+ (cpa
->numpages
<< PAGE_SHIFT
);
987 * Not on a Gb page boundary? => map everything up to it with
990 if (start
& (PUD_SIZE
- 1)) {
991 unsigned long pre_end
;
992 unsigned long next_page
= (start
+ PUD_SIZE
) & PUD_MASK
;
994 pre_end
= min_t(unsigned long, end
, next_page
);
995 cur_pages
= (pre_end
- start
) >> PAGE_SHIFT
;
996 cur_pages
= min_t(int, (int)cpa
->numpages
, cur_pages
);
998 pud
= pud_offset(pgd
, start
);
1004 if (alloc_pmd_page(pud
))
1007 cur_pages
= populate_pmd(cpa
, start
, pre_end
, cur_pages
,
1015 /* We mapped them all? */
1016 if (cpa
->numpages
== cur_pages
)
1019 pud
= pud_offset(pgd
, start
);
1020 pud_pgprot
= pgprot_4k_2_large(pgprot
);
1023 * Map everything starting from the Gb boundary, possibly with 1G pages
1025 while (end
- start
>= PUD_SIZE
) {
1026 set_pud(pud
, __pud(cpa
->pfn
| _PAGE_PSE
|
1027 massage_pgprot(pud_pgprot
)));
1030 cpa
->pfn
+= PUD_SIZE
;
1031 cur_pages
+= PUD_SIZE
>> PAGE_SHIFT
;
1035 /* Map trailing leftover */
1039 pud
= pud_offset(pgd
, start
);
1041 if (alloc_pmd_page(pud
))
1044 tmp
= populate_pmd(cpa
, start
, end
, cpa
->numpages
- cur_pages
,
1055 * Restrictions for kernel page table do not necessarily apply when mapping in
1058 static int populate_pgd(struct cpa_data
*cpa
, unsigned long addr
)
1060 pgprot_t pgprot
= __pgprot(_KERNPG_TABLE
);
1061 pud_t
*pud
= NULL
; /* shut up gcc */
1065 pgd_entry
= cpa
->pgd
+ pgd_index(addr
);
1068 * Allocate a PUD page and hand it down for mapping.
1070 if (pgd_none(*pgd_entry
)) {
1071 pud
= (pud_t
*)get_zeroed_page(GFP_KERNEL
| __GFP_NOTRACK
);
1075 set_pgd(pgd_entry
, __pgd(__pa(pud
) | _KERNPG_TABLE
));
1078 pgprot_val(pgprot
) &= ~pgprot_val(cpa
->mask_clr
);
1079 pgprot_val(pgprot
) |= pgprot_val(cpa
->mask_set
);
1081 ret
= populate_pud(cpa
, addr
, pgd_entry
, pgprot
);
1083 unmap_pgd_range(cpa
->pgd
, addr
,
1084 addr
+ (cpa
->numpages
<< PAGE_SHIFT
));
1088 cpa
->numpages
= ret
;
1092 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
1096 return populate_pgd(cpa
, vaddr
);
1099 * Ignore all non primary paths.
1105 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1107 * Also set numpages to '1' indicating that we processed cpa req for
1108 * one virtual address page and its pfn. TBD: numpages can be set based
1109 * on the initial value and the level returned by lookup_address().
1111 if (within(vaddr
, PAGE_OFFSET
,
1112 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
1114 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
1117 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
1118 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
1125 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
1127 unsigned long address
;
1130 pte_t
*kpte
, old_pte
;
1132 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
1133 struct page
*page
= cpa
->pages
[cpa
->curpage
];
1134 if (unlikely(PageHighMem(page
)))
1136 address
= (unsigned long)page_address(page
);
1137 } else if (cpa
->flags
& CPA_ARRAY
)
1138 address
= cpa
->vaddr
[cpa
->curpage
];
1140 address
= *cpa
->vaddr
;
1142 kpte
= _lookup_address_cpa(cpa
, address
, &level
);
1144 return __cpa_process_fault(cpa
, address
, primary
);
1147 if (!pte_val(old_pte
))
1148 return __cpa_process_fault(cpa
, address
, primary
);
1150 if (level
== PG_LEVEL_4K
) {
1152 pgprot_t new_prot
= pte_pgprot(old_pte
);
1153 unsigned long pfn
= pte_pfn(old_pte
);
1155 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
1156 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
1158 new_prot
= static_protections(new_prot
, address
, pfn
);
1161 * Set the GLOBAL flags only if the PRESENT flag is
1162 * set otherwise pte_present will return true even on
1163 * a non present pte. The canon_pgprot will clear
1164 * _PAGE_GLOBAL for the ancient hardware that doesn't
1167 if (pgprot_val(new_prot
) & _PAGE_PRESENT
)
1168 pgprot_val(new_prot
) |= _PAGE_GLOBAL
;
1170 pgprot_val(new_prot
) &= ~_PAGE_GLOBAL
;
1173 * We need to keep the pfn from the existing PTE,
1174 * after all we're only going to change it's attributes
1175 * not the memory it points to
1177 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
1180 * Do we really change anything ?
1182 if (pte_val(old_pte
) != pte_val(new_pte
)) {
1183 set_pte_atomic(kpte
, new_pte
);
1184 cpa
->flags
|= CPA_FLUSHTLB
;
1191 * Check, whether we can keep the large page intact
1192 * and just change the pte:
1194 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
1196 * When the range fits into the existing large page,
1197 * return. cp->numpages and cpa->tlbflush have been updated in
1204 * We have to split the large page:
1206 err
= split_large_page(cpa
, kpte
, address
);
1209 * Do a global flush tlb after splitting the large page
1210 * and before we do the actual change page attribute in the PTE.
1212 * With out this, we violate the TLB application note, that says
1213 * "The TLBs may contain both ordinary and large-page
1214 * translations for a 4-KByte range of linear addresses. This
1215 * may occur if software modifies the paging structures so that
1216 * the page size used for the address range changes. If the two
1217 * translations differ with respect to page frame or attributes
1218 * (e.g., permissions), processor behavior is undefined and may
1219 * be implementation-specific."
1221 * We do this global tlb flush inside the cpa_lock, so that we
1222 * don't allow any other cpu, with stale tlb entries change the
1223 * page attribute in parallel, that also falls into the
1224 * just split large page entry.
1233 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
1235 static int cpa_process_alias(struct cpa_data
*cpa
)
1237 struct cpa_data alias_cpa
;
1238 unsigned long laddr
= (unsigned long)__va(cpa
->pfn
<< PAGE_SHIFT
);
1239 unsigned long vaddr
;
1242 if (!pfn_range_is_mapped(cpa
->pfn
, cpa
->pfn
+ 1))
1246 * No need to redo, when the primary call touched the direct
1249 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
1250 struct page
*page
= cpa
->pages
[cpa
->curpage
];
1251 if (unlikely(PageHighMem(page
)))
1253 vaddr
= (unsigned long)page_address(page
);
1254 } else if (cpa
->flags
& CPA_ARRAY
)
1255 vaddr
= cpa
->vaddr
[cpa
->curpage
];
1257 vaddr
= *cpa
->vaddr
;
1259 if (!(within(vaddr
, PAGE_OFFSET
,
1260 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
1263 alias_cpa
.vaddr
= &laddr
;
1264 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
1266 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
1271 #ifdef CONFIG_X86_64
1273 * If the primary call didn't touch the high mapping already
1274 * and the physical address is inside the kernel map, we need
1275 * to touch the high mapped kernel as well:
1277 if (!within(vaddr
, (unsigned long)_text
, _brk_end
) &&
1278 within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn())) {
1279 unsigned long temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) +
1280 __START_KERNEL_map
- phys_base
;
1282 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
1283 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
1286 * The high mapping range is imprecise, so ignore the
1289 __change_page_attr_set_clr(&alias_cpa
, 0);
1296 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
1298 int ret
, numpages
= cpa
->numpages
;
1302 * Store the remaining nr of pages for the large page
1303 * preservation check.
1305 cpa
->numpages
= numpages
;
1306 /* for array changes, we can't use large page */
1307 if (cpa
->flags
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
1310 if (!debug_pagealloc
)
1311 spin_lock(&cpa_lock
);
1312 ret
= __change_page_attr(cpa
, checkalias
);
1313 if (!debug_pagealloc
)
1314 spin_unlock(&cpa_lock
);
1319 ret
= cpa_process_alias(cpa
);
1325 * Adjust the number of pages with the result of the
1326 * CPA operation. Either a large page has been
1327 * preserved or a single page update happened.
1329 BUG_ON(cpa
->numpages
> numpages
);
1330 numpages
-= cpa
->numpages
;
1331 if (cpa
->flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
))
1334 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
1340 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
1341 pgprot_t mask_set
, pgprot_t mask_clr
,
1342 int force_split
, int in_flag
,
1343 struct page
**pages
)
1345 struct cpa_data cpa
;
1346 int ret
, cache
, checkalias
;
1347 unsigned long baddr
= 0;
1349 memset(&cpa
, 0, sizeof(cpa
));
1352 * Check, if we are requested to change a not supported
1355 mask_set
= canon_pgprot(mask_set
);
1356 mask_clr
= canon_pgprot(mask_clr
);
1357 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
1360 /* Ensure we are PAGE_SIZE aligned */
1361 if (in_flag
& CPA_ARRAY
) {
1363 for (i
= 0; i
< numpages
; i
++) {
1364 if (addr
[i
] & ~PAGE_MASK
) {
1365 addr
[i
] &= PAGE_MASK
;
1369 } else if (!(in_flag
& CPA_PAGES_ARRAY
)) {
1371 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1372 * No need to cehck in that case
1374 if (*addr
& ~PAGE_MASK
) {
1377 * People should not be passing in unaligned addresses:
1382 * Save address for cache flush. *addr is modified in the call
1383 * to __change_page_attr_set_clr() below.
1388 /* Must avoid aliasing mappings in the highmem code */
1389 kmap_flush_unused();
1395 cpa
.numpages
= numpages
;
1396 cpa
.mask_set
= mask_set
;
1397 cpa
.mask_clr
= mask_clr
;
1400 cpa
.force_split
= force_split
;
1402 if (in_flag
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
1403 cpa
.flags
|= in_flag
;
1405 /* No alias checking for _NX bit modifications */
1406 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
1408 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
1411 * Check whether we really changed something:
1413 if (!(cpa
.flags
& CPA_FLUSHTLB
))
1417 * No need to flush, when we did not set any of the caching
1420 cache
= !!pgprot2cachemode(mask_set
);
1423 * On success we use CLFLUSH, when the CPU supports it to
1424 * avoid the WBINVD. If the CPU does not support it and in the
1425 * error case we fall back to cpa_flush_all (which uses
1428 if (!ret
&& cpu_has_clflush
) {
1429 if (cpa
.flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
)) {
1430 cpa_flush_array(addr
, numpages
, cache
,
1433 cpa_flush_range(baddr
, numpages
, cache
);
1435 cpa_flush_all(cache
);
1441 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
1442 pgprot_t mask
, int array
)
1444 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
1445 (array
? CPA_ARRAY
: 0), NULL
);
1448 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
1449 pgprot_t mask
, int array
)
1451 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
1452 (array
? CPA_ARRAY
: 0), NULL
);
1455 static inline int cpa_set_pages_array(struct page
**pages
, int numpages
,
1458 return change_page_attr_set_clr(NULL
, numpages
, mask
, __pgprot(0), 0,
1459 CPA_PAGES_ARRAY
, pages
);
1462 static inline int cpa_clear_pages_array(struct page
**pages
, int numpages
,
1465 return change_page_attr_set_clr(NULL
, numpages
, __pgprot(0), mask
, 0,
1466 CPA_PAGES_ARRAY
, pages
);
1469 int _set_memory_uc(unsigned long addr
, int numpages
)
1472 * for now UC MINUS. see comments in ioremap_nocache()
1474 return change_page_attr_set(&addr
, numpages
,
1475 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS
),
1479 int set_memory_uc(unsigned long addr
, int numpages
)
1484 * for now UC MINUS. see comments in ioremap_nocache()
1486 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1487 _PAGE_CACHE_MODE_UC_MINUS
, NULL
);
1491 ret
= _set_memory_uc(addr
, numpages
);
1498 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1502 EXPORT_SYMBOL(set_memory_uc
);
1504 static int _set_memory_array(unsigned long *addr
, int addrinarray
,
1505 enum page_cache_mode new_type
)
1511 * for now UC MINUS. see comments in ioremap_nocache()
1513 for (i
= 0; i
< addrinarray
; i
++) {
1514 ret
= reserve_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
,
1520 ret
= change_page_attr_set(addr
, addrinarray
,
1521 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS
),
1524 if (!ret
&& new_type
== _PAGE_CACHE_MODE_WC
)
1525 ret
= change_page_attr_set_clr(addr
, addrinarray
,
1527 _PAGE_CACHE_MODE_WC
),
1528 __pgprot(_PAGE_CACHE_MASK
),
1529 0, CPA_ARRAY
, NULL
);
1536 for (j
= 0; j
< i
; j
++)
1537 free_memtype(__pa(addr
[j
]), __pa(addr
[j
]) + PAGE_SIZE
);
1542 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
1544 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_MODE_UC_MINUS
);
1546 EXPORT_SYMBOL(set_memory_array_uc
);
1548 int set_memory_array_wc(unsigned long *addr
, int addrinarray
)
1550 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_MODE_WC
);
1552 EXPORT_SYMBOL(set_memory_array_wc
);
1554 int _set_memory_wc(unsigned long addr
, int numpages
)
1557 unsigned long addr_copy
= addr
;
1559 ret
= change_page_attr_set(&addr
, numpages
,
1560 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS
),
1563 ret
= change_page_attr_set_clr(&addr_copy
, numpages
,
1565 _PAGE_CACHE_MODE_WC
),
1566 __pgprot(_PAGE_CACHE_MASK
),
1572 int set_memory_wc(unsigned long addr
, int numpages
)
1577 return set_memory_uc(addr
, numpages
);
1579 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1580 _PAGE_CACHE_MODE_WC
, NULL
);
1584 ret
= _set_memory_wc(addr
, numpages
);
1591 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1595 EXPORT_SYMBOL(set_memory_wc
);
1597 int _set_memory_wb(unsigned long addr
, int numpages
)
1599 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1600 return change_page_attr_clear(&addr
, numpages
,
1601 __pgprot(_PAGE_CACHE_MASK
), 0);
1604 int set_memory_wb(unsigned long addr
, int numpages
)
1608 ret
= _set_memory_wb(addr
, numpages
);
1612 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1615 EXPORT_SYMBOL(set_memory_wb
);
1617 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
1622 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1623 ret
= change_page_attr_clear(addr
, addrinarray
,
1624 __pgprot(_PAGE_CACHE_MASK
), 1);
1628 for (i
= 0; i
< addrinarray
; i
++)
1629 free_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
);
1633 EXPORT_SYMBOL(set_memory_array_wb
);
1635 int set_memory_x(unsigned long addr
, int numpages
)
1637 if (!(__supported_pte_mask
& _PAGE_NX
))
1640 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1642 EXPORT_SYMBOL(set_memory_x
);
1644 int set_memory_nx(unsigned long addr
, int numpages
)
1646 if (!(__supported_pte_mask
& _PAGE_NX
))
1649 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1651 EXPORT_SYMBOL(set_memory_nx
);
1653 int set_memory_ro(unsigned long addr
, int numpages
)
1655 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1657 EXPORT_SYMBOL_GPL(set_memory_ro
);
1659 int set_memory_rw(unsigned long addr
, int numpages
)
1661 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1663 EXPORT_SYMBOL_GPL(set_memory_rw
);
1665 int set_memory_np(unsigned long addr
, int numpages
)
1667 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1670 int set_memory_4k(unsigned long addr
, int numpages
)
1672 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1673 __pgprot(0), 1, 0, NULL
);
1676 int set_pages_uc(struct page
*page
, int numpages
)
1678 unsigned long addr
= (unsigned long)page_address(page
);
1680 return set_memory_uc(addr
, numpages
);
1682 EXPORT_SYMBOL(set_pages_uc
);
1684 static int _set_pages_array(struct page
**pages
, int addrinarray
,
1685 enum page_cache_mode new_type
)
1687 unsigned long start
;
1693 for (i
= 0; i
< addrinarray
; i
++) {
1694 if (PageHighMem(pages
[i
]))
1696 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1697 end
= start
+ PAGE_SIZE
;
1698 if (reserve_memtype(start
, end
, new_type
, NULL
))
1702 ret
= cpa_set_pages_array(pages
, addrinarray
,
1703 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS
));
1704 if (!ret
&& new_type
== _PAGE_CACHE_MODE_WC
)
1705 ret
= change_page_attr_set_clr(NULL
, addrinarray
,
1707 _PAGE_CACHE_MODE_WC
),
1708 __pgprot(_PAGE_CACHE_MASK
),
1709 0, CPA_PAGES_ARRAY
, pages
);
1712 return 0; /* Success */
1715 for (i
= 0; i
< free_idx
; i
++) {
1716 if (PageHighMem(pages
[i
]))
1718 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1719 end
= start
+ PAGE_SIZE
;
1720 free_memtype(start
, end
);
1725 int set_pages_array_uc(struct page
**pages
, int addrinarray
)
1727 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_MODE_UC_MINUS
);
1729 EXPORT_SYMBOL(set_pages_array_uc
);
1731 int set_pages_array_wc(struct page
**pages
, int addrinarray
)
1733 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_MODE_WC
);
1735 EXPORT_SYMBOL(set_pages_array_wc
);
1737 int set_pages_wb(struct page
*page
, int numpages
)
1739 unsigned long addr
= (unsigned long)page_address(page
);
1741 return set_memory_wb(addr
, numpages
);
1743 EXPORT_SYMBOL(set_pages_wb
);
1745 int set_pages_array_wb(struct page
**pages
, int addrinarray
)
1748 unsigned long start
;
1752 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1753 retval
= cpa_clear_pages_array(pages
, addrinarray
,
1754 __pgprot(_PAGE_CACHE_MASK
));
1758 for (i
= 0; i
< addrinarray
; i
++) {
1759 if (PageHighMem(pages
[i
]))
1761 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1762 end
= start
+ PAGE_SIZE
;
1763 free_memtype(start
, end
);
1768 EXPORT_SYMBOL(set_pages_array_wb
);
1770 int set_pages_x(struct page
*page
, int numpages
)
1772 unsigned long addr
= (unsigned long)page_address(page
);
1774 return set_memory_x(addr
, numpages
);
1776 EXPORT_SYMBOL(set_pages_x
);
1778 int set_pages_nx(struct page
*page
, int numpages
)
1780 unsigned long addr
= (unsigned long)page_address(page
);
1782 return set_memory_nx(addr
, numpages
);
1784 EXPORT_SYMBOL(set_pages_nx
);
1786 int set_pages_ro(struct page
*page
, int numpages
)
1788 unsigned long addr
= (unsigned long)page_address(page
);
1790 return set_memory_ro(addr
, numpages
);
1793 int set_pages_rw(struct page
*page
, int numpages
)
1795 unsigned long addr
= (unsigned long)page_address(page
);
1797 return set_memory_rw(addr
, numpages
);
1800 #ifdef CONFIG_DEBUG_PAGEALLOC
1802 static int __set_pages_p(struct page
*page
, int numpages
)
1804 unsigned long tempaddr
= (unsigned long) page_address(page
);
1805 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1807 .numpages
= numpages
,
1808 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1809 .mask_clr
= __pgprot(0),
1813 * No alias checking needed for setting present flag. otherwise,
1814 * we may need to break large pages for 64-bit kernel text
1815 * mappings (this adds to complexity if we want to do this from
1816 * atomic context especially). Let's keep it simple!
1818 return __change_page_attr_set_clr(&cpa
, 0);
1821 static int __set_pages_np(struct page
*page
, int numpages
)
1823 unsigned long tempaddr
= (unsigned long) page_address(page
);
1824 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1826 .numpages
= numpages
,
1827 .mask_set
= __pgprot(0),
1828 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1832 * No alias checking needed for setting not present flag. otherwise,
1833 * we may need to break large pages for 64-bit kernel text
1834 * mappings (this adds to complexity if we want to do this from
1835 * atomic context especially). Let's keep it simple!
1837 return __change_page_attr_set_clr(&cpa
, 0);
1840 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1842 if (PageHighMem(page
))
1845 debug_check_no_locks_freed(page_address(page
),
1846 numpages
* PAGE_SIZE
);
1850 * The return value is ignored as the calls cannot fail.
1851 * Large pages for identity mappings are not used at boot time
1852 * and hence no memory allocations during large page split.
1855 __set_pages_p(page
, numpages
);
1857 __set_pages_np(page
, numpages
);
1860 * We should perform an IPI and flush all tlbs,
1861 * but that can deadlock->flush only current cpu:
1865 arch_flush_lazy_mmu_mode();
1868 #ifdef CONFIG_HIBERNATION
1870 bool kernel_page_present(struct page
*page
)
1875 if (PageHighMem(page
))
1878 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1879 return (pte_val(*pte
) & _PAGE_PRESENT
);
1882 #endif /* CONFIG_HIBERNATION */
1884 #endif /* CONFIG_DEBUG_PAGEALLOC */
1886 int kernel_map_pages_in_pgd(pgd_t
*pgd
, u64 pfn
, unsigned long address
,
1887 unsigned numpages
, unsigned long page_flags
)
1889 int retval
= -EINVAL
;
1891 struct cpa_data cpa
= {
1895 .numpages
= numpages
,
1896 .mask_set
= __pgprot(0),
1897 .mask_clr
= __pgprot(0),
1901 if (!(__supported_pte_mask
& _PAGE_NX
))
1904 if (!(page_flags
& _PAGE_NX
))
1905 cpa
.mask_clr
= __pgprot(_PAGE_NX
);
1907 cpa
.mask_set
= __pgprot(_PAGE_PRESENT
| page_flags
);
1909 retval
= __change_page_attr_set_clr(&cpa
, 0);
1916 void kernel_unmap_pages_in_pgd(pgd_t
*root
, unsigned long address
,
1919 unmap_pgd_range(root
, address
, address
+ (numpages
<< PAGE_SHIFT
));
1923 * The testcases use internal knowledge of the implementation that shouldn't
1924 * be exposed to the rest of the kernel. Include these directly here.
1926 #ifdef CONFIG_CPA_DEBUG
1927 #include "pageattr-test.c"