?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mm: Initialize error in shmem_file_aio_read()
[linux/fpc-iii.git] / drivers / clk / st / clkgen-pll.c
blobbca0a0badbfa68c176aa0e82b663682b53845834
1 /*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 /*
12 * Authors:
13 * Stephen Gallimore <stephen.gallimore@st.com>,
14 * Pankaj Dev <pankaj.dev@st.com>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/of_address.h>
19 #include <linux/clk-provider.h>
20
21 #include "clkgen.h"
22
23 static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
24
25 /*
26 * Common PLL configuration register bits for PLL800 and PLL1600 C65
27 */
28 #define C65_MDIV_PLL800_MASK (0xff)
29 #define C65_MDIV_PLL1600_MASK (0x7)
30 #define C65_NDIV_MASK (0xff)
31 #define C65_PDIV_MASK (0x7)
32
33 /*
34 * PLL configuration register bits for PLL3200 C32
35 */
36 #define C32_NDIV_MASK (0xff)
37 #define C32_IDF_MASK (0x7)
38 #define C32_ODF_MASK (0x3f)
39 #define C32_LDF_MASK (0x7f)
40
41 #define C32_MAX_ODFS (4)
42
43 struct clkgen_pll_data {
44 struct clkgen_field pdn_status;
45 struct clkgen_field locked_status;
46 struct clkgen_field mdiv;
47 struct clkgen_field ndiv;
48 struct clkgen_field pdiv;
49 struct clkgen_field idf;
50 struct clkgen_field ldf;
51 unsigned int num_odfs;
52 struct clkgen_field odf[C32_MAX_ODFS];
53 struct clkgen_field odf_gate[C32_MAX_ODFS];
54 const struct clk_ops *ops;
55 };
56
57 static const struct clk_ops st_pll1600c65_ops;
58 static const struct clk_ops st_pll800c65_ops;
59 static const struct clk_ops stm_pll3200c32_ops;
60 static const struct clk_ops st_pll1200c32_ops;
61
62 static struct clkgen_pll_data st_pll1600c65_ax = {
63 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
64 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
65 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
66 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
67 .ops = &st_pll1600c65_ops
68 };
69
70 static struct clkgen_pll_data st_pll800c65_ax = {
71 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
72 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
73 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
74 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
75 .pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16),
76 .ops = &st_pll800c65_ops
77 };
78
79 static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
80 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
81 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
82 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
83 .idf = CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
84 .num_odfs = 4,
85 .odf = { CLKGEN_FIELD(0x54, C32_ODF_MASK, 4),
86 CLKGEN_FIELD(0x54, C32_ODF_MASK, 10),
87 CLKGEN_FIELD(0x54, C32_ODF_MASK, 16),
88 CLKGEN_FIELD(0x54, C32_ODF_MASK, 22) },
89 .odf_gate = { CLKGEN_FIELD(0x54, 0x1, 0),
90 CLKGEN_FIELD(0x54, 0x1, 1),
91 CLKGEN_FIELD(0x54, 0x1, 2),
92 CLKGEN_FIELD(0x54, 0x1, 3) },
93 .ops = &stm_pll3200c32_ops,
94 };
95
96 static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
97 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
98 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
99 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
100 .idf = CLKGEN_FIELD(0x10, C32_IDF_MASK, 0x0),
101 .num_odfs = 4,
102 .odf = { CLKGEN_FIELD(0x58, C32_ODF_MASK, 4),
103 CLKGEN_FIELD(0x58, C32_ODF_MASK, 10),
104 CLKGEN_FIELD(0x58, C32_ODF_MASK, 16),
105 CLKGEN_FIELD(0x58, C32_ODF_MASK, 22) },
106 .odf_gate = { CLKGEN_FIELD(0x58, 0x1, 0),
107 CLKGEN_FIELD(0x58, 0x1, 1),
108 CLKGEN_FIELD(0x58, 0x1, 2),
109 CLKGEN_FIELD(0x58, 0x1, 3) },
110 .ops = &stm_pll3200c32_ops,
111 };
112
113 /* 415 specific */
114 static struct clkgen_pll_data st_pll3200c32_a9_415 = {
115 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
116 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
117 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
118 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
119 .num_odfs = 1,
120 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 3) },
121 .odf_gate = { CLKGEN_FIELD(0x0, 0x1, 28) },
122 .ops = &stm_pll3200c32_ops,
123 };
124
125 static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
126 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
127 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
128 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
129 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
130 .num_odfs = 2,
131 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
132 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
133 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
134 CLKGEN_FIELD(0x4, 0x1, 29) },
135 .ops = &stm_pll3200c32_ops,
136 };
137
138 static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
139 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
140 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
141 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
142 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
143 .num_odfs = 0,
144 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
145 .ops = &st_pll1200c32_ops,
146 };
147
148 /* 416 specific */
149 static struct clkgen_pll_data st_pll3200c32_a9_416 = {
150 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
151 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
152 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
153 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
154 .num_odfs = 1,
155 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8) },
156 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28) },
157 .ops = &stm_pll3200c32_ops,
158 };
159
160 static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
161 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
162 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
163 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
164 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
165 .num_odfs = 2,
166 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
167 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
168 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
169 CLKGEN_FIELD(0x4, 0x1, 29) },
170 .ops = &stm_pll3200c32_ops,
171 };
172
173 static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
174 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
175 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
176 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
177 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
178 .num_odfs = 0,
179 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
180 .ops = &st_pll1200c32_ops,
181 };
182
183 /**
184 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
185 *
186 * Traits of this clock:
187 * prepare - clk_(un)prepare only ensures parent is (un)prepared
188 * enable - clk_enable/disable only ensures parent is enabled
189 * rate - rate is fixed. No clk_set_rate support
190 * parent - fixed parent. No clk_set_parent support
191 */
192
193 /**
194 * PLL clock that is integrated in the ClockGenA instances on the STiH415
195 * and STiH416.
196 *
197 * @hw: handle between common and hardware-specific interfaces.
198 * @type: PLL instance type.
199 * @regs_base: base of the PLL configuration register(s).
200 *
201 */
202 struct clkgen_pll {
203 struct clk_hw hw;
204 struct clkgen_pll_data *data;
205 void __iomem *regs_base;
206 };
207
208 #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
209
210 static int clkgen_pll_is_locked(struct clk_hw *hw)
211 {
212 struct clkgen_pll *pll = to_clkgen_pll(hw);
213 u32 locked = CLKGEN_READ(pll, locked_status);
214
215 return !!locked;
216 }
217
218 static int clkgen_pll_is_enabled(struct clk_hw *hw)
219 {
220 struct clkgen_pll *pll = to_clkgen_pll(hw);
221 u32 poweroff = CLKGEN_READ(pll, pdn_status);
222 return !poweroff;
223 }
224
225 unsigned long recalc_stm_pll800c65(struct clk_hw *hw,
226 unsigned long parent_rate)
227 {
228 struct clkgen_pll *pll = to_clkgen_pll(hw);
229 unsigned long mdiv, ndiv, pdiv;
230 unsigned long rate;
231 uint64_t res;
232
233 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
234 return 0;
235
236 pdiv = CLKGEN_READ(pll, pdiv);
237 mdiv = CLKGEN_READ(pll, mdiv);
238 ndiv = CLKGEN_READ(pll, ndiv);
239
240 if (!mdiv)
241 mdiv++; /* mdiv=0 or 1 => MDIV=1 */
242
243 res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv;
244 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv));
245
246 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
247
248 return rate;
249
250 }
251
252 unsigned long recalc_stm_pll1600c65(struct clk_hw *hw,
253 unsigned long parent_rate)
254 {
255 struct clkgen_pll *pll = to_clkgen_pll(hw);
256 unsigned long mdiv, ndiv;
257 unsigned long rate;
258
259 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
260 return 0;
261
262 mdiv = CLKGEN_READ(pll, mdiv);
263 ndiv = CLKGEN_READ(pll, ndiv);
264
265 if (!mdiv)
266 mdiv = 1;
267
268 /* Note: input is divided by 1000 to avoid overflow */
269 rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000;
270
271 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
272
273 return rate;
274 }
275
276 unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
277 unsigned long parent_rate)
278 {
279 struct clkgen_pll *pll = to_clkgen_pll(hw);
280 unsigned long ndiv, idf;
281 unsigned long rate = 0;
282
283 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
284 return 0;
285
286 ndiv = CLKGEN_READ(pll, ndiv);
287 idf = CLKGEN_READ(pll, idf);
288
289 if (idf)
290 /* Note: input is divided to avoid overflow */
291 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
292
293 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
294
295 return rate;
296 }
297
298 unsigned long recalc_stm_pll1200c32(struct clk_hw *hw,
299 unsigned long parent_rate)
300 {
301 struct clkgen_pll *pll = to_clkgen_pll(hw);
302 unsigned long odf, ldf, idf;
303 unsigned long rate;
304
305 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
306 return 0;
307
308 odf = CLKGEN_READ(pll, odf[0]);
309 ldf = CLKGEN_READ(pll, ldf);
310 idf = CLKGEN_READ(pll, idf);
311
312 if (!idf) /* idf==0 means 1 */
313 idf = 1;
314 if (!odf) /* odf==0 means 1 */
315 odf = 1;
316
317 /* Note: input is divided by 1000 to avoid overflow */
318 rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000;
319
320 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
321
322 return rate;
323 }
324
325 static const struct clk_ops st_pll1600c65_ops = {
326 .is_enabled = clkgen_pll_is_enabled,
327 .recalc_rate = recalc_stm_pll1600c65,
328 };
329
330 static const struct clk_ops st_pll800c65_ops = {
331 .is_enabled = clkgen_pll_is_enabled,
332 .recalc_rate = recalc_stm_pll800c65,
333 };
334
335 static const struct clk_ops stm_pll3200c32_ops = {
336 .is_enabled = clkgen_pll_is_enabled,
337 .recalc_rate = recalc_stm_pll3200c32,
338 };
339
340 static const struct clk_ops st_pll1200c32_ops = {
341 .is_enabled = clkgen_pll_is_enabled,
342 .recalc_rate = recalc_stm_pll1200c32,
343 };
344
345 static struct clk * __init clkgen_pll_register(const char *parent_name,
346 struct clkgen_pll_data *pll_data,
347 void __iomem *reg,
348 const char *clk_name)
349 {
350 struct clkgen_pll *pll;
351 struct clk *clk;
352 struct clk_init_data init;
353
354 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
355 if (!pll)
356 return ERR_PTR(-ENOMEM);
357
358 init.name = clk_name;
359 init.ops = pll_data->ops;
360
361 init.flags = CLK_IS_BASIC;
362 init.parent_names = &parent_name;
363 init.num_parents = 1;
364
365 pll->data = pll_data;
366 pll->regs_base = reg;
367 pll->hw.init = &init;
368
369 clk = clk_register(NULL, &pll->hw);
370 if (IS_ERR(clk)) {
371 kfree(pll);
372 return clk;
373 }
374
375 pr_debug("%s: parent %s rate %lu\n",
376 __clk_get_name(clk),
377 __clk_get_name(clk_get_parent(clk)),
378 clk_get_rate(clk));
379
380 return clk;
381 }
382
383 static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name,
384 const char *clk_name)
385 {
386 struct clk *clk;
387
388 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2);
389 if (IS_ERR(clk))
390 return clk;
391
392 pr_debug("%s: parent %s rate %lu\n",
393 __clk_get_name(clk),
394 __clk_get_name(clk_get_parent(clk)),
395 clk_get_rate(clk));
396 return clk;
397 }
398
399 static void __iomem * __init clkgen_get_register_base(
400 struct device_node *np)
401 {
402 struct device_node *pnode;
403 void __iomem *reg = NULL;
404
405 pnode = of_get_parent(np);
406 if (!pnode)
407 return NULL;
408
409 reg = of_iomap(pnode, 0);
410
411 of_node_put(pnode);
412 return reg;
413 }
414
415 #define CLKGENAx_PLL0_OFFSET 0x0
416 #define CLKGENAx_PLL1_OFFSET 0x4
417
418 static void __init clkgena_c65_pll_setup(struct device_node *np)
419 {
420 const int num_pll_outputs = 3;
421 struct clk_onecell_data *clk_data;
422 const char *parent_name;
423 void __iomem *reg;
424 const char *clk_name;
425
426 parent_name = of_clk_get_parent_name(np, 0);
427 if (!parent_name)
428 return;
429
430 reg = clkgen_get_register_base(np);
431 if (!reg)
432 return;
433
434 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
435 if (!clk_data)
436 return;
437
438 clk_data->clk_num = num_pll_outputs;
439 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
440 GFP_KERNEL);
441
442 if (!clk_data->clks)
443 goto err;
444
445 if (of_property_read_string_index(np, "clock-output-names",
446 0, &clk_name))
447 goto err;
448
449 /*
450 * PLL0 HS (high speed) output
451 */
452 clk_data->clks[0] = clkgen_pll_register(parent_name,
453 &st_pll1600c65_ax,
454 reg + CLKGENAx_PLL0_OFFSET,
455 clk_name);
456
457 if (IS_ERR(clk_data->clks[0]))
458 goto err;
459
460 if (of_property_read_string_index(np, "clock-output-names",
461 1, &clk_name))
462 goto err;
463
464 /*
465 * PLL0 LS (low speed) output, which is a fixed divide by 2 of the
466 * high speed output.
467 */
468 clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name
469 (clk_data->clks[0]),
470 clk_name);
471
472 if (IS_ERR(clk_data->clks[1]))
473 goto err;
474
475 if (of_property_read_string_index(np, "clock-output-names",
476 2, &clk_name))
477 goto err;
478
479 /*
480 * PLL1 output
481 */
482 clk_data->clks[2] = clkgen_pll_register(parent_name,
483 &st_pll800c65_ax,
484 reg + CLKGENAx_PLL1_OFFSET,
485 clk_name);
486
487 if (IS_ERR(clk_data->clks[2]))
488 goto err;
489
490 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
491 return;
492
493 err:
494 kfree(clk_data->clks);
495 kfree(clk_data);
496 }
497 CLK_OF_DECLARE(clkgena_c65_plls,
498 "st,clkgena-plls-c65", clkgena_c65_pll_setup);
499
500 static struct clk * __init clkgen_odf_register(const char *parent_name,
501 void * __iomem reg,
502 struct clkgen_pll_data *pll_data,
503 int odf,
504 spinlock_t *odf_lock,
505 const char *odf_name)
506 {
507 struct clk *clk;
508 unsigned long flags;
509 struct clk_gate *gate;
510 struct clk_divider *div;
511
512 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
513
514 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
515 if (!gate)
516 return ERR_PTR(-ENOMEM);
517
518 gate->flags = CLK_GATE_SET_TO_DISABLE;
519 gate->reg = reg + pll_data->odf_gate[odf].offset;
520 gate->bit_idx = pll_data->odf_gate[odf].shift;
521 gate->lock = odf_lock;
522
523 div = kzalloc(sizeof(*div), GFP_KERNEL);
524 if (!div)
525 return ERR_PTR(-ENOMEM);
526
527 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
528 div->reg = reg + pll_data->odf[odf].offset;
529 div->shift = pll_data->odf[odf].shift;
530 div->width = fls(pll_data->odf[odf].mask);
531 div->lock = odf_lock;
532
533 clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
534 NULL, NULL,
535 &div->hw, &clk_divider_ops,
536 &gate->hw, &clk_gate_ops,
537 flags);
538 if (IS_ERR(clk))
539 return clk;
540
541 pr_debug("%s: parent %s rate %lu\n",
542 __clk_get_name(clk),
543 __clk_get_name(clk_get_parent(clk)),
544 clk_get_rate(clk));
545 return clk;
546 }
547
548 static struct of_device_id c32_pll_of_match[] = {
549 {
550 .compatible = "st,plls-c32-a1x-0",
551 .data = &st_pll3200c32_a1x_0,
552 },
553 {
554 .compatible = "st,plls-c32-a1x-1",
555 .data = &st_pll3200c32_a1x_1,
556 },
557 {
558 .compatible = "st,stih415-plls-c32-a9",
559 .data = &st_pll3200c32_a9_415,
560 },
561 {
562 .compatible = "st,stih415-plls-c32-ddr",
563 .data = &st_pll3200c32_ddr_415,
564 },
565 {
566 .compatible = "st,stih416-plls-c32-a9",
567 .data = &st_pll3200c32_a9_416,
568 },
569 {
570 .compatible = "st,stih416-plls-c32-ddr",
571 .data = &st_pll3200c32_ddr_416,
572 },
573 {}
574 };
575
576 static void __init clkgen_c32_pll_setup(struct device_node *np)
577 {
578 const struct of_device_id *match;
579 struct clk *clk;
580 const char *parent_name, *pll_name;
581 void __iomem *pll_base;
582 int num_odfs, odf;
583 struct clk_onecell_data *clk_data;
584 struct clkgen_pll_data *data;
585
586 match = of_match_node(c32_pll_of_match, np);
587 if (!match) {
588 pr_err("%s: No matching data\n", __func__);
589 return;
590 }
591
592 data = (struct clkgen_pll_data *) match->data;
593
594 parent_name = of_clk_get_parent_name(np, 0);
595 if (!parent_name)
596 return;
597
598 pll_base = clkgen_get_register_base(np);
599 if (!pll_base)
600 return;
601
602 clk = clkgen_pll_register(parent_name, data, pll_base, np->name);
603 if (IS_ERR(clk))
604 return;
605
606 pll_name = __clk_get_name(clk);
607
608 num_odfs = data->num_odfs;
609
610 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
611 if (!clk_data)
612 return;
613
614 clk_data->clk_num = num_odfs;
615 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
616 GFP_KERNEL);
617
618 if (!clk_data->clks)
619 goto err;
620
621 for (odf = 0; odf < num_odfs; odf++) {
622 struct clk *clk;
623 const char *clk_name;
624
625 if (of_property_read_string_index(np, "clock-output-names",
626 odf, &clk_name))
627 return;
628
629 clk = clkgen_odf_register(pll_name, pll_base, data,
630 odf, &clkgena_c32_odf_lock, clk_name);
631 if (IS_ERR(clk))
632 goto err;
633
634 clk_data->clks[odf] = clk;
635 }
636
637 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
638 return;
639
640 err:
641 kfree(pll_name);
642 kfree(clk_data->clks);
643 kfree(clk_data);
644 }
645 CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
646
647 static struct of_device_id c32_gpu_pll_of_match[] = {
648 {
649 .compatible = "st,stih415-gpu-pll-c32",
650 .data = &st_pll1200c32_gpu_415,
651 },
652 {
653 .compatible = "st,stih416-gpu-pll-c32",
654 .data = &st_pll1200c32_gpu_416,
655 },
656 };
657
658 static void __init clkgengpu_c32_pll_setup(struct device_node *np)
659 {
660 const struct of_device_id *match;
661 struct clk *clk;
662 const char *parent_name;
663 void __iomem *reg;
664 const char *clk_name;
665 struct clkgen_pll_data *data;
666
667 match = of_match_node(c32_gpu_pll_of_match, np);
668 if (!match) {
669 pr_err("%s: No matching data\n", __func__);
670 return;
671 }
672
673 data = (struct clkgen_pll_data *)match->data;
674
675 parent_name = of_clk_get_parent_name(np, 0);
676 if (!parent_name)
677 return;
678
679 reg = clkgen_get_register_base(np);
680 if (!reg)
681 return;
682
683 if (of_property_read_string_index(np, "clock-output-names",
684 0, &clk_name))
685 return;
686
687 /*
688 * PLL 1200MHz output
689 */
690 clk = clkgen_pll_register(parent_name, data, reg, clk_name);
691
692 if (!IS_ERR(clk))
693 of_clk_add_provider(np, of_clk_src_simple_get, clk);
694
695 return;
696 }
697 CLK_OF_DECLARE(clkgengpu_c32_pll,
698 "st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup);
Linux with added FPC-III support