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mm: Initialize error in shmem_file_aio_read()
[linux/fpc-iii.git] / drivers / clk / tegra / clk-tegra30.c
blob8b10c38b6e3c677a19be8253ca11629a3a145445
1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/clkdev.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/tegra-powergate.h>
26 #include <dt-bindings/clock/tegra30-car.h>
27 #include "clk.h"
28 #include "clk-id.h"
29
30 #define OSC_CTRL 0x50
31 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
32 #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
33 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
34 #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
35 #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
36 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
37 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
38 #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
39 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
40
41 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
42 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
43 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
44 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
45
46 #define OSC_FREQ_DET 0x58
47 #define OSC_FREQ_DET_TRIG BIT(31)
48
49 #define OSC_FREQ_DET_STATUS 0x5c
50 #define OSC_FREQ_DET_BUSY BIT(31)
51 #define OSC_FREQ_DET_CNT_MASK 0xffff
52
53 #define CCLKG_BURST_POLICY 0x368
54 #define SUPER_CCLKG_DIVIDER 0x36c
55 #define CCLKLP_BURST_POLICY 0x370
56 #define SUPER_CCLKLP_DIVIDER 0x374
57 #define SCLK_BURST_POLICY 0x028
58 #define SUPER_SCLK_DIVIDER 0x02c
59
60 #define SYSTEM_CLK_RATE 0x030
61
62 #define TEGRA30_CLK_PERIPH_BANKS 5
63
64 #define PLLC_BASE 0x80
65 #define PLLC_MISC 0x8c
66 #define PLLM_BASE 0x90
67 #define PLLM_MISC 0x9c
68 #define PLLP_BASE 0xa0
69 #define PLLP_MISC 0xac
70 #define PLLX_BASE 0xe0
71 #define PLLX_MISC 0xe4
72 #define PLLD_BASE 0xd0
73 #define PLLD_MISC 0xdc
74 #define PLLD2_BASE 0x4b8
75 #define PLLD2_MISC 0x4bc
76 #define PLLE_BASE 0xe8
77 #define PLLE_MISC 0xec
78 #define PLLA_BASE 0xb0
79 #define PLLA_MISC 0xbc
80 #define PLLU_BASE 0xc0
81 #define PLLU_MISC 0xcc
82
83 #define PLL_MISC_LOCK_ENABLE 18
84 #define PLLDU_MISC_LOCK_ENABLE 22
85 #define PLLE_MISC_LOCK_ENABLE 9
86
87 #define PLL_BASE_LOCK BIT(27)
88 #define PLLE_MISC_LOCK BIT(11)
89
90 #define PLLE_AUX 0x48c
91 #define PLLC_OUT 0x84
92 #define PLLM_OUT 0x94
93 #define PLLP_OUTA 0xa4
94 #define PLLP_OUTB 0xa8
95 #define PLLA_OUT 0xb4
96
97 #define AUDIO_SYNC_CLK_I2S0 0x4a0
98 #define AUDIO_SYNC_CLK_I2S1 0x4a4
99 #define AUDIO_SYNC_CLK_I2S2 0x4a8
100 #define AUDIO_SYNC_CLK_I2S3 0x4ac
101 #define AUDIO_SYNC_CLK_I2S4 0x4b0
102 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
103
104 #define CLK_SOURCE_SPDIF_OUT 0x108
105 #define CLK_SOURCE_PWM 0x110
106 #define CLK_SOURCE_D_AUDIO 0x3d0
107 #define CLK_SOURCE_DAM0 0x3d8
108 #define CLK_SOURCE_DAM1 0x3dc
109 #define CLK_SOURCE_DAM2 0x3e0
110 #define CLK_SOURCE_3D2 0x3b0
111 #define CLK_SOURCE_2D 0x15c
112 #define CLK_SOURCE_HDMI 0x18c
113 #define CLK_SOURCE_DSIB 0xd0
114 #define CLK_SOURCE_SE 0x42c
115 #define CLK_SOURCE_EMC 0x19c
116
117 #define AUDIO_SYNC_DOUBLER 0x49c
118
119 #define UTMIP_PLL_CFG2 0x488
120 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
121 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
122 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
123 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
124 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
125
126 #define UTMIP_PLL_CFG1 0x484
127 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
128 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
129 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
130 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
131 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
132
133 /* Tegra CPU clock and reset control regs */
134 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
135 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
136 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
137 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
138 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
139
140 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
141 #define CPU_RESET(cpu) (0x1111ul << (cpu))
142
143 #define CLK_RESET_CCLK_BURST 0x20
144 #define CLK_RESET_CCLK_DIVIDER 0x24
145 #define CLK_RESET_PLLX_BASE 0xe0
146 #define CLK_RESET_PLLX_MISC 0xe4
147
148 #define CLK_RESET_SOURCE_CSITE 0x1d4
149
150 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
151 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
152 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
153 #define CLK_RESET_CCLK_IDLE_POLICY 1
154 #define CLK_RESET_CCLK_RUN_POLICY 2
155 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
156
157 /* PLLM override registers */
158 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
159
160 #ifdef CONFIG_PM_SLEEP
161 static struct cpu_clk_suspend_context {
162 u32 pllx_misc;
163 u32 pllx_base;
164
165 u32 cpu_burst;
166 u32 clk_csite_src;
167 u32 cclk_divider;
168 } tegra30_cpu_clk_sctx;
169 #endif
170
171 static void __iomem *clk_base;
172 static void __iomem *pmc_base;
173 static unsigned long input_freq;
174
175 static DEFINE_SPINLOCK(cml_lock);
176 static DEFINE_SPINLOCK(pll_d_lock);
177
178 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
179 _clk_num, _gate_flags, _clk_id) \
180 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
181 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
182 _clk_num, _gate_flags, _clk_id)
183
184 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
185 _clk_num, _gate_flags, _clk_id) \
186 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
187 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
188 _clk_num, _gate_flags, _clk_id)
189
190 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
191 _clk_num, _gate_flags, _clk_id) \
192 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
193 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
194 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
195 _gate_flags, _clk_id)
196
197 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
198 _mux_shift, _mux_width, _clk_num, \
199 _gate_flags, _clk_id) \
200 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
201 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
202 _clk_num, _gate_flags, \
203 _clk_id)
204
205 static struct clk **clks;
206
207 /*
208 * Structure defining the fields for USB UTMI clocks Parameters.
209 */
210 struct utmi_clk_param {
211 /* Oscillator Frequency in KHz */
212 u32 osc_frequency;
213 /* UTMIP PLL Enable Delay Count */
214 u8 enable_delay_count;
215 /* UTMIP PLL Stable count */
216 u8 stable_count;
217 /* UTMIP PLL Active delay count */
218 u8 active_delay_count;
219 /* UTMIP PLL Xtal frequency count */
220 u8 xtal_freq_count;
221 };
222
223 static const struct utmi_clk_param utmi_parameters[] = {
224 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
225 {13000000, 0x02, 0x33, 0x05, 0x7F},
226 {19200000, 0x03, 0x4B, 0x06, 0xBB},
227 {12000000, 0x02, 0x2F, 0x04, 0x76},
228 {26000000, 0x04, 0x66, 0x09, 0xFE},
229 {16800000, 0x03, 0x41, 0x0A, 0xA4},
230 };
231
232 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
233 { 12000000, 1040000000, 520, 6, 0, 8},
234 { 13000000, 1040000000, 480, 6, 0, 8},
235 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
236 { 19200000, 1040000000, 325, 6, 0, 6},
237 { 26000000, 1040000000, 520, 13, 0, 8},
238
239 { 12000000, 832000000, 416, 6, 0, 8},
240 { 13000000, 832000000, 832, 13, 0, 8},
241 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
242 { 19200000, 832000000, 260, 6, 0, 8},
243 { 26000000, 832000000, 416, 13, 0, 8},
244
245 { 12000000, 624000000, 624, 12, 0, 8},
246 { 13000000, 624000000, 624, 13, 0, 8},
247 { 16800000, 600000000, 520, 14, 0, 8},
248 { 19200000, 624000000, 520, 16, 0, 8},
249 { 26000000, 624000000, 624, 26, 0, 8},
250
251 { 12000000, 600000000, 600, 12, 0, 8},
252 { 13000000, 600000000, 600, 13, 0, 8},
253 { 16800000, 600000000, 500, 14, 0, 8},
254 { 19200000, 600000000, 375, 12, 0, 6},
255 { 26000000, 600000000, 600, 26, 0, 8},
256
257 { 12000000, 520000000, 520, 12, 0, 8},
258 { 13000000, 520000000, 520, 13, 0, 8},
259 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
260 { 19200000, 520000000, 325, 12, 0, 6},
261 { 26000000, 520000000, 520, 26, 0, 8},
262
263 { 12000000, 416000000, 416, 12, 0, 8},
264 { 13000000, 416000000, 416, 13, 0, 8},
265 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
266 { 19200000, 416000000, 260, 12, 0, 6},
267 { 26000000, 416000000, 416, 26, 0, 8},
268 { 0, 0, 0, 0, 0, 0 },
269 };
270
271 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
272 { 12000000, 666000000, 666, 12, 0, 8},
273 { 13000000, 666000000, 666, 13, 0, 8},
274 { 16800000, 666000000, 555, 14, 0, 8},
275 { 19200000, 666000000, 555, 16, 0, 8},
276 { 26000000, 666000000, 666, 26, 0, 8},
277 { 12000000, 600000000, 600, 12, 0, 8},
278 { 13000000, 600000000, 600, 13, 0, 8},
279 { 16800000, 600000000, 500, 14, 0, 8},
280 { 19200000, 600000000, 375, 12, 0, 6},
281 { 26000000, 600000000, 600, 26, 0, 8},
282 { 0, 0, 0, 0, 0, 0 },
283 };
284
285 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
286 { 12000000, 216000000, 432, 12, 1, 8},
287 { 13000000, 216000000, 432, 13, 1, 8},
288 { 16800000, 216000000, 360, 14, 1, 8},
289 { 19200000, 216000000, 360, 16, 1, 8},
290 { 26000000, 216000000, 432, 26, 1, 8},
291 { 0, 0, 0, 0, 0, 0 },
292 };
293
294 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
295 { 9600000, 564480000, 294, 5, 0, 4},
296 { 9600000, 552960000, 288, 5, 0, 4},
297 { 9600000, 24000000, 5, 2, 0, 1},
298
299 { 28800000, 56448000, 49, 25, 0, 1},
300 { 28800000, 73728000, 64, 25, 0, 1},
301 { 28800000, 24000000, 5, 6, 0, 1},
302 { 0, 0, 0, 0, 0, 0 },
303 };
304
305 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
306 { 12000000, 216000000, 216, 12, 0, 4},
307 { 13000000, 216000000, 216, 13, 0, 4},
308 { 16800000, 216000000, 180, 14, 0, 4},
309 { 19200000, 216000000, 180, 16, 0, 4},
310 { 26000000, 216000000, 216, 26, 0, 4},
311
312 { 12000000, 594000000, 594, 12, 0, 8},
313 { 13000000, 594000000, 594, 13, 0, 8},
314 { 16800000, 594000000, 495, 14, 0, 8},
315 { 19200000, 594000000, 495, 16, 0, 8},
316 { 26000000, 594000000, 594, 26, 0, 8},
317
318 { 12000000, 1000000000, 1000, 12, 0, 12},
319 { 13000000, 1000000000, 1000, 13, 0, 12},
320 { 19200000, 1000000000, 625, 12, 0, 8},
321 { 26000000, 1000000000, 1000, 26, 0, 12},
322
323 { 0, 0, 0, 0, 0, 0 },
324 };
325
326 static struct pdiv_map pllu_p[] = {
327 { .pdiv = 1, .hw_val = 1 },
328 { .pdiv = 2, .hw_val = 0 },
329 { .pdiv = 0, .hw_val = 0 },
330 };
331
332 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
333 { 12000000, 480000000, 960, 12, 0, 12},
334 { 13000000, 480000000, 960, 13, 0, 12},
335 { 16800000, 480000000, 400, 7, 0, 5},
336 { 19200000, 480000000, 200, 4, 0, 3},
337 { 26000000, 480000000, 960, 26, 0, 12},
338 { 0, 0, 0, 0, 0, 0 },
339 };
340
341 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
342 /* 1.7 GHz */
343 { 12000000, 1700000000, 850, 6, 0, 8},
344 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
345 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
346 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
347 { 26000000, 1700000000, 850, 13, 0, 8},
348
349 /* 1.6 GHz */
350 { 12000000, 1600000000, 800, 6, 0, 8},
351 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
352 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
353 { 19200000, 1600000000, 500, 6, 0, 8},
354 { 26000000, 1600000000, 800, 13, 0, 8},
355
356 /* 1.5 GHz */
357 { 12000000, 1500000000, 750, 6, 0, 8},
358 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
359 { 16800000, 1500000000, 625, 7, 0, 8},
360 { 19200000, 1500000000, 625, 8, 0, 8},
361 { 26000000, 1500000000, 750, 13, 0, 8},
362
363 /* 1.4 GHz */
364 { 12000000, 1400000000, 700, 6, 0, 8},
365 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
366 { 16800000, 1400000000, 1000, 12, 0, 8},
367 { 19200000, 1400000000, 875, 12, 0, 8},
368 { 26000000, 1400000000, 700, 13, 0, 8},
369
370 /* 1.3 GHz */
371 { 12000000, 1300000000, 975, 9, 0, 8},
372 { 13000000, 1300000000, 1000, 10, 0, 8},
373 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
374 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
375 { 26000000, 1300000000, 650, 13, 0, 8},
376
377 /* 1.2 GHz */
378 { 12000000, 1200000000, 1000, 10, 0, 8},
379 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
380 { 16800000, 1200000000, 1000, 14, 0, 8},
381 { 19200000, 1200000000, 1000, 16, 0, 8},
382 { 26000000, 1200000000, 600, 13, 0, 8},
383
384 /* 1.1 GHz */
385 { 12000000, 1100000000, 825, 9, 0, 8},
386 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
387 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
388 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
389 { 26000000, 1100000000, 550, 13, 0, 8},
390
391 /* 1 GHz */
392 { 12000000, 1000000000, 1000, 12, 0, 8},
393 { 13000000, 1000000000, 1000, 13, 0, 8},
394 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
395 { 19200000, 1000000000, 625, 12, 0, 8},
396 { 26000000, 1000000000, 1000, 26, 0, 8},
397
398 { 0, 0, 0, 0, 0, 0 },
399 };
400
401 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
402 /* PLLE special case: use cpcon field to store cml divider value */
403 { 12000000, 100000000, 150, 1, 18, 11},
404 { 216000000, 100000000, 200, 18, 24, 13},
405 { 0, 0, 0, 0, 0, 0 },
406 };
407
408 /* PLL parameters */
409 static struct tegra_clk_pll_params pll_c_params = {
410 .input_min = 2000000,
411 .input_max = 31000000,
412 .cf_min = 1000000,
413 .cf_max = 6000000,
414 .vco_min = 20000000,
415 .vco_max = 1400000000,
416 .base_reg = PLLC_BASE,
417 .misc_reg = PLLC_MISC,
418 .lock_mask = PLL_BASE_LOCK,
419 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
420 .lock_delay = 300,
421 .freq_table = pll_c_freq_table,
422 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
423 };
424
425 static struct div_nmp pllm_nmp = {
426 .divn_shift = 8,
427 .divn_width = 10,
428 .override_divn_shift = 5,
429 .divm_shift = 0,
430 .divm_width = 5,
431 .override_divm_shift = 0,
432 .divp_shift = 20,
433 .divp_width = 3,
434 .override_divp_shift = 15,
435 };
436
437 static struct tegra_clk_pll_params pll_m_params = {
438 .input_min = 2000000,
439 .input_max = 31000000,
440 .cf_min = 1000000,
441 .cf_max = 6000000,
442 .vco_min = 20000000,
443 .vco_max = 1200000000,
444 .base_reg = PLLM_BASE,
445 .misc_reg = PLLM_MISC,
446 .lock_mask = PLL_BASE_LOCK,
447 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
448 .lock_delay = 300,
449 .div_nmp = &pllm_nmp,
450 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
451 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
452 .freq_table = pll_m_freq_table,
453 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
454 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
455 };
456
457 static struct tegra_clk_pll_params pll_p_params = {
458 .input_min = 2000000,
459 .input_max = 31000000,
460 .cf_min = 1000000,
461 .cf_max = 6000000,
462 .vco_min = 20000000,
463 .vco_max = 1400000000,
464 .base_reg = PLLP_BASE,
465 .misc_reg = PLLP_MISC,
466 .lock_mask = PLL_BASE_LOCK,
467 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
468 .lock_delay = 300,
469 .freq_table = pll_p_freq_table,
470 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
471 .fixed_rate = 408000000,
472 };
473
474 static struct tegra_clk_pll_params pll_a_params = {
475 .input_min = 2000000,
476 .input_max = 31000000,
477 .cf_min = 1000000,
478 .cf_max = 6000000,
479 .vco_min = 20000000,
480 .vco_max = 1400000000,
481 .base_reg = PLLA_BASE,
482 .misc_reg = PLLA_MISC,
483 .lock_mask = PLL_BASE_LOCK,
484 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
485 .lock_delay = 300,
486 .freq_table = pll_a_freq_table,
487 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
488 };
489
490 static struct tegra_clk_pll_params pll_d_params = {
491 .input_min = 2000000,
492 .input_max = 40000000,
493 .cf_min = 1000000,
494 .cf_max = 6000000,
495 .vco_min = 40000000,
496 .vco_max = 1000000000,
497 .base_reg = PLLD_BASE,
498 .misc_reg = PLLD_MISC,
499 .lock_mask = PLL_BASE_LOCK,
500 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
501 .lock_delay = 1000,
502 .freq_table = pll_d_freq_table,
503 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
504 TEGRA_PLL_USE_LOCK,
505
506 };
507
508 static struct tegra_clk_pll_params pll_d2_params = {
509 .input_min = 2000000,
510 .input_max = 40000000,
511 .cf_min = 1000000,
512 .cf_max = 6000000,
513 .vco_min = 40000000,
514 .vco_max = 1000000000,
515 .base_reg = PLLD2_BASE,
516 .misc_reg = PLLD2_MISC,
517 .lock_mask = PLL_BASE_LOCK,
518 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
519 .lock_delay = 1000,
520 .freq_table = pll_d_freq_table,
521 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
522 TEGRA_PLL_USE_LOCK,
523 };
524
525 static struct tegra_clk_pll_params pll_u_params = {
526 .input_min = 2000000,
527 .input_max = 40000000,
528 .cf_min = 1000000,
529 .cf_max = 6000000,
530 .vco_min = 48000000,
531 .vco_max = 960000000,
532 .base_reg = PLLU_BASE,
533 .misc_reg = PLLU_MISC,
534 .lock_mask = PLL_BASE_LOCK,
535 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
536 .lock_delay = 1000,
537 .pdiv_tohw = pllu_p,
538 .freq_table = pll_u_freq_table,
539 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
540 };
541
542 static struct tegra_clk_pll_params pll_x_params = {
543 .input_min = 2000000,
544 .input_max = 31000000,
545 .cf_min = 1000000,
546 .cf_max = 6000000,
547 .vco_min = 20000000,
548 .vco_max = 1700000000,
549 .base_reg = PLLX_BASE,
550 .misc_reg = PLLX_MISC,
551 .lock_mask = PLL_BASE_LOCK,
552 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
553 .lock_delay = 300,
554 .freq_table = pll_x_freq_table,
555 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
556 TEGRA_PLL_USE_LOCK,
557 };
558
559 static struct tegra_clk_pll_params pll_e_params = {
560 .input_min = 12000000,
561 .input_max = 216000000,
562 .cf_min = 12000000,
563 .cf_max = 12000000,
564 .vco_min = 1200000000,
565 .vco_max = 2400000000U,
566 .base_reg = PLLE_BASE,
567 .misc_reg = PLLE_MISC,
568 .lock_mask = PLLE_MISC_LOCK,
569 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
570 .lock_delay = 300,
571 .freq_table = pll_e_freq_table,
572 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
573 .fixed_rate = 100000000,
574 };
575
576 static unsigned long tegra30_input_freq[] = {
577 [0] = 13000000,
578 [1] = 16800000,
579 [4] = 19200000,
580 [5] = 38400000,
581 [8] = 12000000,
582 [9] = 48000000,
583 [12] = 260000000,
584 };
585
586 static struct tegra_devclk devclks[] __initdata = {
587 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
588 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
589 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
590 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
591 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
592 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
593 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
594 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
595 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
596 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
597 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
598 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
599 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
600 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
601 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
602 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
603 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
604 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
605 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
606 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
607 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
608 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
609 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
610 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
611 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
612 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
613 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
614 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
615 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
616 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
617 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
618 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
619 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
620 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
621 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
622 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
623 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
624 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
625 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
626 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
627 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
628 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
629 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
630 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
631 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
632 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
633 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
634 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
635 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
636 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
637 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
638 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
639 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
640 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
641 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
642 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
643 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
644 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
645 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
646 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
647 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
648 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
649 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
650 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
651 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
652 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
653 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
654 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
655 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
656 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
657 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
658 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
659 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
660 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
661 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
662 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
663 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
664 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
665 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
666 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
667 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
668 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
669 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
670 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
671 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
672 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
673 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
674 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
675 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
676 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
677 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
678 { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
679 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
680 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
681 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
682 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
683 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
684 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
685 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
686 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
687 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
688 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
689 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
690 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
691 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
692 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
693 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
694 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
695 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
696 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
697 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
698 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
699 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
700 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
701 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
702 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
703 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
704 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
705 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
706 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
707 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
708 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
709 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
710 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
711 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
712 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
713 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
714 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
715 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
716 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
717 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
718 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
719 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
720 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
721 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
722 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
723 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
724 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
725 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
726 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
727 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
728 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
729 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
730 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
731 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
732 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
733 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
734 };
735
736 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
737 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
738 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
739 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
740 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
741 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
742 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
743 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
744 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
745 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
746 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
747 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
748 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
749 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
750 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
751 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
752 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
753 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
754 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
755 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
756 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
757 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
758 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
759 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
760 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
761 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
762 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
763 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
764 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
765 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
766 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
767 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
768 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
769 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
770 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
771 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
772 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
773 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
774 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
775 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
776 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
777 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
778 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
779 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
780 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
781 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
782 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
783 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
784 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
785 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
786 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
787 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
788 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
789 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
790 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
791 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
792 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
793 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
794 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
795 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
796 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
797 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
798 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
799 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
800 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
801 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
802 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
803 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
804 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
805 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
806 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
807 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
808 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
809 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
810 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
811 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
812 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
813 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
814 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
815 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
816 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
817 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
818 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
819 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
820 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
821 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
822 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
823 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
824 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
825 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
826 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
827 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
828 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
829 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
830 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
831 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
832 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
833 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
834 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
835 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
836 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
837 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
838 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
839 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
840 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
841 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
842 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
843 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
844 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
845 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
846 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
847 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
848 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
849 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
850 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
851 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
852 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
853 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
854 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
855 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
856 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
857 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
858 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
859 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
860 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
861
862 };
863
864 static void tegra30_utmi_param_configure(void)
865 {
866 u32 reg;
867 int i;
868
869 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
870 if (input_freq == utmi_parameters[i].osc_frequency)
871 break;
872 }
873
874 if (i >= ARRAY_SIZE(utmi_parameters)) {
875 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
876 return;
877 }
878
879 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
880
881 /* Program UTMIP PLL stable and active counts */
882 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
883 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
884 utmi_parameters[i].stable_count);
885
886 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
887
888 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
889 utmi_parameters[i].active_delay_count);
890
891 /* Remove power downs from UTMIP PLL control bits */
892 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
893 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
894 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
895
896 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
897
898 /* Program UTMIP PLL delay and oscillator frequency counts */
899 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
900 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
901
902 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
903 utmi_parameters[i].enable_delay_count);
904
905 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
906 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
907 utmi_parameters[i].xtal_freq_count);
908
909 /* Remove power downs from UTMIP PLL control bits */
910 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
911 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
912 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
913
914 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
915 }
916
917 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
918
919 static void __init tegra30_pll_init(void)
920 {
921 struct clk *clk;
922
923 /* PLLC */
924 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
925 &pll_c_params, NULL);
926 clks[TEGRA30_CLK_PLL_C] = clk;
927
928 /* PLLC_OUT1 */
929 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
930 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
931 8, 8, 1, NULL);
932 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
933 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
934 0, NULL);
935 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
936
937 /* PLLM */
938 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
939 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
940 &pll_m_params, NULL);
941 clks[TEGRA30_CLK_PLL_M] = clk;
942
943 /* PLLM_OUT1 */
944 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
945 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
946 8, 8, 1, NULL);
947 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
948 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
949 CLK_SET_RATE_PARENT, 0, NULL);
950 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
951
952 /* PLLX */
953 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
954 &pll_x_params, NULL);
955 clks[TEGRA30_CLK_PLL_X] = clk;
956
957 /* PLLX_OUT0 */
958 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
959 CLK_SET_RATE_PARENT, 1, 2);
960 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
961
962 /* PLLU */
963 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
964 &pll_u_params, NULL);
965 clks[TEGRA30_CLK_PLL_U] = clk;
966
967 tegra30_utmi_param_configure();
968
969 /* PLLD */
970 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
971 &pll_d_params, &pll_d_lock);
972 clks[TEGRA30_CLK_PLL_D] = clk;
973
974 /* PLLD_OUT0 */
975 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
976 CLK_SET_RATE_PARENT, 1, 2);
977 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
978
979 /* PLLD2 */
980 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
981 &pll_d2_params, NULL);
982 clks[TEGRA30_CLK_PLL_D2] = clk;
983
984 /* PLLD2_OUT0 */
985 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
986 CLK_SET_RATE_PARENT, 1, 2);
987 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
988
989 /* PLLE */
990 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
991 ARRAY_SIZE(pll_e_parents),
992 CLK_SET_RATE_NO_REPARENT,
993 clk_base + PLLE_AUX, 2, 1, 0, NULL);
994 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
995 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
996 clks[TEGRA30_CLK_PLL_E] = clk;
997 }
998
999 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1000 "pll_p_cclkg", "pll_p_out4_cclkg",
1001 "pll_p_out3_cclkg", "unused", "pll_x" };
1002 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1003 "pll_p_cclklp", "pll_p_out4_cclklp",
1004 "pll_p_out3_cclklp", "unused", "pll_x",
1005 "pll_x_out0" };
1006 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1007 "pll_p_out3", "pll_p_out2", "unused",
1008 "clk_32k", "pll_m_out1" };
1009
1010 static void __init tegra30_super_clk_init(void)
1011 {
1012 struct clk *clk;
1013
1014 /*
1015 * Clock input to cclk_g divided from pll_p using
1016 * U71 divider of cclk_g.
1017 */
1018 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1019 clk_base + SUPER_CCLKG_DIVIDER, 0,
1020 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1021 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1022
1023 /*
1024 * Clock input to cclk_g divided from pll_p_out3 using
1025 * U71 divider of cclk_g.
1026 */
1027 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1028 clk_base + SUPER_CCLKG_DIVIDER, 0,
1029 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1030 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1031
1032 /*
1033 * Clock input to cclk_g divided from pll_p_out4 using
1034 * U71 divider of cclk_g.
1035 */
1036 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1037 clk_base + SUPER_CCLKG_DIVIDER, 0,
1038 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1039 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1040
1041 /* CCLKG */
1042 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1043 ARRAY_SIZE(cclk_g_parents),
1044 CLK_SET_RATE_PARENT,
1045 clk_base + CCLKG_BURST_POLICY,
1046 0, 4, 0, 0, NULL);
1047 clks[TEGRA30_CLK_CCLK_G] = clk;
1048
1049 /*
1050 * Clock input to cclk_lp divided from pll_p using
1051 * U71 divider of cclk_lp.
1052 */
1053 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1054 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1055 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1056 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1057
1058 /*
1059 * Clock input to cclk_lp divided from pll_p_out3 using
1060 * U71 divider of cclk_lp.
1061 */
1062 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1063 clk_base + SUPER_CCLKG_DIVIDER, 0,
1064 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1065 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1066
1067 /*
1068 * Clock input to cclk_lp divided from pll_p_out4 using
1069 * U71 divider of cclk_lp.
1070 */
1071 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1072 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1073 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1074 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1075
1076 /* CCLKLP */
1077 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1078 ARRAY_SIZE(cclk_lp_parents),
1079 CLK_SET_RATE_PARENT,
1080 clk_base + CCLKLP_BURST_POLICY,
1081 TEGRA_DIVIDER_2, 4, 8, 9,
1082 NULL);
1083 clks[TEGRA30_CLK_CCLK_LP] = clk;
1084
1085 /* SCLK */
1086 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1087 ARRAY_SIZE(sclk_parents),
1088 CLK_SET_RATE_PARENT,
1089 clk_base + SCLK_BURST_POLICY,
1090 0, 4, 0, 0, NULL);
1091 clks[TEGRA30_CLK_SCLK] = clk;
1092
1093 /* twd */
1094 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1095 CLK_SET_RATE_PARENT, 1, 2);
1096 clks[TEGRA30_CLK_TWD] = clk;
1097
1098 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1099 }
1100
1101 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1102 "clk_m" };
1103 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1104 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1105 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1106 "clk_m" };
1107 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1108 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1109 "pll_a_out0", "pll_c",
1110 "pll_d2_out0", "clk_m" };
1111 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1112 "pll_d2_out0" };
1113 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1114
1115 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1116 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1117 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1118 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1119 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1120 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1121 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1122 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1123 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1124 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1125 };
1126
1127 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1128 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1129 };
1130
1131 static void __init tegra30_periph_clk_init(void)
1132 {
1133 struct tegra_periph_init_data *data;
1134 struct clk *clk;
1135 int i;
1136
1137 /* dsia */
1138 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1139 0, 48, periph_clk_enb_refcnt);
1140 clks[TEGRA30_CLK_DSIA] = clk;
1141
1142 /* pcie */
1143 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1144 70, periph_clk_enb_refcnt);
1145 clks[TEGRA30_CLK_PCIE] = clk;
1146
1147 /* afi */
1148 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1149 periph_clk_enb_refcnt);
1150 clks[TEGRA30_CLK_AFI] = clk;
1151
1152 /* emc */
1153 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1154 ARRAY_SIZE(mux_pllmcp_clkm),
1155 CLK_SET_RATE_NO_REPARENT,
1156 clk_base + CLK_SOURCE_EMC,
1157 30, 2, 0, NULL);
1158 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1159 57, periph_clk_enb_refcnt);
1160 clks[TEGRA30_CLK_EMC] = clk;
1161
1162 /* cml0 */
1163 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1164 0, 0, &cml_lock);
1165 clks[TEGRA30_CLK_CML0] = clk;
1166
1167 /* cml1 */
1168 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1169 1, 0, &cml_lock);
1170 clks[TEGRA30_CLK_CML1] = clk;
1171
1172 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1173 data = &tegra_periph_clk_list[i];
1174 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1175 data->num_parents, &data->periph,
1176 clk_base, data->offset, data->flags);
1177 clks[data->clk_id] = clk;
1178 }
1179
1180 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1181 data = &tegra_periph_nodiv_clk_list[i];
1182 clk = tegra_clk_register_periph_nodiv(data->name,
1183 data->p.parent_names,
1184 data->num_parents, &data->periph,
1185 clk_base, data->offset);
1186 clks[data->clk_id] = clk;
1187 }
1188
1189 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1190 }
1191
1192 /* Tegra30 CPU clock and reset control functions */
1193 static void tegra30_wait_cpu_in_reset(u32 cpu)
1194 {
1195 unsigned int reg;
1196
1197 do {
1198 reg = readl(clk_base +
1199 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1200 cpu_relax();
1201 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1202
1203 return;
1204 }
1205
1206 static void tegra30_put_cpu_in_reset(u32 cpu)
1207 {
1208 writel(CPU_RESET(cpu),
1209 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1210 dmb();
1211 }
1212
1213 static void tegra30_cpu_out_of_reset(u32 cpu)
1214 {
1215 writel(CPU_RESET(cpu),
1216 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1217 wmb();
1218 }
1219
1220
1221 static void tegra30_enable_cpu_clock(u32 cpu)
1222 {
1223 unsigned int reg;
1224
1225 writel(CPU_CLOCK(cpu),
1226 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1227 reg = readl(clk_base +
1228 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1229 }
1230
1231 static void tegra30_disable_cpu_clock(u32 cpu)
1232 {
1233
1234 unsigned int reg;
1235
1236 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1237 writel(reg | CPU_CLOCK(cpu),
1238 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1239 }
1240
1241 #ifdef CONFIG_PM_SLEEP
1242 static bool tegra30_cpu_rail_off_ready(void)
1243 {
1244 unsigned int cpu_rst_status;
1245 int cpu_pwr_status;
1246
1247 cpu_rst_status = readl(clk_base +
1248 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1249 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1250 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1251 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1252
1253 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1254 return false;
1255
1256 return true;
1257 }
1258
1259 static void tegra30_cpu_clock_suspend(void)
1260 {
1261 /* switch coresite to clk_m, save off original source */
1262 tegra30_cpu_clk_sctx.clk_csite_src =
1263 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1264 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1265
1266 tegra30_cpu_clk_sctx.cpu_burst =
1267 readl(clk_base + CLK_RESET_CCLK_BURST);
1268 tegra30_cpu_clk_sctx.pllx_base =
1269 readl(clk_base + CLK_RESET_PLLX_BASE);
1270 tegra30_cpu_clk_sctx.pllx_misc =
1271 readl(clk_base + CLK_RESET_PLLX_MISC);
1272 tegra30_cpu_clk_sctx.cclk_divider =
1273 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1274 }
1275
1276 static void tegra30_cpu_clock_resume(void)
1277 {
1278 unsigned int reg, policy;
1279
1280 /* Is CPU complex already running on PLLX? */
1281 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1282 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1283
1284 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1285 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1286 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1287 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1288 else
1289 BUG();
1290
1291 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1292 /* restore PLLX settings if CPU is on different PLL */
1293 writel(tegra30_cpu_clk_sctx.pllx_misc,
1294 clk_base + CLK_RESET_PLLX_MISC);
1295 writel(tegra30_cpu_clk_sctx.pllx_base,
1296 clk_base + CLK_RESET_PLLX_BASE);
1297
1298 /* wait for PLL stabilization if PLLX was enabled */
1299 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1300 udelay(300);
1301 }
1302
1303 /*
1304 * Restore original burst policy setting for calls resulting from CPU
1305 * LP2 in idle or system suspend.
1306 */
1307 writel(tegra30_cpu_clk_sctx.cclk_divider,
1308 clk_base + CLK_RESET_CCLK_DIVIDER);
1309 writel(tegra30_cpu_clk_sctx.cpu_burst,
1310 clk_base + CLK_RESET_CCLK_BURST);
1311
1312 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1313 clk_base + CLK_RESET_SOURCE_CSITE);
1314 }
1315 #endif
1316
1317 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1318 .wait_for_reset = tegra30_wait_cpu_in_reset,
1319 .put_in_reset = tegra30_put_cpu_in_reset,
1320 .out_of_reset = tegra30_cpu_out_of_reset,
1321 .enable_clock = tegra30_enable_cpu_clock,
1322 .disable_clock = tegra30_disable_cpu_clock,
1323 #ifdef CONFIG_PM_SLEEP
1324 .rail_off_ready = tegra30_cpu_rail_off_ready,
1325 .suspend = tegra30_cpu_clock_suspend,
1326 .resume = tegra30_cpu_clock_resume,
1327 #endif
1328 };
1329
1330 static struct tegra_clk_init_table init_table[] __initdata = {
1331 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1332 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1333 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1334 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1335 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1336 {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1337 {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1338 {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1339 {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1340 {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1341 {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1342 {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1343 {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1344 {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1345 {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1346 {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1347 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1348 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1349 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1350 {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1351 {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1352 {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1353 {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1354 {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1355 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1356 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1357 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1358 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1359 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1360 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1361 {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1362 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1363 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1364 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1365 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1366 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1367 {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1368 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1369 };
1370
1371 static void __init tegra30_clock_apply_init_table(void)
1372 {
1373 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1374 }
1375
1376 /*
1377 * Some clocks may be used by different drivers depending on the board
1378 * configuration. List those here to register them twice in the clock lookup
1379 * table under two names.
1380 */
1381 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1382 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1383 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1384 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1385 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1386 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1387 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1388 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1389 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1390 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1391 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1392 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1393 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1394 };
1395
1396 static const struct of_device_id pmc_match[] __initconst = {
1397 { .compatible = "nvidia,tegra30-pmc" },
1398 {},
1399 };
1400
1401 static void __init tegra30_clock_init(struct device_node *np)
1402 {
1403 struct device_node *node;
1404
1405 clk_base = of_iomap(np, 0);
1406 if (!clk_base) {
1407 pr_err("ioremap tegra30 CAR failed\n");
1408 return;
1409 }
1410
1411 node = of_find_matching_node(NULL, pmc_match);
1412 if (!node) {
1413 pr_err("Failed to find pmc node\n");
1414 BUG();
1415 }
1416
1417 pmc_base = of_iomap(node, 0);
1418 if (!pmc_base) {
1419 pr_err("Can't map pmc registers\n");
1420 BUG();
1421 }
1422
1423 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1424 TEGRA30_CLK_PERIPH_BANKS);
1425 if (!clks)
1426 return;
1427
1428 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1429 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
1430 return;
1431
1432
1433 tegra_fixed_clk_init(tegra30_clks);
1434 tegra30_pll_init();
1435 tegra30_super_clk_init();
1436 tegra30_periph_clk_init();
1437 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
1438 tegra_pmc_clk_init(pmc_base, tegra30_clks);
1439
1440 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1441
1442 tegra_add_of_provider(np);
1443 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1444
1445 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1446
1447 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1448 }
1449 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
Linux with added FPC-III support