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mm: Initialize error in shmem_file_aio_read()
[linux/fpc-iii.git] / drivers / usb / chipidea / core.c
blobca6831c5b763053d146d8c7bbae2f10d85e3c3d1
1 /*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - OTG
46 * - Interrupt Traffic
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
50 */
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
58 #include <linux/io.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
67 #include <linux/of.h>
68 #include <linux/phy.h>
69 #include <linux/regulator/consumer.h>
70
71 #include "ci.h"
72 #include "udc.h"
73 #include "bits.h"
74 #include "host.h"
75 #include "debug.h"
76 #include "otg.h"
77
78 /* Controller register map */
79 static const u8 ci_regs_nolpm[] = {
80 [CAP_CAPLENGTH] = 0x00U,
81 [CAP_HCCPARAMS] = 0x08U,
82 [CAP_DCCPARAMS] = 0x24U,
83 [CAP_TESTMODE] = 0x38U,
84 [OP_USBCMD] = 0x00U,
85 [OP_USBSTS] = 0x04U,
86 [OP_USBINTR] = 0x08U,
87 [OP_DEVICEADDR] = 0x14U,
88 [OP_ENDPTLISTADDR] = 0x18U,
89 [OP_PORTSC] = 0x44U,
90 [OP_DEVLC] = 0x84U,
91 [OP_OTGSC] = 0x64U,
92 [OP_USBMODE] = 0x68U,
93 [OP_ENDPTSETUPSTAT] = 0x6CU,
94 [OP_ENDPTPRIME] = 0x70U,
95 [OP_ENDPTFLUSH] = 0x74U,
96 [OP_ENDPTSTAT] = 0x78U,
97 [OP_ENDPTCOMPLETE] = 0x7CU,
98 [OP_ENDPTCTRL] = 0x80U,
99 };
100
101 static const u8 ci_regs_lpm[] = {
102 [CAP_CAPLENGTH] = 0x00U,
103 [CAP_HCCPARAMS] = 0x08U,
104 [CAP_DCCPARAMS] = 0x24U,
105 [CAP_TESTMODE] = 0xFCU,
106 [OP_USBCMD] = 0x00U,
107 [OP_USBSTS] = 0x04U,
108 [OP_USBINTR] = 0x08U,
109 [OP_DEVICEADDR] = 0x14U,
110 [OP_ENDPTLISTADDR] = 0x18U,
111 [OP_PORTSC] = 0x44U,
112 [OP_DEVLC] = 0x84U,
113 [OP_OTGSC] = 0xC4U,
114 [OP_USBMODE] = 0xC8U,
115 [OP_ENDPTSETUPSTAT] = 0xD8U,
116 [OP_ENDPTPRIME] = 0xDCU,
117 [OP_ENDPTFLUSH] = 0xE0U,
118 [OP_ENDPTSTAT] = 0xE4U,
119 [OP_ENDPTCOMPLETE] = 0xE8U,
120 [OP_ENDPTCTRL] = 0xECU,
121 };
122
123 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
124 {
125 int i;
126
127 for (i = 0; i < OP_ENDPTCTRL; i++)
128 ci->hw_bank.regmap[i] =
129 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
130 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
131
132 for (; i <= OP_LAST; i++)
133 ci->hw_bank.regmap[i] = ci->hw_bank.op +
134 4 * (i - OP_ENDPTCTRL) +
135 (is_lpm
136 ? ci_regs_lpm[OP_ENDPTCTRL]
137 : ci_regs_nolpm[OP_ENDPTCTRL]);
138
139 return 0;
140 }
141
142 /**
143 * hw_port_test_set: writes port test mode (execute without interruption)
144 * @mode: new value
145 *
146 * This function returns an error code
147 */
148 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
149 {
150 const u8 TEST_MODE_MAX = 7;
151
152 if (mode > TEST_MODE_MAX)
153 return -EINVAL;
154
155 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
156 return 0;
157 }
158
159 /**
160 * hw_port_test_get: reads port test mode value
161 *
162 * This function returns port test mode value
163 */
164 u8 hw_port_test_get(struct ci_hdrc *ci)
165 {
166 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
167 }
168
169 /* The PHY enters/leaves low power mode */
170 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
171 {
172 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
173 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
174
175 if (enable && !lpm) {
176 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
177 PORTSC_PHCD(ci->hw_bank.lpm));
178 } else if (!enable && lpm) {
179 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
180 0);
181 /*
182 * The controller needs at least 1ms to reflect
183 * PHY's status, the PHY also needs some time (less
184 * than 1ms) to leave low power mode.
185 */
186 usleep_range(1500, 2000);
187 }
188 }
189
190 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
191 {
192 u32 reg;
193
194 /* bank is a module variable */
195 ci->hw_bank.abs = base;
196
197 ci->hw_bank.cap = ci->hw_bank.abs;
198 ci->hw_bank.cap += ci->platdata->capoffset;
199 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
200
201 hw_alloc_regmap(ci, false);
202 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
203 __ffs(HCCPARAMS_LEN);
204 ci->hw_bank.lpm = reg;
205 if (reg)
206 hw_alloc_regmap(ci, !!reg);
207 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
208 ci->hw_bank.size += OP_LAST;
209 ci->hw_bank.size /= sizeof(u32);
210
211 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
212 __ffs(DCCPARAMS_DEN);
213 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
214
215 if (ci->hw_ep_max > ENDPT_MAX)
216 return -ENODEV;
217
218 ci_hdrc_enter_lpm(ci, false);
219
220 /* Disable all interrupts bits */
221 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
222
223 /* Clear all interrupts status bits*/
224 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
225
226 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
227 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
228
229 /* setup lock mode ? */
230
231 /* ENDPTSETUPSTAT is '0' by default */
232
233 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
234
235 return 0;
236 }
237
238 static void hw_phymode_configure(struct ci_hdrc *ci)
239 {
240 u32 portsc, lpm, sts = 0;
241
242 switch (ci->platdata->phy_mode) {
243 case USBPHY_INTERFACE_MODE_UTMI:
244 portsc = PORTSC_PTS(PTS_UTMI);
245 lpm = DEVLC_PTS(PTS_UTMI);
246 break;
247 case USBPHY_INTERFACE_MODE_UTMIW:
248 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
249 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
250 break;
251 case USBPHY_INTERFACE_MODE_ULPI:
252 portsc = PORTSC_PTS(PTS_ULPI);
253 lpm = DEVLC_PTS(PTS_ULPI);
254 break;
255 case USBPHY_INTERFACE_MODE_SERIAL:
256 portsc = PORTSC_PTS(PTS_SERIAL);
257 lpm = DEVLC_PTS(PTS_SERIAL);
258 sts = 1;
259 break;
260 case USBPHY_INTERFACE_MODE_HSIC:
261 portsc = PORTSC_PTS(PTS_HSIC);
262 lpm = DEVLC_PTS(PTS_HSIC);
263 break;
264 default:
265 return;
266 }
267
268 if (ci->hw_bank.lpm) {
269 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
270 if (sts)
271 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
272 } else {
273 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
274 if (sts)
275 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
276 }
277 }
278
279 /**
280 * hw_device_reset: resets chip (execute without interruption)
281 * @ci: the controller
282 *
283 * This function returns an error code
284 */
285 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
286 {
287 /* should flush & stop before reset */
288 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
289 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
290
291 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
292 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
293 udelay(10); /* not RTOS friendly */
294
295 if (ci->platdata->notify_event)
296 ci->platdata->notify_event(ci,
297 CI_HDRC_CONTROLLER_RESET_EVENT);
298
299 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
300 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
301
302 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
303 if (ci->hw_bank.lpm)
304 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
305 else
306 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
307 }
308
309 /* USBMODE should be configured step by step */
310 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
311 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
312 /* HW >= 2.3 */
313 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
314
315 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
316 pr_err("cannot enter in %s mode", ci_role(ci)->name);
317 pr_err("lpm = %i", ci->hw_bank.lpm);
318 return -ENODEV;
319 }
320
321 return 0;
322 }
323
324 /**
325 * hw_wait_reg: wait the register value
326 *
327 * Sometimes, it needs to wait register value before going on.
328 * Eg, when switch to device mode, the vbus value should be lower
329 * than OTGSC_BSV before connects to host.
330 *
331 * @ci: the controller
332 * @reg: register index
333 * @mask: mast bit
334 * @value: the bit value to wait
335 * @timeout_ms: timeout in millisecond
336 *
337 * This function returns an error code if timeout
338 */
339 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
340 u32 value, unsigned int timeout_ms)
341 {
342 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
343
344 while (hw_read(ci, reg, mask) != value) {
345 if (time_after(jiffies, elapse)) {
346 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
347 mask, reg);
348 return -ETIMEDOUT;
349 }
350 msleep(20);
351 }
352
353 return 0;
354 }
355
356 static irqreturn_t ci_irq(int irq, void *data)
357 {
358 struct ci_hdrc *ci = data;
359 irqreturn_t ret = IRQ_NONE;
360 u32 otgsc = 0;
361
362 if (ci->is_otg)
363 otgsc = hw_read(ci, OP_OTGSC, ~0);
364
365 /*
366 * Handle id change interrupt, it indicates device/host function
367 * switch.
368 */
369 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
370 ci->id_event = true;
371 ci_clear_otg_interrupt(ci, OTGSC_IDIS);
372 disable_irq_nosync(ci->irq);
373 queue_work(ci->wq, &ci->work);
374 return IRQ_HANDLED;
375 }
376
377 /*
378 * Handle vbus change interrupt, it indicates device connection
379 * and disconnection events.
380 */
381 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
382 ci->b_sess_valid_event = true;
383 ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
384 disable_irq_nosync(ci->irq);
385 queue_work(ci->wq, &ci->work);
386 return IRQ_HANDLED;
387 }
388
389 /* Handle device/host interrupt */
390 if (ci->role != CI_ROLE_END)
391 ret = ci_role(ci)->irq(ci);
392
393 return ret;
394 }
395
396 static int ci_get_platdata(struct device *dev,
397 struct ci_hdrc_platform_data *platdata)
398 {
399 if (!platdata->phy_mode)
400 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
401
402 if (!platdata->dr_mode)
403 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
404
405 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
406 platdata->dr_mode = USB_DR_MODE_OTG;
407
408 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
409 /* Get the vbus regulator */
410 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
411 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
412 return -EPROBE_DEFER;
413 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
414 /* no vbus regualator is needed */
415 platdata->reg_vbus = NULL;
416 } else if (IS_ERR(platdata->reg_vbus)) {
417 dev_err(dev, "Getting regulator error: %ld\n",
418 PTR_ERR(platdata->reg_vbus));
419 return PTR_ERR(platdata->reg_vbus);
420 }
421 }
422
423 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
424 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
425
426 return 0;
427 }
428
429 static DEFINE_IDA(ci_ida);
430
431 struct platform_device *ci_hdrc_add_device(struct device *dev,
432 struct resource *res, int nres,
433 struct ci_hdrc_platform_data *platdata)
434 {
435 struct platform_device *pdev;
436 int id, ret;
437
438 ret = ci_get_platdata(dev, platdata);
439 if (ret)
440 return ERR_PTR(ret);
441
442 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
443 if (id < 0)
444 return ERR_PTR(id);
445
446 pdev = platform_device_alloc("ci_hdrc", id);
447 if (!pdev) {
448 ret = -ENOMEM;
449 goto put_id;
450 }
451
452 pdev->dev.parent = dev;
453 pdev->dev.dma_mask = dev->dma_mask;
454 pdev->dev.dma_parms = dev->dma_parms;
455 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
456
457 ret = platform_device_add_resources(pdev, res, nres);
458 if (ret)
459 goto err;
460
461 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
462 if (ret)
463 goto err;
464
465 ret = platform_device_add(pdev);
466 if (ret)
467 goto err;
468
469 return pdev;
470
471 err:
472 platform_device_put(pdev);
473 put_id:
474 ida_simple_remove(&ci_ida, id);
475 return ERR_PTR(ret);
476 }
477 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
478
479 void ci_hdrc_remove_device(struct platform_device *pdev)
480 {
481 int id = pdev->id;
482 platform_device_unregister(pdev);
483 ida_simple_remove(&ci_ida, id);
484 }
485 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
486
487 static inline void ci_role_destroy(struct ci_hdrc *ci)
488 {
489 ci_hdrc_gadget_destroy(ci);
490 ci_hdrc_host_destroy(ci);
491 if (ci->is_otg)
492 ci_hdrc_otg_destroy(ci);
493 }
494
495 static void ci_get_otg_capable(struct ci_hdrc *ci)
496 {
497 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
498 ci->is_otg = false;
499 else
500 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
501 DCCPARAMS_DC | DCCPARAMS_HC)
502 == (DCCPARAMS_DC | DCCPARAMS_HC));
503 if (ci->is_otg) {
504 dev_dbg(ci->dev, "It is OTG capable controller\n");
505 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
506 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
507 }
508 }
509
510 static int ci_hdrc_probe(struct platform_device *pdev)
511 {
512 struct device *dev = &pdev->dev;
513 struct ci_hdrc *ci;
514 struct resource *res;
515 void __iomem *base;
516 int ret;
517 enum usb_dr_mode dr_mode;
518
519 if (!dev_get_platdata(dev)) {
520 dev_err(dev, "platform data missing\n");
521 return -ENODEV;
522 }
523
524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 base = devm_ioremap_resource(dev, res);
526 if (IS_ERR(base))
527 return PTR_ERR(base);
528
529 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
530 if (!ci) {
531 dev_err(dev, "can't allocate device\n");
532 return -ENOMEM;
533 }
534
535 ci->dev = dev;
536 ci->platdata = dev_get_platdata(dev);
537 ci->imx28_write_fix = !!(ci->platdata->flags &
538 CI_HDRC_IMX28_WRITE_FIX);
539
540 ret = hw_device_init(ci, base);
541 if (ret < 0) {
542 dev_err(dev, "can't initialize hardware\n");
543 return -ENODEV;
544 }
545
546 hw_phymode_configure(ci);
547
548 if (ci->platdata->phy)
549 ci->transceiver = ci->platdata->phy;
550 else
551 ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
552
553 if (IS_ERR(ci->transceiver)) {
554 ret = PTR_ERR(ci->transceiver);
555 /*
556 * if -ENXIO is returned, it means PHY layer wasn't
557 * enabled, so it makes no sense to return -EPROBE_DEFER
558 * in that case, since no PHY driver will ever probe.
559 */
560 if (ret == -ENXIO)
561 return ret;
562
563 dev_err(dev, "no usb2 phy configured\n");
564 return -EPROBE_DEFER;
565 }
566
567 ret = usb_phy_init(ci->transceiver);
568 if (ret) {
569 dev_err(dev, "unable to init phy: %d\n", ret);
570 return ret;
571 }
572
573 ci->hw_bank.phys = res->start;
574
575 ci->irq = platform_get_irq(pdev, 0);
576 if (ci->irq < 0) {
577 dev_err(dev, "missing IRQ\n");
578 ret = ci->irq;
579 goto deinit_phy;
580 }
581
582 ci_get_otg_capable(ci);
583
584 dr_mode = ci->platdata->dr_mode;
585 /* initialize role(s) before the interrupt is requested */
586 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
587 ret = ci_hdrc_host_init(ci);
588 if (ret)
589 dev_info(dev, "doesn't support host\n");
590 }
591
592 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
593 ret = ci_hdrc_gadget_init(ci);
594 if (ret)
595 dev_info(dev, "doesn't support gadget\n");
596 }
597
598 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
599 dev_err(dev, "no supported roles\n");
600 ret = -ENODEV;
601 goto deinit_phy;
602 }
603
604 if (ci->is_otg) {
605 ret = ci_hdrc_otg_init(ci);
606 if (ret) {
607 dev_err(dev, "init otg fails, ret = %d\n", ret);
608 goto stop;
609 }
610 }
611
612 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
613 if (ci->is_otg) {
614 /*
615 * ID pin needs 1ms debouce time,
616 * we delay 2ms for safe.
617 */
618 mdelay(2);
619 ci->role = ci_otg_role(ci);
620 ci_enable_otg_interrupt(ci, OTGSC_IDIE);
621 } else {
622 /*
623 * If the controller is not OTG capable, but support
624 * role switch, the defalt role is gadget, and the
625 * user can switch it through debugfs.
626 */
627 ci->role = CI_ROLE_GADGET;
628 }
629 } else {
630 ci->role = ci->roles[CI_ROLE_HOST]
631 ? CI_ROLE_HOST
632 : CI_ROLE_GADGET;
633 }
634
635 /* only update vbus status for peripheral */
636 if (ci->role == CI_ROLE_GADGET)
637 ci_handle_vbus_change(ci);
638
639 ret = ci_role_start(ci, ci->role);
640 if (ret) {
641 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
642 goto stop;
643 }
644
645 platform_set_drvdata(pdev, ci);
646 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
647 ci);
648 if (ret)
649 goto stop;
650
651 ret = dbg_create_files(ci);
652 if (!ret)
653 return 0;
654
655 free_irq(ci->irq, ci);
656 stop:
657 ci_role_destroy(ci);
658 deinit_phy:
659 usb_phy_shutdown(ci->transceiver);
660
661 return ret;
662 }
663
664 static int ci_hdrc_remove(struct platform_device *pdev)
665 {
666 struct ci_hdrc *ci = platform_get_drvdata(pdev);
667
668 dbg_remove_files(ci);
669 free_irq(ci->irq, ci);
670 ci_role_destroy(ci);
671 ci_hdrc_enter_lpm(ci, true);
672 usb_phy_shutdown(ci->transceiver);
673 kfree(ci->hw_bank.regmap);
674
675 return 0;
676 }
677
678 static struct platform_driver ci_hdrc_driver = {
679 .probe = ci_hdrc_probe,
680 .remove = ci_hdrc_remove,
681 .driver = {
682 .name = "ci_hdrc",
683 },
684 };
685
686 module_platform_driver(ci_hdrc_driver);
687
688 MODULE_ALIAS("platform:ci_hdrc");
689 MODULE_LICENSE("GPL v2");
690 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
691 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Linux with added FPC-III support