drivers/pinctrl/intel/pinctrl-sunrisepoint.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Sunrisepoint PCH pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm.h>
  14 #include <linux/pinctrl/pinctrl.h>
  15
  16 #include "pinctrl-intel.h"
  17
  18 #define SPT_PAD_OWN     0x020
  19 #define SPT_PADCFGLOCK  0x0a0
  20 #define SPT_HOSTSW_OWN  0x0d0
  21 #define SPT_GPI_IE      0x120
  22
  23 #define SPT_COMMUNITY(b, s, e)                          \
  24         {                                               \
  25                 .barno = (b),                           \
  26                 .padown_offset = SPT_PAD_OWN,           \
  27                 .padcfglock_offset = SPT_PADCFGLOCK,    \
  28                 .hostown_offset = SPT_HOSTSW_OWN,       \
  29                 .ie_offset = SPT_GPI_IE,                \
  30                 .gpp_size = 24,                         \
  31                 .gpp_num_padown_regs = 4,               \
  32                 .pin_base = (s),                        \
  33                 .npins = ((e) - (s) + 1),               \
  34         }
  35
  36 #define SPTH_GPP(r, s, e, g)                            \
  37         {                                               \
  38                 .reg_num = (r),                         \
  39                 .base = (s),                            \
  40                 .size = ((e) - (s) + 1),                \
  41                 .gpio_base = (g),                       \
  42         }
  43
  44 #define SPTH_COMMUNITY(b, s, e, g)                      \
  45         {                                               \
  46                 .barno = (b),                           \
  47                 .padown_offset = SPT_PAD_OWN,           \
  48                 .padcfglock_offset = SPT_PADCFGLOCK,    \
  49                 .hostown_offset = SPT_HOSTSW_OWN,       \
  50                 .ie_offset = SPT_GPI_IE,                \
  51                 .pin_base = (s),                        \
  52                 .npins = ((e) - (s) + 1),               \
  53                 .gpps = (g),                            \
  54                 .ngpps = ARRAY_SIZE(g),                 \
  55         }
  56
  57 /* Sunrisepoint-LP */
  58 static const struct pinctrl_pin_desc sptlp_pins[] = {
  59         /* GPP_A */
  60         PINCTRL_PIN(0, "RCINB"),
  61         PINCTRL_PIN(1, "LAD_0"),
  62         PINCTRL_PIN(2, "LAD_1"),
  63         PINCTRL_PIN(3, "LAD_2"),
  64         PINCTRL_PIN(4, "LAD_3"),
  65         PINCTRL_PIN(5, "LFRAMEB"),
  66         PINCTRL_PIN(6, "SERIQ"),
  67         PINCTRL_PIN(7, "PIRQAB"),
  68         PINCTRL_PIN(8, "CLKRUNB"),
  69         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
  70         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
  71         PINCTRL_PIN(11, "PMEB"),
  72         PINCTRL_PIN(12, "BM_BUSYB"),
  73         PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
  74         PINCTRL_PIN(14, "SUS_STATB"),
  75         PINCTRL_PIN(15, "SUSACKB"),
  76         PINCTRL_PIN(16, "SD_1P8_SEL"),
  77         PINCTRL_PIN(17, "SD_PWR_EN_B"),
  78         PINCTRL_PIN(18, "ISH_GP_0"),
  79         PINCTRL_PIN(19, "ISH_GP_1"),
  80         PINCTRL_PIN(20, "ISH_GP_2"),
  81         PINCTRL_PIN(21, "ISH_GP_3"),
  82         PINCTRL_PIN(22, "ISH_GP_4"),
  83         PINCTRL_PIN(23, "ISH_GP_5"),
  84         /* GPP_B */
  85         PINCTRL_PIN(24, "CORE_VID_0"),
  86         PINCTRL_PIN(25, "CORE_VID_1"),
  87         PINCTRL_PIN(26, "VRALERTB"),
  88         PINCTRL_PIN(27, "CPU_GP_2"),
  89         PINCTRL_PIN(28, "CPU_GP_3"),
  90         PINCTRL_PIN(29, "SRCCLKREQB_0"),
  91         PINCTRL_PIN(30, "SRCCLKREQB_1"),
  92         PINCTRL_PIN(31, "SRCCLKREQB_2"),
  93         PINCTRL_PIN(32, "SRCCLKREQB_3"),
  94         PINCTRL_PIN(33, "SRCCLKREQB_4"),
  95         PINCTRL_PIN(34, "SRCCLKREQB_5"),
  96         PINCTRL_PIN(35, "EXT_PWR_GATEB"),
  97         PINCTRL_PIN(36, "SLP_S0B"),
  98         PINCTRL_PIN(37, "PLTRSTB"),
  99         PINCTRL_PIN(38, "SPKR"),
 100         PINCTRL_PIN(39, "GSPI0_CSB"),
 101         PINCTRL_PIN(40, "GSPI0_CLK"),
 102         PINCTRL_PIN(41, "GSPI0_MISO"),
 103         PINCTRL_PIN(42, "GSPI0_MOSI"),
 104         PINCTRL_PIN(43, "GSPI1_CSB"),
 105         PINCTRL_PIN(44, "GSPI1_CLK"),
 106         PINCTRL_PIN(45, "GSPI1_MISO"),
 107         PINCTRL_PIN(46, "GSPI1_MOSI"),
 108         PINCTRL_PIN(47, "SML1ALERTB"),
 109         /* GPP_C */
 110         PINCTRL_PIN(48, "SMBCLK"),
 111         PINCTRL_PIN(49, "SMBDATA"),
 112         PINCTRL_PIN(50, "SMBALERTB"),
 113         PINCTRL_PIN(51, "SML0CLK"),
 114         PINCTRL_PIN(52, "SML0DATA"),
 115         PINCTRL_PIN(53, "SML0ALERTB"),
 116         PINCTRL_PIN(54, "SML1CLK"),
 117         PINCTRL_PIN(55, "SML1DATA"),
 118         PINCTRL_PIN(56, "UART0_RXD"),
 119         PINCTRL_PIN(57, "UART0_TXD"),
 120         PINCTRL_PIN(58, "UART0_RTSB"),
 121         PINCTRL_PIN(59, "UART0_CTSB"),
 122         PINCTRL_PIN(60, "UART1_RXD"),
 123         PINCTRL_PIN(61, "UART1_TXD"),
 124         PINCTRL_PIN(62, "UART1_RTSB"),
 125         PINCTRL_PIN(63, "UART1_CTSB"),
 126         PINCTRL_PIN(64, "I2C0_SDA"),
 127         PINCTRL_PIN(65, "I2C0_SCL"),
 128         PINCTRL_PIN(66, "I2C1_SDA"),
 129         PINCTRL_PIN(67, "I2C1_SCL"),
 130         PINCTRL_PIN(68, "UART2_RXD"),
 131         PINCTRL_PIN(69, "UART2_TXD"),
 132         PINCTRL_PIN(70, "UART2_RTSB"),
 133         PINCTRL_PIN(71, "UART2_CTSB"),
 134         /* GPP_D */
 135         PINCTRL_PIN(72, "SPI1_CSB"),
 136         PINCTRL_PIN(73, "SPI1_CLK"),
 137         PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
 138         PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
 139         PINCTRL_PIN(76, "FLASHTRIG"),
 140         PINCTRL_PIN(77, "ISH_I2C0_SDA"),
 141         PINCTRL_PIN(78, "ISH_I2C0_SCL"),
 142         PINCTRL_PIN(79, "ISH_I2C1_SDA"),
 143         PINCTRL_PIN(80, "ISH_I2C1_SCL"),
 144         PINCTRL_PIN(81, "ISH_SPI_CSB"),
 145         PINCTRL_PIN(82, "ISH_SPI_CLK"),
 146         PINCTRL_PIN(83, "ISH_SPI_MISO"),
 147         PINCTRL_PIN(84, "ISH_SPI_MOSI"),
 148         PINCTRL_PIN(85, "ISH_UART0_RXD"),
 149         PINCTRL_PIN(86, "ISH_UART0_TXD"),
 150         PINCTRL_PIN(87, "ISH_UART0_RTSB"),
 151         PINCTRL_PIN(88, "ISH_UART0_CTSB"),
 152         PINCTRL_PIN(89, "DMIC_CLK_1"),
 153         PINCTRL_PIN(90, "DMIC_DATA_1"),
 154         PINCTRL_PIN(91, "DMIC_CLK_0"),
 155         PINCTRL_PIN(92, "DMIC_DATA_0"),
 156         PINCTRL_PIN(93, "SPI1_IO_2"),
 157         PINCTRL_PIN(94, "SPI1_IO_3"),
 158         PINCTRL_PIN(95, "SSP_MCLK"),
 159         /* GPP_E */
 160         PINCTRL_PIN(96, "SATAXPCIE_0"),
 161         PINCTRL_PIN(97, "SATAXPCIE_1"),
 162         PINCTRL_PIN(98, "SATAXPCIE_2"),
 163         PINCTRL_PIN(99, "CPU_GP_0"),
 164         PINCTRL_PIN(100, "SATA_DEVSLP_0"),
 165         PINCTRL_PIN(101, "SATA_DEVSLP_1"),
 166         PINCTRL_PIN(102, "SATA_DEVSLP_2"),
 167         PINCTRL_PIN(103, "CPU_GP_1"),
 168         PINCTRL_PIN(104, "SATA_LEDB"),
 169         PINCTRL_PIN(105, "USB2_OCB_0"),
 170         PINCTRL_PIN(106, "USB2_OCB_1"),
 171         PINCTRL_PIN(107, "USB2_OCB_2"),
 172         PINCTRL_PIN(108, "USB2_OCB_3"),
 173         PINCTRL_PIN(109, "DDSP_HPD_0"),
 174         PINCTRL_PIN(110, "DDSP_HPD_1"),
 175         PINCTRL_PIN(111, "DDSP_HPD_2"),
 176         PINCTRL_PIN(112, "DDSP_HPD_3"),
 177         PINCTRL_PIN(113, "EDP_HPD"),
 178         PINCTRL_PIN(114, "DDPB_CTRLCLK"),
 179         PINCTRL_PIN(115, "DDPB_CTRLDATA"),
 180         PINCTRL_PIN(116, "DDPC_CTRLCLK"),
 181         PINCTRL_PIN(117, "DDPC_CTRLDATA"),
 182         PINCTRL_PIN(118, "DDPD_CTRLCLK"),
 183         PINCTRL_PIN(119, "DDPD_CTRLDATA"),
 184         /* GPP_F */
 185         PINCTRL_PIN(120, "SSP2_SCLK"),
 186         PINCTRL_PIN(121, "SSP2_SFRM"),
 187         PINCTRL_PIN(122, "SSP2_TXD"),
 188         PINCTRL_PIN(123, "SSP2_RXD"),
 189         PINCTRL_PIN(124, "I2C2_SDA"),
 190         PINCTRL_PIN(125, "I2C2_SCL"),
 191         PINCTRL_PIN(126, "I2C3_SDA"),
 192         PINCTRL_PIN(127, "I2C3_SCL"),
 193         PINCTRL_PIN(128, "I2C4_SDA"),
 194         PINCTRL_PIN(129, "I2C4_SCL"),
 195         PINCTRL_PIN(130, "I2C5_SDA"),
 196         PINCTRL_PIN(131, "I2C5_SCL"),
 197         PINCTRL_PIN(132, "EMMC_CMD"),
 198         PINCTRL_PIN(133, "EMMC_DATA_0"),
 199         PINCTRL_PIN(134, "EMMC_DATA_1"),
 200         PINCTRL_PIN(135, "EMMC_DATA_2"),
 201         PINCTRL_PIN(136, "EMMC_DATA_3"),
 202         PINCTRL_PIN(137, "EMMC_DATA_4"),
 203         PINCTRL_PIN(138, "EMMC_DATA_5"),
 204         PINCTRL_PIN(139, "EMMC_DATA_6"),
 205         PINCTRL_PIN(140, "EMMC_DATA_7"),
 206         PINCTRL_PIN(141, "EMMC_RCLK"),
 207         PINCTRL_PIN(142, "EMMC_CLK"),
 208         PINCTRL_PIN(143, "GPP_F_23"),
 209         /* GPP_G */
 210         PINCTRL_PIN(144, "SD_CMD"),
 211         PINCTRL_PIN(145, "SD_DATA_0"),
 212         PINCTRL_PIN(146, "SD_DATA_1"),
 213         PINCTRL_PIN(147, "SD_DATA_2"),
 214         PINCTRL_PIN(148, "SD_DATA_3"),
 215         PINCTRL_PIN(149, "SD_CDB"),
 216         PINCTRL_PIN(150, "SD_CLK"),
 217         PINCTRL_PIN(151, "SD_WP"),
 218 };
 219
 220 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
 221 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
 222 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
 223 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
 224 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
 225 static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
 226 static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
 227 static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
 228 static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
 229 static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
 230 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
 231 static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
 232 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
 233 static const unsigned sptlp_emmc_pins[] = {
 234         132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
 235 };
 236 static const unsigned sptlp_sd_pins[] = {
 237         144, 145, 146, 147, 148, 149, 150, 151,
 238 };
 239
 240 static const struct intel_pingroup sptlp_groups[] = {
 241         PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
 242         PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
 243         PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
 244         PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
 245         PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
 246         PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
 247         PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
 248         PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
 249         PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
 250         PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
 251         PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
 252         PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
 253         PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
 254         PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
 255         PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
 256 };
 257
 258 static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
 259 static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
 260 static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
 261 static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
 262 static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
 263 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
 264 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
 265 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
 266 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
 267 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
 268 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
 269 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
 270 static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
 271 static const char * const sptlp_sd_groups[] = { "sd_grp" };
 272
 273 static const struct intel_function sptlp_functions[] = {
 274         FUNCTION("spi0", sptlp_spi0_groups),
 275         FUNCTION("spi1", sptlp_spi1_groups),
 276         FUNCTION("uart0", sptlp_uart0_groups),
 277         FUNCTION("uart1", sptlp_uart1_groups),
 278         FUNCTION("uart2", sptlp_uart2_groups),
 279         FUNCTION("i2c0", sptlp_i2c0_groups),
 280         FUNCTION("i2c1", sptlp_i2c1_groups),
 281         FUNCTION("i2c2", sptlp_i2c2_groups),
 282         FUNCTION("i2c3", sptlp_i2c3_groups),
 283         FUNCTION("i2c4", sptlp_i2c4_groups),
 284         FUNCTION("i2c5", sptlp_i2c5_groups),
 285         FUNCTION("ssp2", sptlp_ssp2_groups),
 286         FUNCTION("emmc", sptlp_emmc_groups),
 287         FUNCTION("sd", sptlp_sd_groups),
 288 };
 289
 290 static const struct intel_community sptlp_communities[] = {
 291         SPT_COMMUNITY(0, 0, 47),
 292         SPT_COMMUNITY(1, 48, 119),
 293         SPT_COMMUNITY(2, 120, 151),
 294 };
 295
 296 static const struct intel_pinctrl_soc_data sptlp_soc_data = {
 297         .pins = sptlp_pins,
 298         .npins = ARRAY_SIZE(sptlp_pins),
 299         .groups = sptlp_groups,
 300         .ngroups = ARRAY_SIZE(sptlp_groups),
 301         .functions = sptlp_functions,
 302         .nfunctions = ARRAY_SIZE(sptlp_functions),
 303         .communities = sptlp_communities,
 304         .ncommunities = ARRAY_SIZE(sptlp_communities),
 305 };
 306
 307 /* Sunrisepoint-H */
 308 static const struct pinctrl_pin_desc spth_pins[] = {
 309         /* GPP_A */
 310         PINCTRL_PIN(0, "RCINB"),
 311         PINCTRL_PIN(1, "LAD_0"),
 312         PINCTRL_PIN(2, "LAD_1"),
 313         PINCTRL_PIN(3, "LAD_2"),
 314         PINCTRL_PIN(4, "LAD_3"),
 315         PINCTRL_PIN(5, "LFRAMEB"),
 316         PINCTRL_PIN(6, "SERIQ"),
 317         PINCTRL_PIN(7, "PIRQAB"),
 318         PINCTRL_PIN(8, "CLKRUNB"),
 319         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
 320         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
 321         PINCTRL_PIN(11, "PMEB"),
 322         PINCTRL_PIN(12, "BM_BUSYB"),
 323         PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
 324         PINCTRL_PIN(14, "SUS_STATB"),
 325         PINCTRL_PIN(15, "SUSACKB"),
 326         PINCTRL_PIN(16, "CLKOUT_48"),
 327         PINCTRL_PIN(17, "ISH_GP_7"),
 328         PINCTRL_PIN(18, "ISH_GP_0"),
 329         PINCTRL_PIN(19, "ISH_GP_1"),
 330         PINCTRL_PIN(20, "ISH_GP_2"),
 331         PINCTRL_PIN(21, "ISH_GP_3"),
 332         PINCTRL_PIN(22, "ISH_GP_4"),
 333         PINCTRL_PIN(23, "ISH_GP_5"),
 334         /* GPP_B */
 335         PINCTRL_PIN(24, "CORE_VID_0"),
 336         PINCTRL_PIN(25, "CORE_VID_1"),
 337         PINCTRL_PIN(26, "VRALERTB"),
 338         PINCTRL_PIN(27, "CPU_GP_2"),
 339         PINCTRL_PIN(28, "CPU_GP_3"),
 340         PINCTRL_PIN(29, "SRCCLKREQB_0"),
 341         PINCTRL_PIN(30, "SRCCLKREQB_1"),
 342         PINCTRL_PIN(31, "SRCCLKREQB_2"),
 343         PINCTRL_PIN(32, "SRCCLKREQB_3"),
 344         PINCTRL_PIN(33, "SRCCLKREQB_4"),
 345         PINCTRL_PIN(34, "SRCCLKREQB_5"),
 346         PINCTRL_PIN(35, "EXT_PWR_GATEB"),
 347         PINCTRL_PIN(36, "SLP_S0B"),
 348         PINCTRL_PIN(37, "PLTRSTB"),
 349         PINCTRL_PIN(38, "SPKR"),
 350         PINCTRL_PIN(39, "GSPI0_CSB"),
 351         PINCTRL_PIN(40, "GSPI0_CLK"),
 352         PINCTRL_PIN(41, "GSPI0_MISO"),
 353         PINCTRL_PIN(42, "GSPI0_MOSI"),
 354         PINCTRL_PIN(43, "GSPI1_CSB"),
 355         PINCTRL_PIN(44, "GSPI1_CLK"),
 356         PINCTRL_PIN(45, "GSPI1_MISO"),
 357         PINCTRL_PIN(46, "GSPI1_MOSI"),
 358         PINCTRL_PIN(47, "SML1ALERTB"),
 359         /* GPP_C */
 360         PINCTRL_PIN(48, "SMBCLK"),
 361         PINCTRL_PIN(49, "SMBDATA"),
 362         PINCTRL_PIN(50, "SMBALERTB"),
 363         PINCTRL_PIN(51, "SML0CLK"),
 364         PINCTRL_PIN(52, "SML0DATA"),
 365         PINCTRL_PIN(53, "SML0ALERTB"),
 366         PINCTRL_PIN(54, "SML1CLK"),
 367         PINCTRL_PIN(55, "SML1DATA"),
 368         PINCTRL_PIN(56, "UART0_RXD"),
 369         PINCTRL_PIN(57, "UART0_TXD"),
 370         PINCTRL_PIN(58, "UART0_RTSB"),
 371         PINCTRL_PIN(59, "UART0_CTSB"),
 372         PINCTRL_PIN(60, "UART1_RXD"),
 373         PINCTRL_PIN(61, "UART1_TXD"),
 374         PINCTRL_PIN(62, "UART1_RTSB"),
 375         PINCTRL_PIN(63, "UART1_CTSB"),
 376         PINCTRL_PIN(64, "I2C0_SDA"),
 377         PINCTRL_PIN(65, "I2C0_SCL"),
 378         PINCTRL_PIN(66, "I2C1_SDA"),
 379         PINCTRL_PIN(67, "I2C1_SCL"),
 380         PINCTRL_PIN(68, "UART2_RXD"),
 381         PINCTRL_PIN(69, "UART2_TXD"),
 382         PINCTRL_PIN(70, "UART2_RTSB"),
 383         PINCTRL_PIN(71, "UART2_CTSB"),
 384         /* GPP_D */
 385         PINCTRL_PIN(72, "SPI1_CSB"),
 386         PINCTRL_PIN(73, "SPI1_CLK"),
 387         PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
 388         PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
 389         PINCTRL_PIN(76, "ISH_I2C2_SDA"),
 390         PINCTRL_PIN(77, "SSP0_SFRM"),
 391         PINCTRL_PIN(78, "SSP0_TXD"),
 392         PINCTRL_PIN(79, "SSP0_RXD"),
 393         PINCTRL_PIN(80, "SSP0_SCLK"),
 394         PINCTRL_PIN(81, "ISH_SPI_CSB"),
 395         PINCTRL_PIN(82, "ISH_SPI_CLK"),
 396         PINCTRL_PIN(83, "ISH_SPI_MISO"),
 397         PINCTRL_PIN(84, "ISH_SPI_MOSI"),
 398         PINCTRL_PIN(85, "ISH_UART0_RXD"),
 399         PINCTRL_PIN(86, "ISH_UART0_TXD"),
 400         PINCTRL_PIN(87, "ISH_UART0_RTSB"),
 401         PINCTRL_PIN(88, "ISH_UART0_CTSB"),
 402         PINCTRL_PIN(89, "DMIC_CLK_1"),
 403         PINCTRL_PIN(90, "DMIC_DATA_1"),
 404         PINCTRL_PIN(91, "DMIC_CLK_0"),
 405         PINCTRL_PIN(92, "DMIC_DATA_0"),
 406         PINCTRL_PIN(93, "SPI1_IO_2"),
 407         PINCTRL_PIN(94, "SPI1_IO_3"),
 408         PINCTRL_PIN(95, "ISH_I2C2_SCL"),
 409         /* GPP_E */
 410         PINCTRL_PIN(96, "SATAXPCIE_0"),
 411         PINCTRL_PIN(97, "SATAXPCIE_1"),
 412         PINCTRL_PIN(98, "SATAXPCIE_2"),
 413         PINCTRL_PIN(99, "CPU_GP_0"),
 414         PINCTRL_PIN(100, "SATA_DEVSLP_0"),
 415         PINCTRL_PIN(101, "SATA_DEVSLP_1"),
 416         PINCTRL_PIN(102, "SATA_DEVSLP_2"),
 417         PINCTRL_PIN(103, "CPU_GP_1"),
 418         PINCTRL_PIN(104, "SATA_LEDB"),
 419         PINCTRL_PIN(105, "USB2_OCB_0"),
 420         PINCTRL_PIN(106, "USB2_OCB_1"),
 421         PINCTRL_PIN(107, "USB2_OCB_2"),
 422         PINCTRL_PIN(108, "USB2_OCB_3"),
 423         /* GPP_F */
 424         PINCTRL_PIN(109, "SATAXPCIE_3"),
 425         PINCTRL_PIN(110, "SATAXPCIE_4"),
 426         PINCTRL_PIN(111, "SATAXPCIE_5"),
 427         PINCTRL_PIN(112, "SATAXPCIE_6"),
 428         PINCTRL_PIN(113, "SATAXPCIE_7"),
 429         PINCTRL_PIN(114, "SATA_DEVSLP_3"),
 430         PINCTRL_PIN(115, "SATA_DEVSLP_4"),
 431         PINCTRL_PIN(116, "SATA_DEVSLP_5"),
 432         PINCTRL_PIN(117, "SATA_DEVSLP_6"),
 433         PINCTRL_PIN(118, "SATA_DEVSLP_7"),
 434         PINCTRL_PIN(119, "SATA_SCLOCK"),
 435         PINCTRL_PIN(120, "SATA_SLOAD"),
 436         PINCTRL_PIN(121, "SATA_SDATAOUT1"),
 437         PINCTRL_PIN(122, "SATA_SDATAOUT0"),
 438         PINCTRL_PIN(123, "GPP_F_14"),
 439         PINCTRL_PIN(124, "USB_OCB_4"),
 440         PINCTRL_PIN(125, "USB_OCB_5"),
 441         PINCTRL_PIN(126, "USB_OCB_6"),
 442         PINCTRL_PIN(127, "USB_OCB_7"),
 443         PINCTRL_PIN(128, "L_VDDEN"),
 444         PINCTRL_PIN(129, "L_BKLTEN"),
 445         PINCTRL_PIN(130, "L_BKLTCTL"),
 446         PINCTRL_PIN(131, "GPP_F_22"),
 447         PINCTRL_PIN(132, "GPP_F_23"),
 448         /* GPP_G */
 449         PINCTRL_PIN(133, "FAN_TACH_0"),
 450         PINCTRL_PIN(134, "FAN_TACH_1"),
 451         PINCTRL_PIN(135, "FAN_TACH_2"),
 452         PINCTRL_PIN(136, "FAN_TACH_3"),
 453         PINCTRL_PIN(137, "FAN_TACH_4"),
 454         PINCTRL_PIN(138, "FAN_TACH_5"),
 455         PINCTRL_PIN(139, "FAN_TACH_6"),
 456         PINCTRL_PIN(140, "FAN_TACH_7"),
 457         PINCTRL_PIN(141, "FAN_PWM_0"),
 458         PINCTRL_PIN(142, "FAN_PWM_1"),
 459         PINCTRL_PIN(143, "FAN_PWM_2"),
 460         PINCTRL_PIN(144, "FAN_PWM_3"),
 461         PINCTRL_PIN(145, "GSXDOUT"),
 462         PINCTRL_PIN(146, "GSXSLOAD"),
 463         PINCTRL_PIN(147, "GSXDIN"),
 464         PINCTRL_PIN(148, "GSXRESETB"),
 465         PINCTRL_PIN(149, "GSXCLK"),
 466         PINCTRL_PIN(150, "ADR_COMPLETE"),
 467         PINCTRL_PIN(151, "NMIB"),
 468         PINCTRL_PIN(152, "SMIB"),
 469         PINCTRL_PIN(153, "GPP_G_20"),
 470         PINCTRL_PIN(154, "GPP_G_21"),
 471         PINCTRL_PIN(155, "GPP_G_22"),
 472         PINCTRL_PIN(156, "GPP_G_23"),
 473         /* GPP_H */
 474         PINCTRL_PIN(157, "SRCCLKREQB_6"),
 475         PINCTRL_PIN(158, "SRCCLKREQB_7"),
 476         PINCTRL_PIN(159, "SRCCLKREQB_8"),
 477         PINCTRL_PIN(160, "SRCCLKREQB_9"),
 478         PINCTRL_PIN(161, "SRCCLKREQB_10"),
 479         PINCTRL_PIN(162, "SRCCLKREQB_11"),
 480         PINCTRL_PIN(163, "SRCCLKREQB_12"),
 481         PINCTRL_PIN(164, "SRCCLKREQB_13"),
 482         PINCTRL_PIN(165, "SRCCLKREQB_14"),
 483         PINCTRL_PIN(166, "SRCCLKREQB_15"),
 484         PINCTRL_PIN(167, "SML2CLK"),
 485         PINCTRL_PIN(168, "SML2DATA"),
 486         PINCTRL_PIN(169, "SML2ALERTB"),
 487         PINCTRL_PIN(170, "SML3CLK"),
 488         PINCTRL_PIN(171, "SML3DATA"),
 489         PINCTRL_PIN(172, "SML3ALERTB"),
 490         PINCTRL_PIN(173, "SML4CLK"),
 491         PINCTRL_PIN(174, "SML4DATA"),
 492         PINCTRL_PIN(175, "SML4ALERTB"),
 493         PINCTRL_PIN(176, "ISH_I2C0_SDA"),
 494         PINCTRL_PIN(177, "ISH_I2C0_SCL"),
 495         PINCTRL_PIN(178, "ISH_I2C1_SDA"),
 496         PINCTRL_PIN(179, "ISH_I2C1_SCL"),
 497         PINCTRL_PIN(180, "GPP_H_23"),
 498         /* GPP_I */
 499         PINCTRL_PIN(181, "DDSP_HDP_0"),
 500         PINCTRL_PIN(182, "DDSP_HDP_1"),
 501         PINCTRL_PIN(183, "DDSP_HDP_2"),
 502         PINCTRL_PIN(184, "DDSP_HDP_3"),
 503         PINCTRL_PIN(185, "EDP_HPD"),
 504         PINCTRL_PIN(186, "DDPB_CTRLCLK"),
 505         PINCTRL_PIN(187, "DDPB_CTRLDATA"),
 506         PINCTRL_PIN(188, "DDPC_CTRLCLK"),
 507         PINCTRL_PIN(189, "DDPC_CTRLDATA"),
 508         PINCTRL_PIN(190, "DDPD_CTRLCLK"),
 509         PINCTRL_PIN(191, "DDPD_CTRLDATA"),
 510 };
 511
 512 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
 513 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
 514 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
 515 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
 516 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
 517 static const unsigned spth_i2c0_pins[] = { 64, 65 };
 518 static const unsigned spth_i2c1_pins[] = { 66, 67 };
 519 static const unsigned spth_i2c2_pins[] = { 76, 95 };
 520
 521 static const struct intel_pingroup spth_groups[] = {
 522         PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
 523         PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
 524         PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
 525         PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
 526         PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
 527         PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
 528         PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
 529         PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
 530 };
 531
 532 static const char * const spth_spi0_groups[] = { "spi0_grp" };
 533 static const char * const spth_spi1_groups[] = { "spi0_grp" };
 534 static const char * const spth_uart0_groups[] = { "uart0_grp" };
 535 static const char * const spth_uart1_groups[] = { "uart1_grp" };
 536 static const char * const spth_uart2_groups[] = { "uart2_grp" };
 537 static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
 538 static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
 539 static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
 540
 541 static const struct intel_function spth_functions[] = {
 542         FUNCTION("spi0", spth_spi0_groups),
 543         FUNCTION("spi1", spth_spi1_groups),
 544         FUNCTION("uart0", spth_uart0_groups),
 545         FUNCTION("uart1", spth_uart1_groups),
 546         FUNCTION("uart2", spth_uart2_groups),
 547         FUNCTION("i2c0", spth_i2c0_groups),
 548         FUNCTION("i2c1", spth_i2c1_groups),
 549         FUNCTION("i2c2", spth_i2c2_groups),
 550 };
 551
 552 static const struct intel_padgroup spth_community0_gpps[] = {
 553         SPTH_GPP(0, 0, 23, 0),          /* GPP_A */
 554         SPTH_GPP(1, 24, 47, 24),        /* GPP_B */
 555 };
 556
 557 static const struct intel_padgroup spth_community1_gpps[] = {
 558         SPTH_GPP(0, 48, 71, 48),        /* GPP_C */
 559         SPTH_GPP(1, 72, 95, 72),        /* GPP_D */
 560         SPTH_GPP(2, 96, 108, 96),       /* GPP_E */
 561         SPTH_GPP(3, 109, 132, 120),     /* GPP_F */
 562         SPTH_GPP(4, 133, 156, 144),     /* GPP_G */
 563         SPTH_GPP(5, 157, 180, 168),     /* GPP_H */
 564 };
 565
 566 static const struct intel_padgroup spth_community3_gpps[] = {
 567         SPTH_GPP(0, 181, 191, 192),     /* GPP_I */
 568 };
 569
 570 static const struct intel_community spth_communities[] = {
 571         SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps),
 572         SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps),
 573         SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps),
 574 };
 575
 576 static const struct intel_pinctrl_soc_data spth_soc_data = {
 577         .pins = spth_pins,
 578         .npins = ARRAY_SIZE(spth_pins),
 579         .groups = spth_groups,
 580         .ngroups = ARRAY_SIZE(spth_groups),
 581         .functions = spth_functions,
 582         .nfunctions = ARRAY_SIZE(spth_functions),
 583         .communities = spth_communities,
 584         .ncommunities = ARRAY_SIZE(spth_communities),
 585 };
 586
 587 static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
 588         { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
 589         { "INT345D", (kernel_ulong_t)&spth_soc_data },
 590         { }
 591 };
 592 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
 593
 594 static int spt_pinctrl_probe(struct platform_device *pdev)
 595 {
 596         const struct intel_pinctrl_soc_data *soc_data;
 597         const struct acpi_device_id *id;
 598
 599         id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
 600         if (!id || !id->driver_data)
 601                 return -ENODEV;
 602
 603         soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
 604         return intel_pinctrl_probe(pdev, soc_data);
 605 }
 606
 607 static const struct dev_pm_ops spt_pinctrl_pm_ops = {
 608         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
 609                                      intel_pinctrl_resume)
 610 };
 611
 612 static struct platform_driver spt_pinctrl_driver = {
 613         .probe = spt_pinctrl_probe,
 614         .driver = {
 615                 .name = "sunrisepoint-pinctrl",
 616                 .acpi_match_table = spt_pinctrl_acpi_match,
 617                 .pm = &spt_pinctrl_pm_ops,
 618         },
 619 };
 620
 621 static int __init spt_pinctrl_init(void)
 622 {
 623         return platform_driver_register(&spt_pinctrl_driver);
 624 }
 625 subsys_initcall(spt_pinctrl_init);
 626
 627 static void __exit spt_pinctrl_exit(void)
 628 {
 629         platform_driver_unregister(&spt_pinctrl_driver);
 630 }
 631 module_exit(spt_pinctrl_exit);
 632
 633 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
 634 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 635 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
 636 MODULE_LICENSE("GPL v2");