drivers/pinctrl/pinctrl-rza1.c

   1 /*
   2  * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
   3  *
   4  * Copyright (C) 2017 Jacopo Mondi
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 /*
  12  * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
  13  * family.
  14  * This includes SoCs which are sub- or super- sets of this particular line,
  15  * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/init.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/pinconf-generic.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/slab.h>
  31
  32 #include "core.h"
  33 #include "devicetree.h"
  34 #include "pinconf.h"
  35 #include "pinmux.h"
  36
  37 #define DRIVER_NAME                     "pinctrl-rza1"
  38
  39 #define RZA1_P_REG                      0x0000
  40 #define RZA1_PPR_REG                    0x0200
  41 #define RZA1_PM_REG                     0x0300
  42 #define RZA1_PMC_REG                    0x0400
  43 #define RZA1_PFC_REG                    0x0500
  44 #define RZA1_PFCE_REG                   0x0600
  45 #define RZA1_PFCEA_REG                  0x0a00
  46 #define RZA1_PIBC_REG                   0x4000
  47 #define RZA1_PBDC_REG                   0x4100
  48 #define RZA1_PIPC_REG                   0x4200
  49
  50 #define RZA1_ADDR(mem, reg, port)       ((mem) + (reg) + ((port) * 4))
  51
  52 #define RZA1_NPORTS                     12
  53 #define RZA1_PINS_PER_PORT              16
  54 #define RZA1_NPINS                      (RZA1_PINS_PER_PORT * RZA1_NPORTS)
  55 #define RZA1_PIN_ID_TO_PORT(id)         ((id) / RZA1_PINS_PER_PORT)
  56 #define RZA1_PIN_ID_TO_PIN(id)          ((id) % RZA1_PINS_PER_PORT)
  57
  58 /*
  59  * Use 16 lower bits [15:0] for pin identifier
  60  * Use 16 higher bits [31:16] for pin mux function
  61  */
  62 #define MUX_PIN_ID_MASK                 GENMASK(15, 0)
  63 #define MUX_FUNC_MASK                   GENMASK(31, 16)
  64
  65 #define MUX_FUNC_OFFS                   16
  66 #define MUX_FUNC(pinconf)               \
  67         ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  68 #define MUX_FUNC_PFC_MASK               BIT(0)
  69 #define MUX_FUNC_PFCE_MASK              BIT(1)
  70 #define MUX_FUNC_PFCEA_MASK             BIT(2)
  71
  72 /* Pin mux flags */
  73 #define MUX_FLAGS_BIDIR                 BIT(0)
  74 #define MUX_FLAGS_SWIO_INPUT            BIT(1)
  75 #define MUX_FLAGS_SWIO_OUTPUT           BIT(2)
  76
  77 /* ----------------------------------------------------------------------------
  78  * RZ/A1 pinmux flags
  79  */
  80
  81 /**
  82  * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
  83  */
  84 struct rza1_bidir_pin {
  85         u8 pin: 4;
  86         u8 func: 4;
  87 };
  88
  89 /**
  90  * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
  91  *                    Each struct rza1_bidir_entry describes a port.
  92  */
  93 struct rza1_bidir_entry {
  94         const unsigned int npins;
  95         const struct rza1_bidir_pin *pins;
  96 };
  97
  98 /**
  99  * rza1_swio_pin - describe a single pin that needs bidir flag applied.
 100  */
 101 struct rza1_swio_pin {
 102         u16 pin: 4;
 103         u16 port: 4;
 104         u16 func: 4;
 105         u16 input: 1;
 106 };
 107
 108 /**
 109  * rza1_swio_entry - describe a list of pins that needs swio flag applied
 110  */
 111 struct rza1_swio_entry {
 112         const unsigned int npins;
 113         const struct rza1_swio_pin *pins;
 114 };
 115
 116 /**
 117  * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
 118  */
 119 struct rza1_pinmux_conf {
 120         const struct rza1_bidir_entry *bidir_entries;
 121         const struct rza1_swio_entry *swio_entries;
 122 };
 123
 124 /* ----------------------------------------------------------------------------
 125  * RZ/A1H (r7s72100) pinmux flags
 126  */
 127
 128 static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
 129         { .pin = 0, .func = 1 },
 130         { .pin = 1, .func = 1 },
 131         { .pin = 2, .func = 1 },
 132         { .pin = 3, .func = 1 },
 133         { .pin = 4, .func = 1 },
 134         { .pin = 5, .func = 1 },
 135         { .pin = 6, .func = 1 },
 136         { .pin = 7, .func = 1 },
 137 };
 138
 139 static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
 140         { .pin = 0, .func = 1 },
 141         { .pin = 1, .func = 1 },
 142         { .pin = 2, .func = 1 },
 143         { .pin = 3, .func = 1 },
 144         { .pin = 4, .func = 1 },
 145         { .pin = 0, .func = 4 },
 146         { .pin = 1, .func = 4 },
 147         { .pin = 2, .func = 4 },
 148         { .pin = 3, .func = 4 },
 149         { .pin = 5, .func = 1 },
 150         { .pin = 6, .func = 1 },
 151         { .pin = 7, .func = 1 },
 152         { .pin = 8, .func = 1 },
 153         { .pin = 9, .func = 1 },
 154         { .pin = 10, .func = 1 },
 155         { .pin = 11, .func = 1 },
 156         { .pin = 12, .func = 1 },
 157         { .pin = 13, .func = 1 },
 158         { .pin = 14, .func = 1 },
 159         { .pin = 15, .func = 1 },
 160         { .pin = 12, .func = 4 },
 161         { .pin = 13, .func = 4 },
 162         { .pin = 14, .func = 4 },
 163         { .pin = 15, .func = 4 },
 164 };
 165
 166 static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
 167         { .pin = 3, .func = 2 },
 168         { .pin = 10, .func = 7 },
 169         { .pin = 11, .func = 7 },
 170         { .pin = 13, .func = 7 },
 171         { .pin = 14, .func = 7 },
 172         { .pin = 15, .func = 7 },
 173         { .pin = 10, .func = 8 },
 174         { .pin = 11, .func = 8 },
 175         { .pin = 13, .func = 8 },
 176         { .pin = 14, .func = 8 },
 177         { .pin = 15, .func = 8 },
 178 };
 179
 180 static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
 181         { .pin = 0, .func = 8 },
 182         { .pin = 1, .func = 8 },
 183         { .pin = 2, .func = 8 },
 184         { .pin = 3, .func = 8 },
 185         { .pin = 10, .func = 3 },
 186         { .pin = 11, .func = 3 },
 187         { .pin = 13, .func = 3 },
 188         { .pin = 14, .func = 3 },
 189         { .pin = 15, .func = 3 },
 190         { .pin = 10, .func = 4 },
 191         { .pin = 11, .func = 4 },
 192         { .pin = 13, .func = 4 },
 193         { .pin = 14, .func = 4 },
 194         { .pin = 15, .func = 4 },
 195         { .pin = 12, .func = 5 },
 196         { .pin = 13, .func = 5 },
 197         { .pin = 14, .func = 5 },
 198         { .pin = 15, .func = 5 },
 199 };
 200
 201 static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
 202         { .pin = 0, .func = 1 },
 203         { .pin = 1, .func = 1 },
 204         { .pin = 2, .func = 1 },
 205         { .pin = 3, .func = 1 },
 206         { .pin = 4, .func = 1 },
 207         { .pin = 5, .func = 1 },
 208         { .pin = 6, .func = 1 },
 209         { .pin = 7, .func = 1 },
 210         { .pin = 8, .func = 1 },
 211         { .pin = 9, .func = 1 },
 212         { .pin = 10, .func = 1 },
 213         { .pin = 11, .func = 1 },
 214         { .pin = 12, .func = 1 },
 215         { .pin = 13, .func = 1 },
 216         { .pin = 14, .func = 1 },
 217         { .pin = 15, .func = 1 },
 218 };
 219
 220 static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
 221         { .pin = 13, .func = 3 },
 222 };
 223
 224 static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
 225         { .pin = 8, .func = 3 },
 226         { .pin = 9, .func = 3 },
 227         { .pin = 10, .func = 3 },
 228         { .pin = 11, .func = 3 },
 229         { .pin = 14, .func = 2 },
 230         { .pin = 15, .func = 2 },
 231         { .pin = 14, .func = 3 },
 232         { .pin = 15, .func = 3 },
 233 };
 234
 235 static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
 236         { .pin = 0, .func = 2 },
 237         { .pin = 1, .func = 2 },
 238         { .pin = 4, .func = 2 },
 239         { .pin = 5, .func = 2 },
 240         { .pin = 6, .func = 2 },
 241         { .pin = 7, .func = 2 },
 242 };
 243
 244 static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
 245         { .pin = 6, .func = 2 },
 246         { .pin = 7, .func = 2 },
 247         { .pin = 9, .func = 2 },
 248         { .pin = 6, .func = 4 },
 249         { .pin = 7, .func = 4 },
 250         { .pin = 9, .func = 4 },
 251         { .pin = 10, .func = 2 },
 252         { .pin = 11, .func = 2 },
 253         { .pin = 10, .func = 4 },
 254         { .pin = 11, .func = 4 },
 255         { .pin = 12, .func = 4 },
 256         { .pin = 13, .func = 4 },
 257         { .pin = 14, .func = 4 },
 258         { .pin = 15, .func = 4 },
 259 };
 260
 261 static const struct rza1_swio_pin rza1h_swio_pins[] = {
 262         { .port = 2, .pin = 7, .func = 4, .input = 0 },
 263         { .port = 2, .pin = 11, .func = 4, .input = 0 },
 264         { .port = 3, .pin = 7, .func = 3, .input = 0 },
 265         { .port = 3, .pin = 7, .func = 8, .input = 0 },
 266         { .port = 4, .pin = 7, .func = 5, .input = 0 },
 267         { .port = 4, .pin = 7, .func = 11, .input = 0 },
 268         { .port = 4, .pin = 15, .func = 6, .input = 0 },
 269         { .port = 5, .pin = 0, .func = 1, .input = 1 },
 270         { .port = 5, .pin = 1, .func = 1, .input = 1 },
 271         { .port = 5, .pin = 2, .func = 1, .input = 1 },
 272         { .port = 5, .pin = 3, .func = 1, .input = 1 },
 273         { .port = 5, .pin = 4, .func = 1, .input = 1 },
 274         { .port = 5, .pin = 5, .func = 1, .input = 1 },
 275         { .port = 5, .pin = 6, .func = 1, .input = 1 },
 276         { .port = 5, .pin = 7, .func = 1, .input = 1 },
 277         { .port = 7, .pin = 4, .func = 6, .input = 0 },
 278         { .port = 7, .pin = 11, .func = 2, .input = 0 },
 279         { .port = 8, .pin = 10, .func = 8, .input = 0 },
 280         { .port = 10, .pin = 15, .func = 2, .input = 0 },
 281 };
 282
 283 static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
 284         [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
 285         [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
 286         [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
 287         [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
 288         [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
 289         [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
 290         [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
 291         [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
 292         [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
 293 };
 294
 295 static const struct rza1_swio_entry rza1h_swio_entries[] = {
 296         [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
 297 };
 298
 299 /* RZ/A1H (r7s72100x) pinmux flags table */
 300 static const struct rza1_pinmux_conf rza1h_pmx_conf = {
 301         .bidir_entries  = rza1h_bidir_entries,
 302         .swio_entries   = rza1h_swio_entries,
 303 };
 304
 305 /* ----------------------------------------------------------------------------
 306  * RZ/A1L (r7s72102) pinmux flags
 307  */
 308
 309 static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
 310         { .pin = 0, .func = 1 },
 311         { .pin = 1, .func = 1 },
 312         { .pin = 2, .func = 1 },
 313         { .pin = 3, .func = 1 },
 314         { .pin = 4, .func = 1 },
 315         { .pin = 5, .func = 1 },
 316         { .pin = 6, .func = 1 },
 317         { .pin = 7, .func = 1 },
 318 };
 319
 320 static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
 321         { .pin = 0, .func = 2 },
 322         { .pin = 1, .func = 2 },
 323         { .pin = 2, .func = 2 },
 324         { .pin = 4, .func = 2 },
 325         { .pin = 5, .func = 2 },
 326         { .pin = 10, .func = 2 },
 327         { .pin = 11, .func = 2 },
 328         { .pin = 12, .func = 2 },
 329         { .pin = 13, .func = 2 },
 330 };
 331
 332 static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
 333         { .pin = 1, .func = 4 },
 334         { .pin = 2, .func = 2 },
 335         { .pin = 3, .func = 2 },
 336         { .pin = 6, .func = 2 },
 337         { .pin = 7, .func = 2 },
 338 };
 339
 340 static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
 341         { .pin = 0, .func = 1 },
 342         { .pin = 1, .func = 1 },
 343         { .pin = 2, .func = 1 },
 344         { .pin = 3, .func = 1 },
 345         { .pin = 4, .func = 1 },
 346         { .pin = 5, .func = 1 },
 347         { .pin = 6, .func = 1 },
 348         { .pin = 7, .func = 1 },
 349         { .pin = 8, .func = 1 },
 350         { .pin = 9, .func = 1 },
 351         { .pin = 10, .func = 1 },
 352         { .pin = 11, .func = 1 },
 353         { .pin = 12, .func = 1 },
 354         { .pin = 13, .func = 1 },
 355         { .pin = 14, .func = 1 },
 356         { .pin = 15, .func = 1 },
 357         { .pin = 0, .func = 2 },
 358         { .pin = 1, .func = 2 },
 359         { .pin = 2, .func = 2 },
 360         { .pin = 3, .func = 2 },
 361 };
 362
 363 static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
 364         { .pin = 0, .func = 1 },
 365         { .pin = 1, .func = 1 },
 366         { .pin = 2, .func = 1 },
 367         { .pin = 3, .func = 1 },
 368         { .pin = 4, .func = 1 },
 369         { .pin = 5, .func = 1 },
 370         { .pin = 6, .func = 1 },
 371         { .pin = 7, .func = 1 },
 372         { .pin = 8, .func = 1 },
 373         { .pin = 9, .func = 1 },
 374         { .pin = 10, .func = 1 },
 375         { .pin = 11, .func = 1 },
 376         { .pin = 12, .func = 1 },
 377         { .pin = 13, .func = 1 },
 378         { .pin = 14, .func = 1 },
 379         { .pin = 15, .func = 1 },
 380 };
 381
 382 static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
 383         { .pin = 2, .func = 2 },
 384         { .pin = 3, .func = 2 },
 385         { .pin = 5, .func = 2 },
 386         { .pin = 6, .func = 2 },
 387         { .pin = 7, .func = 2 },
 388         { .pin = 2, .func = 3 },
 389         { .pin = 3, .func = 3 },
 390         { .pin = 5, .func = 3 },
 391         { .pin = 6, .func = 3 },
 392         { .pin = 7, .func = 3 },
 393 };
 394
 395 static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
 396         { .pin = 1, .func = 2 },
 397         { .pin = 0, .func = 3 },
 398         { .pin = 1, .func = 3 },
 399         { .pin = 3, .func = 3 },
 400         { .pin = 4, .func = 3 },
 401         { .pin = 5, .func = 3 },
 402 };
 403
 404 static const struct rza1_swio_pin rza1l_swio_pins[] = {
 405         { .port = 2, .pin = 8, .func = 2, .input = 0 },
 406         { .port = 5, .pin = 6, .func = 3, .input = 0 },
 407         { .port = 6, .pin = 6, .func = 3, .input = 0 },
 408         { .port = 6, .pin = 10, .func = 3, .input = 0 },
 409         { .port = 7, .pin = 10, .func = 2, .input = 0 },
 410         { .port = 8, .pin = 2, .func = 3, .input = 0 },
 411 };
 412
 413 static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
 414         [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
 415         [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
 416         [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
 417         [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
 418         [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
 419         [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
 420         [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
 421 };
 422
 423 static const struct rza1_swio_entry rza1l_swio_entries[] = {
 424         [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
 425 };
 426
 427 /* RZ/A1L (r7s72102x) pinmux flags table */
 428 static const struct rza1_pinmux_conf rza1l_pmx_conf = {
 429         .bidir_entries  = rza1l_bidir_entries,
 430         .swio_entries   = rza1l_swio_entries,
 431 };
 432
 433 /* ----------------------------------------------------------------------------
 434  * RZ/A1 types
 435  */
 436 /**
 437  * rza1_mux_conf - describes a pin multiplexing operation
 438  *
 439  * @id: the pin identifier from 0 to RZA1_NPINS
 440  * @port: the port where pin sits on
 441  * @pin: pin id
 442  * @mux_func: alternate function id number
 443  * @mux_flags: alternate function flags
 444  * @value: output value to set the pin to
 445  */
 446 struct rza1_mux_conf {
 447         u16 id;
 448         u8 port;
 449         u8 pin;
 450         u8 mux_func;
 451         u8 mux_flags;
 452         u8 value;
 453 };
 454
 455 /**
 456  * rza1_port - describes a pin port
 457  *
 458  * This is mostly useful to lock register writes per-bank and not globally.
 459  *
 460  * @lock: protect access to HW registers
 461  * @id: port number
 462  * @base: logical address base
 463  * @pins: pins sitting on this port
 464  */
 465 struct rza1_port {
 466         spinlock_t lock;
 467         unsigned int id;
 468         void __iomem *base;
 469         struct pinctrl_pin_desc *pins;
 470 };
 471
 472 /**
 473  * rza1_pinctrl - RZ pincontroller device
 474  *
 475  * @dev: parent device structure
 476  * @mutex: protect [pinctrl|pinmux]_generic functions
 477  * @base: logical address base
 478  * @nports: number of pin controller ports
 479  * @ports: pin controller banks
 480  * @pins: pin array for pinctrl core
 481  * @desc: pincontroller desc for pinctrl core
 482  * @pctl: pinctrl device
 483  * @data: device specific data
 484  */
 485 struct rza1_pinctrl {
 486         struct device *dev;
 487
 488         struct mutex mutex;
 489
 490         void __iomem *base;
 491
 492         unsigned int nport;
 493         struct rza1_port *ports;
 494
 495         struct pinctrl_pin_desc *pins;
 496         struct pinctrl_desc desc;
 497         struct pinctrl_dev *pctl;
 498
 499         const void *data;
 500 };
 501
 502 /* ----------------------------------------------------------------------------
 503  * RZ/A1 pinmux flags
 504  */
 505 static inline bool rza1_pinmux_get_bidir(unsigned int port,
 506                                          unsigned int pin,
 507                                          unsigned int func,
 508                                          const struct rza1_bidir_entry *table)
 509 {
 510         const struct rza1_bidir_entry *entry = &table[port];
 511         const struct rza1_bidir_pin *bidir_pin;
 512         unsigned int i;
 513
 514         for (i = 0; i < entry->npins; ++i) {
 515                 bidir_pin = &entry->pins[i];
 516                 if (bidir_pin->pin == pin && bidir_pin->func == func)
 517                         return true;
 518         }
 519
 520         return false;
 521 }
 522
 523 static inline int rza1_pinmux_get_swio(unsigned int port,
 524                                        unsigned int pin,
 525                                        unsigned int func,
 526                                        const struct rza1_swio_entry *table)
 527 {
 528         const struct rza1_swio_pin *swio_pin;
 529         unsigned int i;
 530
 531
 532         for (i = 0; i < table->npins; ++i) {
 533                 swio_pin = &table->pins[i];
 534                 if (swio_pin->port == port && swio_pin->pin == pin &&
 535                     swio_pin->func == func)
 536                         return swio_pin->input;
 537         }
 538
 539         return -ENOENT;
 540 }
 541
 542 /**
 543  * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
 544  */
 545 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
 546                                           unsigned int func,
 547                                           struct rza1_pinctrl *rza1_pctl)
 548
 549 {
 550         const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
 551         const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
 552         const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
 553         unsigned int pmx_flags = 0;
 554         int ret;
 555
 556         if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
 557                 pmx_flags |= MUX_FLAGS_BIDIR;
 558
 559         ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
 560         if (ret == 0)
 561                 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
 562         else if (ret > 0)
 563                 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
 564
 565         return pmx_flags;
 566 }
 567
 568 /* ----------------------------------------------------------------------------
 569  * RZ/A1 SoC operations
 570  */
 571
 572 /**
 573  * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
 574  *                  registers
 575  */
 576 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
 577                                 unsigned int bit, bool set)
 578 {
 579         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 580         u16 val = ioread16(mem);
 581
 582         if (set)
 583                 val |= BIT(bit);
 584         else
 585                 val &= ~BIT(bit);
 586
 587         iowrite16(val, mem);
 588 }
 589
 590 static inline unsigned int rza1_get_bit(struct rza1_port *port,
 591                                         unsigned int reg, unsigned int bit)
 592 {
 593         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 594
 595         return ioread16(mem) & BIT(bit);
 596 }
 597
 598 /**
 599  * rza1_pin_reset() - reset a pin to default initial state
 600  *
 601  * Reset pin state disabling input buffer and bi-directional control,
 602  * and configure it as input port.
 603  * Note that pin is now configured with direction as input but with input
 604  * buffer disabled. This implies the pin value cannot be read in this state.
 605  *
 606  * @port: port where pin sits on
 607  * @pin: pin offset
 608  */
 609 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
 610 {
 611         unsigned long irqflags;
 612
 613         spin_lock_irqsave(&port->lock, irqflags);
 614         rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
 615         rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 616
 617         rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 618         rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
 619         rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
 620         spin_unlock_irqrestore(&port->lock, irqflags);
 621 }
 622
 623 static inline int rza1_pin_get_direction(struct rza1_port *port,
 624                                          unsigned int pin)
 625 {
 626         unsigned long irqflags;
 627         int input;
 628
 629         spin_lock_irqsave(&port->lock, irqflags);
 630         input = rza1_get_bit(port, RZA1_PM_REG, pin);
 631         spin_unlock_irqrestore(&port->lock, irqflags);
 632
 633         return !!input;
 634 }
 635
 636 /**
 637  * rza1_pin_set_direction() - set I/O direction on a pin in port mode
 638  *
 639  * When running in output port mode keep PBDC enabled to allow reading the
 640  * pin value from PPR.
 641  *
 642  * @port: port where pin sits on
 643  * @pin: pin offset
 644  * @input: input enable/disable flag
 645  */
 646 static inline void rza1_pin_set_direction(struct rza1_port *port,
 647                                           unsigned int pin, bool input)
 648 {
 649         unsigned long irqflags;
 650
 651         spin_lock_irqsave(&port->lock, irqflags);
 652
 653         rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
 654         if (input) {
 655                 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 656                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 657         } else {
 658                 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
 659                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 660         }
 661
 662         spin_unlock_irqrestore(&port->lock, irqflags);
 663 }
 664
 665 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
 666                                 unsigned int value)
 667 {
 668         unsigned long irqflags;
 669
 670         spin_lock_irqsave(&port->lock, irqflags);
 671         rza1_set_bit(port, RZA1_P_REG, pin, !!value);
 672         spin_unlock_irqrestore(&port->lock, irqflags);
 673 }
 674
 675 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
 676 {
 677         unsigned long irqflags;
 678         int val;
 679
 680         spin_lock_irqsave(&port->lock, irqflags);
 681         val = rza1_get_bit(port, RZA1_PPR_REG, pin);
 682         spin_unlock_irqrestore(&port->lock, irqflags);
 683
 684         return val;
 685 }
 686
 687 /**
 688  * rza1_pin_mux_single() - configure pin multiplexing on a single pin
 689  *
 690  * @pinctrl: RZ/A1 pin controller device
 691  * @mux_conf: pin multiplexing descriptor
 692  */
 693 static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
 694                                struct rza1_mux_conf *mux_conf)
 695 {
 696         struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
 697         unsigned int pin = mux_conf->pin;
 698         u8 mux_func = mux_conf->mux_func;
 699         u8 mux_flags = mux_conf->mux_flags;
 700         u8 mux_flags_from_table;
 701
 702         rza1_pin_reset(port, pin);
 703
 704         /* SWIO pinmux flags coming from DT are high precedence */
 705         mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
 706                                                      rza1_pctl);
 707         if (mux_flags)
 708                 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
 709         else
 710                 mux_flags = mux_flags_from_table;
 711
 712         if (mux_flags & MUX_FLAGS_BIDIR)
 713                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 714
 715         /*
 716          * Enable alternate function mode and select it.
 717          *
 718          * Be careful here: the pin mux sub-nodes in device tree
 719          * enumerate alternate functions from 1 to 8;
 720          * subtract 1 before using macros to match registers configuration
 721          * which expects numbers from 0 to 7 instead.
 722          *
 723          * ----------------------------------------------------
 724          * Alternate mode selection table:
 725          *
 726          * PMC  PFC     PFCE    PFCAE   (mux_func - 1)
 727          * 1    0       0       0       0
 728          * 1    1       0       0       1
 729          * 1    0       1       0       2
 730          * 1    1       1       0       3
 731          * 1    0       0       1       4
 732          * 1    1       0       1       5
 733          * 1    0       1       1       6
 734          * 1    1       1       1       7
 735          * ----------------------------------------------------
 736          */
 737         mux_func -= 1;
 738         rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
 739         rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
 740         rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
 741
 742         /*
 743          * All alternate functions except a few need PIPCn = 1.
 744          * If PIPCn has to stay disabled (SW IO mode), configure PMn according
 745          * to I/O direction specified by pin configuration -after- PMC has been
 746          * set to one.
 747          */
 748         if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
 749                 rza1_set_bit(port, RZA1_PM_REG, pin,
 750                              mux_flags & MUX_FLAGS_SWIO_INPUT);
 751         else
 752                 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
 753
 754         rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
 755
 756         return 0;
 757 }
 758
 759 /* ----------------------------------------------------------------------------
 760  * gpio operations
 761  */
 762
 763 /**
 764  * rza1_gpio_request() - configure pin in port mode
 765  *
 766  * Configure a pin as gpio (port mode).
 767  * After reset, the pin is in input mode with input buffer disabled.
 768  * To use the pin as input or output, set_direction shall be called first
 769  *
 770  * @chip: gpio chip where the gpio sits on
 771  * @gpio: gpio offset
 772  */
 773 static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
 774 {
 775         struct rza1_port *port = gpiochip_get_data(chip);
 776
 777         rza1_pin_reset(port, gpio);
 778
 779         return 0;
 780 }
 781
 782 /**
 783  * rza1_gpio_disable_free() - reset a pin
 784  *
 785  * Surprisingly, disable_free a gpio, is equivalent to request it.
 786  * Reset pin to port mode, with input buffer disabled. This overwrites all
 787  * port direction settings applied with set_direction
 788  *
 789  * @chip: gpio chip where the gpio sits on
 790  * @gpio: gpio offset
 791  */
 792 static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
 793 {
 794         struct rza1_port *port = gpiochip_get_data(chip);
 795
 796         rza1_pin_reset(port, gpio);
 797 }
 798
 799 static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 800 {
 801         struct rza1_port *port = gpiochip_get_data(chip);
 802
 803         return rza1_pin_get_direction(port, gpio);
 804 }
 805
 806 static int rza1_gpio_direction_input(struct gpio_chip *chip,
 807                                      unsigned int gpio)
 808 {
 809         struct rza1_port *port = gpiochip_get_data(chip);
 810
 811         rza1_pin_set_direction(port, gpio, true);
 812
 813         return 0;
 814 }
 815
 816 static int rza1_gpio_direction_output(struct gpio_chip *chip,
 817                                       unsigned int gpio,
 818                                       int value)
 819 {
 820         struct rza1_port *port = gpiochip_get_data(chip);
 821
 822         /* Set value before driving pin direction */
 823         rza1_pin_set(port, gpio, value);
 824         rza1_pin_set_direction(port, gpio, false);
 825
 826         return 0;
 827 }
 828
 829 /**
 830  * rza1_gpio_get() - read a gpio pin value
 831  *
 832  * Read gpio pin value through PPR register.
 833  * Requires bi-directional mode to work when reading the value of a pin
 834  * in output mode
 835  *
 836  * @chip: gpio chip where the gpio sits on
 837  * @gpio: gpio offset
 838  */
 839 static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 840 {
 841         struct rza1_port *port = gpiochip_get_data(chip);
 842
 843         return rza1_pin_get(port, gpio);
 844 }
 845
 846 static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
 847                           int value)
 848 {
 849         struct rza1_port *port = gpiochip_get_data(chip);
 850
 851         rza1_pin_set(port, gpio, value);
 852 }
 853
 854 static const struct gpio_chip rza1_gpiochip_template = {
 855         .request                = rza1_gpio_request,
 856         .free                   = rza1_gpio_free,
 857         .get_direction          = rza1_gpio_get_direction,
 858         .direction_input        = rza1_gpio_direction_input,
 859         .direction_output       = rza1_gpio_direction_output,
 860         .get                    = rza1_gpio_get,
 861         .set                    = rza1_gpio_set,
 862 };
 863 /* ----------------------------------------------------------------------------
 864  * pinctrl operations
 865  */
 866
 867 /**
 868  * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
 869  *                            children sub-nodes
 870  *
 871  * @np: device tree node to parse
 872  */
 873 static int rza1_dt_node_pin_count(struct device_node *np)
 874 {
 875         struct device_node *child;
 876         struct property *of_pins;
 877         unsigned int npins;
 878
 879         of_pins = of_find_property(np, "pinmux", NULL);
 880         if (of_pins)
 881                 return of_pins->length / sizeof(u32);
 882
 883         npins = 0;
 884         for_each_child_of_node(np, child) {
 885                 of_pins = of_find_property(child, "pinmux", NULL);
 886                 if (!of_pins)
 887                         return -EINVAL;
 888
 889                 npins += of_pins->length / sizeof(u32);
 890         }
 891
 892         return npins;
 893 }
 894
 895 /**
 896  * rza1_parse_pmx_function() - parse a pin mux sub-node
 897  *
 898  * @rza1_pctl: RZ/A1 pin controller device
 899  * @np: of pmx sub-node
 900  * @mux_confs: array of pin mux configurations to fill with parsed info
 901  * @grpins: array of pin ids to mux
 902  */
 903 static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
 904                                   struct device_node *np,
 905                                   struct rza1_mux_conf *mux_confs,
 906                                   unsigned int *grpins)
 907 {
 908         struct pinctrl_dev *pctldev = rza1_pctl->pctl;
 909         char const *prop_name = "pinmux";
 910         unsigned long *pin_configs;
 911         unsigned int npin_configs;
 912         struct property *of_pins;
 913         unsigned int npins;
 914         u8 pinmux_flags;
 915         unsigned int i;
 916         int ret;
 917
 918         of_pins = of_find_property(np, prop_name, NULL);
 919         if (!of_pins) {
 920                 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
 921                 return -ENOENT;
 922         }
 923         npins = of_pins->length / sizeof(u32);
 924
 925         /*
 926          * Collect pin configuration properties: they apply to all pins in
 927          * this sub-node
 928          */
 929         ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
 930                                               &npin_configs);
 931         if (ret) {
 932                 dev_err(rza1_pctl->dev,
 933                         "Unable to parse pin configuration options for %s\n",
 934                         np->name);
 935                 return ret;
 936         }
 937
 938         /*
 939          * Create a mask with pinmux flags from pin configuration;
 940          * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
 941          * specified in device tree.
 942          */
 943         pinmux_flags = 0;
 944         for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
 945                 switch (pinconf_to_config_param(pin_configs[i])) {
 946                 case PIN_CONFIG_INPUT_ENABLE:
 947                         pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
 948                         break;
 949                 case PIN_CONFIG_OUTPUT:
 950                         pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
 951                 default:
 952                         break;
 953
 954                 }
 955
 956         kfree(pin_configs);
 957
 958         /* Collect pin positions and their mux settings. */
 959         for (i = 0; i < npins; ++i) {
 960                 u32 of_pinconf;
 961                 struct rza1_mux_conf *mux_conf = &mux_confs[i];
 962
 963                 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
 964                 if (ret)
 965                         return ret;
 966
 967                 mux_conf->id            = of_pinconf & MUX_PIN_ID_MASK;
 968                 mux_conf->port          = RZA1_PIN_ID_TO_PORT(mux_conf->id);
 969                 mux_conf->pin           = RZA1_PIN_ID_TO_PIN(mux_conf->id);
 970                 mux_conf->mux_func      = MUX_FUNC(of_pinconf);
 971                 mux_conf->mux_flags     = pinmux_flags;
 972
 973                 if (mux_conf->port >= RZA1_NPORTS ||
 974                     mux_conf->pin >= RZA1_PINS_PER_PORT) {
 975                         dev_err(rza1_pctl->dev,
 976                                 "Wrong port %u pin %u for %s property\n",
 977                                 mux_conf->port, mux_conf->pin, prop_name);
 978                         return -EINVAL;
 979                 }
 980
 981                 grpins[i] = mux_conf->id;
 982         }
 983
 984         return npins;
 985 }
 986
 987 /**
 988  * rza1_dt_node_to_map() - map a pin mux node to a function/group
 989  *
 990  * Parse and register a pin mux function.
 991  *
 992  * @pctldev: pin controller device
 993  * @np: device tree node to parse
 994  * @map: pointer to pin map (output)
 995  * @num_maps: number of collected maps (output)
 996  */
 997 static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
 998                                struct device_node *np,
 999                                struct pinctrl_map **map,
1000                                unsigned int *num_maps)
1001 {
1002         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1003         struct rza1_mux_conf *mux_confs, *mux_conf;
1004         unsigned int *grpins, *grpin;
1005         struct device_node *child;
1006         const char *grpname;
1007         const char **fngrps;
1008         int ret, npins;
1009         int gsel, fsel;
1010
1011         npins = rza1_dt_node_pin_count(np);
1012         if (npins < 0) {
1013                 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
1014                 return -EINVAL;
1015         }
1016
1017         /*
1018          * Functions are made of 1 group only;
1019          * in fact, functions and groups are identical for this pin controller
1020          * except that functions carry an array of per-pin mux configuration
1021          * settings.
1022          */
1023         mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1024                                  GFP_KERNEL);
1025         grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1026                               GFP_KERNEL);
1027         fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1028
1029         if (!mux_confs || !grpins || !fngrps)
1030                 return -ENOMEM;
1031
1032         /*
1033          * Parse the pinmux node.
1034          * If the node does not contain "pinmux" property (-ENOENT)
1035          * that property shall be specified in all its children sub-nodes.
1036          */
1037         mux_conf = &mux_confs[0];
1038         grpin = &grpins[0];
1039
1040         ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1041         if (ret == -ENOENT)
1042                 for_each_child_of_node(np, child) {
1043                         ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1044                                                      grpin);
1045                         if (ret < 0)
1046                                 return ret;
1047
1048                         grpin += ret;
1049                         mux_conf += ret;
1050                 }
1051         else if (ret < 0)
1052                 return ret;
1053
1054         /* Register pin group and function name to pinctrl_generic */
1055         grpname = np->name;
1056         fngrps[0] = grpname;
1057
1058         mutex_lock(&rza1_pctl->mutex);
1059         gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1060                                          NULL);
1061         if (gsel < 0) {
1062                 mutex_unlock(&rza1_pctl->mutex);
1063                 return gsel;
1064         }
1065
1066         fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1067                                            mux_confs);
1068         if (fsel < 0) {
1069                 ret = fsel;
1070                 goto remove_group;
1071         }
1072
1073         dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1074                                  grpname, npins);
1075
1076         /* Create map where to retrieve function and mux settings from */
1077         *num_maps = 0;
1078         *map = kzalloc(sizeof(**map), GFP_KERNEL);
1079         if (!*map) {
1080                 ret = -ENOMEM;
1081                 goto remove_function;
1082         }
1083
1084         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1085         (*map)->data.mux.group = np->name;
1086         (*map)->data.mux.function = np->name;
1087         *num_maps = 1;
1088         mutex_unlock(&rza1_pctl->mutex);
1089
1090         return 0;
1091
1092 remove_function:
1093         pinmux_generic_remove_function(pctldev, fsel);
1094
1095 remove_group:
1096         pinctrl_generic_remove_group(pctldev, gsel);
1097         mutex_unlock(&rza1_pctl->mutex);
1098
1099         dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1100                                  grpname);
1101
1102         return ret;
1103 }
1104
1105 static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1106                              struct pinctrl_map *map, unsigned int num_maps)
1107 {
1108         kfree(map);
1109 }
1110
1111 static const struct pinctrl_ops rza1_pinctrl_ops = {
1112         .get_groups_count       = pinctrl_generic_get_group_count,
1113         .get_group_name         = pinctrl_generic_get_group_name,
1114         .get_group_pins         = pinctrl_generic_get_group_pins,
1115         .dt_node_to_map         = rza1_dt_node_to_map,
1116         .dt_free_map            = rza1_dt_free_map,
1117 };
1118
1119 /* ----------------------------------------------------------------------------
1120  * pinmux operations
1121  */
1122
1123 /**
1124  * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1125  *
1126  * @pctldev: pin controller device
1127  * @selector: function selector
1128  * @group: group selector
1129  */
1130 static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1131                            unsigned int group)
1132 {
1133         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1134         struct rza1_mux_conf *mux_confs;
1135         struct function_desc *func;
1136         struct group_desc *grp;
1137         int i;
1138
1139         grp = pinctrl_generic_get_group(pctldev, group);
1140         if (!grp)
1141                 return -EINVAL;
1142
1143         func = pinmux_generic_get_function(pctldev, selector);
1144         if (!func)
1145                 return -EINVAL;
1146
1147         mux_confs = (struct rza1_mux_conf *)func->data;
1148         for (i = 0; i < grp->num_pins; ++i) {
1149                 int ret;
1150
1151                 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1152                 if (ret)
1153                         return ret;
1154         }
1155
1156         return 0;
1157 }
1158
1159 static const struct pinmux_ops rza1_pinmux_ops = {
1160         .get_functions_count    = pinmux_generic_get_function_count,
1161         .get_function_name      = pinmux_generic_get_function_name,
1162         .get_function_groups    = pinmux_generic_get_function_groups,
1163         .set_mux                = rza1_set_mux,
1164         .strict                 = true,
1165 };
1166
1167 /* ----------------------------------------------------------------------------
1168  * RZ/A1 pin controller driver operations
1169  */
1170
1171 static unsigned int rza1_count_gpio_chips(struct device_node *np)
1172 {
1173         struct device_node *child;
1174         unsigned int count = 0;
1175
1176         for_each_child_of_node(np, child) {
1177                 if (!of_property_read_bool(child, "gpio-controller"))
1178                         continue;
1179
1180                 count++;
1181         }
1182
1183         return count;
1184 }
1185
1186 /**
1187  * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1188  *
1189  * The gpio controller subnode shall provide a "gpio-ranges" list property as
1190  * defined by gpio device tree binding documentation.
1191  *
1192  * @rza1_pctl: RZ/A1 pin controller device
1193  * @np: of gpio-controller node
1194  * @chip: gpio chip to register to gpiolib
1195  * @range: pin range to register to pinctrl core
1196  */
1197 static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1198                                struct device_node *np,
1199                                struct gpio_chip *chip,
1200                                struct pinctrl_gpio_range *range)
1201 {
1202         const char *list_name = "gpio-ranges";
1203         struct of_phandle_args of_args;
1204         unsigned int gpioport;
1205         u32 pinctrl_base;
1206         int ret;
1207
1208         ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
1209         if (ret) {
1210                 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1211                         list_name);
1212                 return ret;
1213         }
1214
1215         /*
1216          * Find out on which port this gpio-chip maps to by inspecting the
1217          * second argument of the "gpio-ranges" property.
1218          */
1219         pinctrl_base = of_args.args[1];
1220         gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
1221         if (gpioport >= RZA1_NPORTS) {
1222                 dev_err(rza1_pctl->dev,
1223                         "Invalid values in property %s\n", list_name);
1224                 return -EINVAL;
1225         }
1226
1227         *chip           = rza1_gpiochip_template;
1228         chip->base      = -1;
1229         chip->label     = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s",
1230                                          np->name);
1231         chip->ngpio     = of_args.args[2];
1232         chip->of_node   = np;
1233         chip->parent    = rza1_pctl->dev;
1234
1235         range->id       = gpioport;
1236         range->name     = chip->label;
1237         range->pin_base = range->base = pinctrl_base;
1238         range->npins    = of_args.args[2];
1239         range->gc       = chip;
1240
1241         ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1242                                      &rza1_pctl->ports[gpioport]);
1243         if (ret)
1244                 return ret;
1245
1246         pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1247
1248         dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1249                  chip->label, chip->ngpio);
1250
1251         return 0;
1252 }
1253
1254 /**
1255  * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1256  *
1257  * @rza1_pctl: RZ/A1 pin controller device
1258  */
1259 static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1260 {
1261         struct device_node *np = rza1_pctl->dev->of_node;
1262         struct pinctrl_gpio_range *gpio_ranges;
1263         struct gpio_chip *gpio_chips;
1264         struct device_node *child;
1265         unsigned int ngpiochips;
1266         unsigned int i;
1267         int ret;
1268
1269         ngpiochips = rza1_count_gpio_chips(np);
1270         if (ngpiochips == 0) {
1271                 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1272                 return 0;
1273         }
1274
1275         gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1276                                   sizeof(*gpio_chips), GFP_KERNEL);
1277         gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1278                                    sizeof(*gpio_ranges), GFP_KERNEL);
1279         if (!gpio_chips || !gpio_ranges)
1280                 return -ENOMEM;
1281
1282         i = 0;
1283         for_each_child_of_node(np, child) {
1284                 if (!of_property_read_bool(child, "gpio-controller"))
1285                         continue;
1286
1287                 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1288                                           &gpio_ranges[i]);
1289                 if (ret)
1290                         goto gpiochip_remove;
1291
1292                 ++i;
1293         }
1294
1295         dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1296
1297         return 0;
1298
1299 gpiochip_remove:
1300         for (; i > 0; i--)
1301                 devm_gpiochip_remove(rza1_pctl->dev, &gpio_chips[i - 1]);
1302
1303         return ret;
1304 }
1305
1306 /**
1307  * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1308  *                           them to pinctrl and gpio cores.
1309  *
1310  * @rza1_pctl: RZ/A1 pin controller device
1311  */
1312 static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1313 {
1314         struct pinctrl_pin_desc *pins;
1315         struct rza1_port *ports;
1316         unsigned int i;
1317         int ret;
1318
1319         pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1320                             GFP_KERNEL);
1321         ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1322                              GFP_KERNEL);
1323         if (!pins || !ports)
1324                 return -ENOMEM;
1325
1326         rza1_pctl->pins         = pins;
1327         rza1_pctl->desc.pins    = pins;
1328         rza1_pctl->desc.npins   = RZA1_NPINS;
1329         rza1_pctl->ports        = ports;
1330
1331         for (i = 0; i < RZA1_NPINS; ++i) {
1332                 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1333                 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1334
1335                 pins[i].number = i;
1336                 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1337                                               "P%u-%u", port, pin);
1338
1339                 if (i % RZA1_PINS_PER_PORT == 0) {
1340                         /*
1341                          * Setup ports;
1342                          * they provide per-port lock and logical base address.
1343                          */
1344                         unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1345
1346                         ports[port_id].id       = port_id;
1347                         ports[port_id].base     = rza1_pctl->base;
1348                         ports[port_id].pins     = &pins[i];
1349                         spin_lock_init(&ports[port_id].lock);
1350                 }
1351         }
1352
1353         ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1354                                              rza1_pctl, &rza1_pctl->pctl);
1355         if (ret) {
1356                 dev_err(rza1_pctl->dev,
1357                         "RZ/A1 pin controller registration failed\n");
1358                 return ret;
1359         }
1360
1361         ret = pinctrl_enable(rza1_pctl->pctl);
1362         if (ret) {
1363                 dev_err(rza1_pctl->dev,
1364                         "RZ/A1 pin controller failed to start\n");
1365                 return ret;
1366         }
1367
1368         ret = rza1_gpio_register(rza1_pctl);
1369         if (ret) {
1370                 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1371                 return ret;
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int rza1_pinctrl_probe(struct platform_device *pdev)
1378 {
1379         struct rza1_pinctrl *rza1_pctl;
1380         struct resource *res;
1381         int ret;
1382
1383         rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1384         if (!rza1_pctl)
1385                 return -ENOMEM;
1386
1387         rza1_pctl->dev = &pdev->dev;
1388
1389         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390         rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
1391         if (IS_ERR(rza1_pctl->base))
1392                 return PTR_ERR(rza1_pctl->base);
1393
1394         mutex_init(&rza1_pctl->mutex);
1395
1396         platform_set_drvdata(pdev, rza1_pctl);
1397
1398         rza1_pctl->desc.name    = DRIVER_NAME;
1399         rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1400         rza1_pctl->desc.pmxops  = &rza1_pinmux_ops;
1401         rza1_pctl->desc.owner   = THIS_MODULE;
1402         rza1_pctl->data         = of_device_get_match_data(&pdev->dev);
1403
1404         ret = rza1_pinctrl_register(rza1_pctl);
1405         if (ret)
1406                 return ret;
1407
1408         dev_info(&pdev->dev,
1409                  "RZ/A1 pin controller and gpio successfully registered\n");
1410
1411         return 0;
1412 }
1413
1414 static const struct of_device_id rza1_pinctrl_of_match[] = {
1415         {
1416                 /* RZ/A1H, RZ/A1M */
1417                 .compatible     = "renesas,r7s72100-ports",
1418                 .data           = &rza1h_pmx_conf,
1419         },
1420         {
1421                 /* RZ/A1L */
1422                 .compatible     = "renesas,r7s72102-ports",
1423                 .data           = &rza1l_pmx_conf,
1424         },
1425         { }
1426 };
1427
1428 static struct platform_driver rza1_pinctrl_driver = {
1429         .driver = {
1430                 .name = DRIVER_NAME,
1431                 .of_match_table = rza1_pinctrl_of_match,
1432         },
1433         .probe = rza1_pinctrl_probe,
1434 };
1435
1436 static int __init rza1_pinctrl_init(void)
1437 {
1438         return platform_driver_register(&rza1_pinctrl_driver);
1439 }
1440 core_initcall(rza1_pinctrl_init);
1441
1442 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1443 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1444 MODULE_LICENSE("GPL v2");